2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
49 #include "util/string_buffer.h"
51 static const struct nir_shader_compiler_options nir_options
= {
52 .vertex_id_zero_based
= true,
58 .lower_pack_snorm_2x16
= true,
59 .lower_pack_snorm_4x8
= true,
60 .lower_pack_unorm_2x16
= true,
61 .lower_pack_unorm_4x8
= true,
62 .lower_unpack_snorm_2x16
= true,
63 .lower_unpack_snorm_4x8
= true,
64 .lower_unpack_unorm_2x16
= true,
65 .lower_unpack_unorm_4x8
= true,
66 .lower_extract_byte
= true,
67 .lower_extract_word
= true,
69 .max_unroll_iterations
= 32
72 VkResult
radv_CreateShaderModule(
74 const VkShaderModuleCreateInfo
* pCreateInfo
,
75 const VkAllocationCallbacks
* pAllocator
,
76 VkShaderModule
* pShaderModule
)
78 RADV_FROM_HANDLE(radv_device
, device
, _device
);
79 struct radv_shader_module
*module
;
81 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
82 assert(pCreateInfo
->flags
== 0);
84 module
= vk_alloc2(&device
->alloc
, pAllocator
,
85 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
86 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
88 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
91 module
->size
= pCreateInfo
->codeSize
;
92 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
94 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
96 *pShaderModule
= radv_shader_module_to_handle(module
);
101 void radv_DestroyShaderModule(
103 VkShaderModule _module
,
104 const VkAllocationCallbacks
* pAllocator
)
106 RADV_FROM_HANDLE(radv_device
, device
, _device
);
107 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
112 vk_free2(&device
->alloc
, pAllocator
, module
);
116 radv_optimize_nir(struct nir_shader
*shader
)
123 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
124 NIR_PASS_V(shader
, nir_lower_64bit_pack
);
125 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
126 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
128 NIR_PASS(progress
, shader
, nir_copy_prop
);
129 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
130 NIR_PASS(progress
, shader
, nir_opt_dce
);
131 if (nir_opt_trivial_continues(shader
)) {
133 NIR_PASS(progress
, shader
, nir_copy_prop
);
134 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
135 NIR_PASS(progress
, shader
, nir_opt_dce
);
137 NIR_PASS(progress
, shader
, nir_opt_if
);
138 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
139 NIR_PASS(progress
, shader
, nir_opt_cse
);
140 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
141 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
142 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
143 NIR_PASS(progress
, shader
, nir_opt_undef
);
144 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
145 if (shader
->options
->max_unroll_iterations
) {
146 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
152 radv_shader_compile_to_nir(struct radv_device
*device
,
153 struct radv_shader_module
*module
,
154 const char *entrypoint_name
,
155 gl_shader_stage stage
,
156 const VkSpecializationInfo
*spec_info
)
158 if (strcmp(entrypoint_name
, "main") != 0) {
159 radv_finishme("Multiple shaders per module not really supported");
163 nir_function
*entry_point
;
165 /* Some things such as our meta clear/blit code will give us a NIR
166 * shader directly. In that case, we just ignore the SPIR-V entirely
167 * and just use the NIR shader */
169 nir
->options
= &nir_options
;
170 nir_validate_shader(nir
);
172 assert(exec_list_length(&nir
->functions
) == 1);
173 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
174 entry_point
= exec_node_data(nir_function
, node
, node
);
176 uint32_t *spirv
= (uint32_t *) module
->data
;
177 assert(module
->size
% 4 == 0);
179 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
180 radv_print_spirv(spirv
, module
->size
, stderr
);
182 uint32_t num_spec_entries
= 0;
183 struct nir_spirv_specialization
*spec_entries
= NULL
;
184 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
185 num_spec_entries
= spec_info
->mapEntryCount
;
186 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
187 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
188 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
189 const void *data
= spec_info
->pData
+ entry
.offset
;
190 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
192 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
193 if (spec_info
->dataSize
== 8)
194 spec_entries
[i
].data64
= *(const uint64_t *)data
;
196 spec_entries
[i
].data32
= *(const uint32_t *)data
;
199 const struct spirv_to_nir_options spirv_options
= {
201 .draw_parameters
= true,
203 .image_read_without_format
= true,
204 .image_write_without_format
= true,
205 .tessellation
= true,
208 .variable_pointers
= true,
211 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
212 spec_entries
, num_spec_entries
,
213 stage
, entrypoint_name
,
214 &spirv_options
, &nir_options
);
215 nir
= entry_point
->shader
;
216 assert(nir
->info
.stage
== stage
);
217 nir_validate_shader(nir
);
221 /* We have to lower away local constant initializers right before we
222 * inline functions. That way they get properly initialized at the top
223 * of the function and not at the top of its caller.
225 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
226 NIR_PASS_V(nir
, nir_lower_returns
);
227 NIR_PASS_V(nir
, nir_inline_functions
);
229 /* Pick off the single entrypoint that we want */
230 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
231 if (func
!= entry_point
)
232 exec_node_remove(&func
->node
);
234 assert(exec_list_length(&nir
->functions
) == 1);
235 entry_point
->name
= ralloc_strdup(entry_point
, "main");
237 NIR_PASS_V(nir
, nir_remove_dead_variables
,
238 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
240 /* Now that we've deleted all but the main function, we can go ahead and
241 * lower the rest of the constant initializers.
243 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
244 NIR_PASS_V(nir
, nir_lower_system_values
);
245 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
248 /* Vulkan uses the separate-shader linking model */
249 nir
->info
.separate_shader
= true;
251 nir_shader_gather_info(nir
, entry_point
->impl
);
253 /* While it would be nice not to have this flag, we are constrained
254 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
257 bool llvm_has_working_vgpr_indexing
=
258 device
->physical_device
->rad_info
.chip_class
<= VI
;
260 /* TODO: Indirect indexing of GS inputs is unimplemented.
262 * TCS and TES load inputs directly from LDS or offchip memory, so
263 * indirect indexing is trivial.
265 nir_variable_mode indirect_mask
= 0;
266 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
267 (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
&&
268 nir
->info
.stage
!= MESA_SHADER_TESS_EVAL
&&
269 !llvm_has_working_vgpr_indexing
)) {
270 indirect_mask
|= nir_var_shader_in
;
272 if (!llvm_has_working_vgpr_indexing
&&
273 nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
274 indirect_mask
|= nir_var_shader_out
;
276 /* TODO: We shouldn't need to do this, however LLVM isn't currently
277 * smart enough to handle indirects without causing excess spilling
278 * causing the gpu to hang.
280 * See the following thread for more details of the problem:
281 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
283 indirect_mask
|= nir_var_local
;
285 nir_lower_indirect_derefs(nir
, indirect_mask
);
287 static const nir_lower_tex_options tex_options
= {
291 nir_lower_tex(nir
, &tex_options
);
293 nir_lower_vars_to_ssa(nir
);
294 nir_lower_var_copies(nir
);
295 nir_lower_global_vars_to_local(nir
);
296 nir_remove_dead_variables(nir
, nir_var_local
);
297 radv_optimize_nir(nir
);
303 radv_alloc_shader_memory(struct radv_device
*device
,
304 struct radv_shader_variant
*shader
)
306 mtx_lock(&device
->shader_slab_mutex
);
307 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
309 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
310 if (s
->bo_offset
- offset
>= shader
->code_size
) {
311 shader
->bo
= slab
->bo
;
312 shader
->bo_offset
= offset
;
313 list_addtail(&shader
->slab_list
, &s
->slab_list
);
314 mtx_unlock(&device
->shader_slab_mutex
);
315 return slab
->ptr
+ offset
;
317 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
319 if (slab
->size
- offset
>= shader
->code_size
) {
320 shader
->bo
= slab
->bo
;
321 shader
->bo_offset
= offset
;
322 list_addtail(&shader
->slab_list
, &slab
->shaders
);
323 mtx_unlock(&device
->shader_slab_mutex
);
324 return slab
->ptr
+ offset
;
328 mtx_unlock(&device
->shader_slab_mutex
);
329 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
331 slab
->size
= 256 * 1024;
332 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
333 RADEON_DOMAIN_VRAM
, RADEON_FLAG_NO_INTERPROCESS_SHARING
);
334 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
335 list_inithead(&slab
->shaders
);
337 mtx_lock(&device
->shader_slab_mutex
);
338 list_add(&slab
->slabs
, &device
->shader_slabs
);
340 shader
->bo
= slab
->bo
;
341 shader
->bo_offset
= 0;
342 list_add(&shader
->slab_list
, &slab
->shaders
);
343 mtx_unlock(&device
->shader_slab_mutex
);
348 radv_destroy_shader_slabs(struct radv_device
*device
)
350 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
351 device
->ws
->buffer_destroy(slab
->bo
);
354 mtx_destroy(&device
->shader_slab_mutex
);
358 radv_fill_shader_variant(struct radv_device
*device
,
359 struct radv_shader_variant
*variant
,
360 struct ac_shader_binary
*binary
,
361 gl_shader_stage stage
)
363 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
364 unsigned vgpr_comp_cnt
= 0;
366 if (scratch_enabled
&& !device
->llvm_supports_spill
)
367 radv_finishme("shader scratch support only available with LLVM 4.0");
369 variant
->code_size
= binary
->code_size
;
370 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
371 S_00B12C_SCRATCH_EN(scratch_enabled
);
373 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
374 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
375 S_00B848_DX10_CLAMP(1) |
376 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
379 case MESA_SHADER_TESS_EVAL
:
381 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
383 case MESA_SHADER_TESS_CTRL
:
384 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
385 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
387 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
389 case MESA_SHADER_VERTEX
:
390 case MESA_SHADER_GEOMETRY
:
391 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
393 case MESA_SHADER_FRAGMENT
:
395 case MESA_SHADER_COMPUTE
:
397 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
398 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
399 S_00B84C_TG_SIZE_EN(1) |
400 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
403 unreachable("unsupported shader type");
407 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
408 stage
== MESA_SHADER_GEOMETRY
) {
409 /* TODO: Figure out how many we actually need. */
410 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(3);
411 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(3) |
412 S_00B22C_OC_LDS_EN(1);
413 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
414 stage
== MESA_SHADER_TESS_CTRL
)
415 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
417 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
419 void *ptr
= radv_alloc_shader_memory(device
, variant
);
420 memcpy(ptr
, binary
->code
, binary
->code_size
);
423 static struct radv_shader_variant
*
424 shader_variant_create(struct radv_device
*device
,
425 struct radv_shader_module
*module
,
426 struct nir_shader
* const *shaders
,
428 gl_shader_stage stage
,
429 struct ac_nir_compiler_options
*options
,
432 unsigned *code_size_out
)
434 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
435 bool dump_shaders
= radv_can_dump_shader(device
, module
);
436 enum ac_target_machine_options tm_options
= 0;
437 struct radv_shader_variant
*variant
;
438 struct ac_shader_binary binary
;
439 LLVMTargetMachineRef tm
;
441 variant
= calloc(1, sizeof(struct radv_shader_variant
));
445 options
->family
= chip_family
;
446 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
448 if (options
->supports_spill
)
449 tm_options
|= AC_TM_SUPPORTS_SPILL
;
450 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
451 tm_options
|= AC_TM_SISCHED
;
452 tm
= ac_create_target_machine(chip_family
, tm_options
);
454 if (gs_copy_shader
) {
455 assert(shader_count
== 1);
456 ac_create_gs_copy_shader(tm
, *shaders
, &binary
, &variant
->config
,
457 &variant
->info
, options
, dump_shaders
);
459 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
460 &variant
->info
, shaders
, shader_count
, options
,
464 LLVMDisposeTargetMachine(tm
);
466 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
469 *code_out
= binary
.code
;
470 *code_size_out
= binary
.code_size
;
475 free(binary
.global_symbol_offsets
);
477 variant
->ref_count
= 1;
479 if (device
->keep_shader_info
) {
480 variant
->disasm_string
= binary
.disasm_string
;
481 if (!gs_copy_shader
&& !module
->nir
) {
482 variant
->nir
= *shaders
;
483 variant
->spirv
= (uint32_t *)module
->data
;
484 variant
->spirv_size
= module
->size
;
487 free(binary
.disasm_string
);
493 struct radv_shader_variant
*
494 radv_shader_variant_create(struct radv_device
*device
,
495 struct radv_shader_module
*module
,
496 struct nir_shader
*const *shaders
,
498 struct radv_pipeline_layout
*layout
,
499 const struct ac_shader_variant_key
*key
,
501 unsigned *code_size_out
)
503 struct ac_nir_compiler_options options
= {0};
505 options
.layout
= layout
;
509 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
510 options
.supports_spill
= device
->llvm_supports_spill
;
512 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
513 &options
, false, code_out
, code_size_out
);
516 struct radv_shader_variant
*
517 radv_create_gs_copy_shader(struct radv_device
*device
,
518 struct nir_shader
*shader
,
520 unsigned *code_size_out
,
523 struct ac_nir_compiler_options options
= {0};
525 options
.key
.has_multiview_view_index
= multiview
;
527 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
528 &options
, true, code_out
, code_size_out
);
532 radv_shader_variant_destroy(struct radv_device
*device
,
533 struct radv_shader_variant
*variant
)
535 if (!p_atomic_dec_zero(&variant
->ref_count
))
538 mtx_lock(&device
->shader_slab_mutex
);
539 list_del(&variant
->slab_list
);
540 mtx_unlock(&device
->shader_slab_mutex
);
542 ralloc_free(variant
->nir
);
543 free(variant
->disasm_string
);
548 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
551 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
552 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
553 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
554 case MESA_SHADER_COMPUTE
: return "Compute Shader";
555 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
556 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
558 return "Unknown shader";
563 get_total_sgprs(struct radv_device
*device
)
565 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
572 generate_shader_stats(struct radv_device
*device
,
573 struct radv_shader_variant
*variant
,
574 gl_shader_stage stage
,
575 struct _mesa_string_buffer
*buf
)
577 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
578 struct ac_shader_config
*conf
;
579 unsigned max_simd_waves
;
580 unsigned lds_per_wave
= 0;
582 switch (device
->physical_device
->rad_info
.family
) {
583 /* These always have 8 waves: */
593 conf
= &variant
->config
;
595 if (stage
== MESA_SHADER_FRAGMENT
) {
596 lds_per_wave
= conf
->lds_size
* lds_increment
+
597 align(variant
->info
.fs
.num_interp
* 48,
602 max_simd_waves
= MIN2(max_simd_waves
, get_total_sgprs(device
) / conf
->num_sgprs
);
605 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
607 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
611 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
613 if (stage
== MESA_SHADER_FRAGMENT
) {
614 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
615 "SPI_PS_INPUT_ADDR = 0x%04x\n"
616 "SPI_PS_INPUT_ENA = 0x%04x\n",
617 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
620 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
623 "Spilled SGPRs: %d\n"
624 "Spilled VGPRs: %d\n"
625 "Code Size: %d bytes\n"
627 "Scratch: %d bytes per wave\n"
629 "********************\n\n\n",
630 conf
->num_sgprs
, conf
->num_vgprs
,
631 conf
->spilled_sgprs
, conf
->spilled_vgprs
, variant
->code_size
,
632 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
637 radv_shader_dump_stats(struct radv_device
*device
,
638 struct radv_shader_variant
*variant
,
639 gl_shader_stage stage
,
642 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
644 generate_shader_stats(device
, variant
, stage
, buf
);
646 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
647 fprintf(file
, "%s", buf
->buf
);
649 _mesa_string_buffer_destroy(buf
);
653 radv_GetShaderInfoAMD(VkDevice _device
,
654 VkPipeline _pipeline
,
655 VkShaderStageFlagBits shaderStage
,
656 VkShaderInfoTypeAMD infoType
,
660 RADV_FROM_HANDLE(radv_device
, device
, _device
);
661 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
662 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
663 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
664 struct _mesa_string_buffer
*buf
;
665 VkResult result
= VK_SUCCESS
;
667 /* Spec doesn't indicate what to do if the stage is invalid, so just
668 * return no info for this. */
670 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
673 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
675 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
677 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
678 struct ac_shader_config
*conf
= &variant
->config
;
680 VkShaderStatisticsInfoAMD statistics
= {};
681 statistics
.shaderStageMask
= shaderStage
;
682 statistics
.numPhysicalVgprs
= 256;
683 statistics
.numPhysicalSgprs
= get_total_sgprs(device
);
684 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
686 if (stage
== MESA_SHADER_COMPUTE
) {
687 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
688 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
690 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
691 ceil(workgroup_size
/ statistics
.numPhysicalVgprs
);
693 statistics
.computeWorkGroupSize
[0] = local_size
[0];
694 statistics
.computeWorkGroupSize
[1] = local_size
[1];
695 statistics
.computeWorkGroupSize
[2] = local_size
[2];
697 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
700 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
701 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
702 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
703 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
704 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
706 size_t size
= *pInfoSize
;
707 *pInfoSize
= sizeof(statistics
);
709 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
711 if (size
< *pInfoSize
)
712 result
= VK_INCOMPLETE
;
716 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
717 buf
= _mesa_string_buffer_create(NULL
, 1024);
719 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
720 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
721 generate_shader_stats(device
, variant
, stage
, buf
);
723 /* Need to include the null terminator. */
724 size_t length
= buf
->length
+ 1;
729 size_t size
= *pInfoSize
;
732 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
735 result
= VK_INCOMPLETE
;
738 _mesa_string_buffer_destroy(buf
);
741 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
742 result
= VK_ERROR_FEATURE_NOT_PRESENT
;