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radv: use nir_opt_find_array_copies()
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_sub = true,
62 .lower_pack_snorm_2x16 = true,
63 .lower_pack_snorm_4x8 = true,
64 .lower_pack_unorm_2x16 = true,
65 .lower_pack_unorm_4x8 = true,
66 .lower_unpack_snorm_2x16 = true,
67 .lower_unpack_snorm_4x8 = true,
68 .lower_unpack_unorm_2x16 = true,
69 .lower_unpack_unorm_4x8 = true,
70 .lower_extract_byte = true,
71 .lower_extract_word = true,
72 .lower_ffma = true,
73 .lower_fpow = true,
74 .max_unroll_iterations = 32
75 };
76
77 VkResult radv_CreateShaderModule(
78 VkDevice _device,
79 const VkShaderModuleCreateInfo* pCreateInfo,
80 const VkAllocationCallbacks* pAllocator,
81 VkShaderModule* pShaderModule)
82 {
83 RADV_FROM_HANDLE(radv_device, device, _device);
84 struct radv_shader_module *module;
85
86 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
87 assert(pCreateInfo->flags == 0);
88
89 module = vk_alloc2(&device->alloc, pAllocator,
90 sizeof(*module) + pCreateInfo->codeSize, 8,
91 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
92 if (module == NULL)
93 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
94
95 module->nir = NULL;
96 module->size = pCreateInfo->codeSize;
97 memcpy(module->data, pCreateInfo->pCode, module->size);
98
99 _mesa_sha1_compute(module->data, module->size, module->sha1);
100
101 *pShaderModule = radv_shader_module_to_handle(module);
102
103 return VK_SUCCESS;
104 }
105
106 void radv_DestroyShaderModule(
107 VkDevice _device,
108 VkShaderModule _module,
109 const VkAllocationCallbacks* pAllocator)
110 {
111 RADV_FROM_HANDLE(radv_device, device, _device);
112 RADV_FROM_HANDLE(radv_shader_module, module, _module);
113
114 if (!module)
115 return;
116
117 vk_free2(&device->alloc, pAllocator, module);
118 }
119
120 void
121 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
122 bool allow_copies)
123 {
124 bool progress;
125
126 do {
127 progress = false;
128
129 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
130 NIR_PASS_V(shader, nir_lower_pack);
131
132 if (allow_copies) {
133 /* Only run this pass in the first call to
134 * radv_optimize_nir. Later calls assume that we've
135 * lowered away any copy_deref instructions and we
136 * don't want to introduce any more.
137 */
138 NIR_PASS(progress, shader, nir_opt_find_array_copies);
139 }
140
141 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
142 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
143
144 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
145 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
146
147 NIR_PASS(progress, shader, nir_copy_prop);
148 NIR_PASS(progress, shader, nir_opt_remove_phis);
149 NIR_PASS(progress, shader, nir_opt_dce);
150 if (nir_opt_trivial_continues(shader)) {
151 progress = true;
152 NIR_PASS(progress, shader, nir_copy_prop);
153 NIR_PASS(progress, shader, nir_opt_remove_phis);
154 NIR_PASS(progress, shader, nir_opt_dce);
155 }
156 NIR_PASS(progress, shader, nir_opt_if);
157 NIR_PASS(progress, shader, nir_opt_dead_cf);
158 NIR_PASS(progress, shader, nir_opt_cse);
159 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
160 NIR_PASS(progress, shader, nir_opt_algebraic);
161 NIR_PASS(progress, shader, nir_opt_constant_folding);
162 NIR_PASS(progress, shader, nir_opt_undef);
163 NIR_PASS(progress, shader, nir_opt_conditional_discard);
164 if (shader->options->max_unroll_iterations) {
165 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
166 }
167 } while (progress && !optimize_conservatively);
168
169 NIR_PASS(progress, shader, nir_opt_shrink_load);
170 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
171 }
172
173 nir_shader *
174 radv_shader_compile_to_nir(struct radv_device *device,
175 struct radv_shader_module *module,
176 const char *entrypoint_name,
177 gl_shader_stage stage,
178 const VkSpecializationInfo *spec_info,
179 const VkPipelineCreateFlags flags)
180 {
181 nir_shader *nir;
182 nir_function *entry_point;
183 if (module->nir) {
184 /* Some things such as our meta clear/blit code will give us a NIR
185 * shader directly. In that case, we just ignore the SPIR-V entirely
186 * and just use the NIR shader */
187 nir = module->nir;
188 nir->options = &nir_options;
189 nir_validate_shader(nir);
190
191 assert(exec_list_length(&nir->functions) == 1);
192 struct exec_node *node = exec_list_get_head(&nir->functions);
193 entry_point = exec_node_data(nir_function, node, node);
194 } else {
195 uint32_t *spirv = (uint32_t *) module->data;
196 assert(module->size % 4 == 0);
197
198 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
199 radv_print_spirv(spirv, module->size, stderr);
200
201 uint32_t num_spec_entries = 0;
202 struct nir_spirv_specialization *spec_entries = NULL;
203 if (spec_info && spec_info->mapEntryCount > 0) {
204 num_spec_entries = spec_info->mapEntryCount;
205 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
206 for (uint32_t i = 0; i < num_spec_entries; i++) {
207 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
208 const void *data = spec_info->pData + entry.offset;
209 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
210
211 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
212 if (spec_info->dataSize == 8)
213 spec_entries[i].data64 = *(const uint64_t *)data;
214 else
215 spec_entries[i].data32 = *(const uint32_t *)data;
216 }
217 }
218 const struct spirv_to_nir_options spirv_options = {
219 .caps = {
220 .device_group = true,
221 .draw_parameters = true,
222 .float64 = true,
223 .image_read_without_format = true,
224 .image_write_without_format = true,
225 .tessellation = true,
226 .int64 = true,
227 .int16 = true,
228 .multiview = true,
229 .subgroup_arithmetic = true,
230 .subgroup_ballot = true,
231 .subgroup_basic = true,
232 .subgroup_quad = true,
233 .subgroup_shuffle = true,
234 .subgroup_vote = true,
235 .variable_pointers = true,
236 .gcn_shader = true,
237 .trinary_minmax = true,
238 .shader_viewport_index_layer = true,
239 .descriptor_array_dynamic_indexing = true,
240 .runtime_descriptor_array = true,
241 .stencil_export = true,
242 .storage_16bit = true,
243 },
244 };
245 entry_point = spirv_to_nir(spirv, module->size / 4,
246 spec_entries, num_spec_entries,
247 stage, entrypoint_name,
248 &spirv_options, &nir_options);
249 nir = entry_point->shader;
250 assert(nir->info.stage == stage);
251 nir_validate_shader(nir);
252
253 free(spec_entries);
254
255 /* We have to lower away local constant initializers right before we
256 * inline functions. That way they get properly initialized at the top
257 * of the function and not at the top of its caller.
258 */
259 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
260 NIR_PASS_V(nir, nir_lower_returns);
261 NIR_PASS_V(nir, nir_inline_functions);
262 NIR_PASS_V(nir, nir_copy_prop);
263
264 /* Pick off the single entrypoint that we want */
265 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
266 if (func != entry_point)
267 exec_node_remove(&func->node);
268 }
269 assert(exec_list_length(&nir->functions) == 1);
270 entry_point->name = ralloc_strdup(entry_point, "main");
271
272 /* Make sure we lower constant initializers on output variables so that
273 * nir_remove_dead_variables below sees the corresponding stores
274 */
275 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
276
277 /* Now that we've deleted all but the main function, we can go ahead and
278 * lower the rest of the constant initializers.
279 */
280 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
281
282 /* Split member structs. We do this before lower_io_to_temporaries so that
283 * it doesn't lower system values to temporaries by accident.
284 */
285 NIR_PASS_V(nir, nir_split_var_copies);
286 NIR_PASS_V(nir, nir_split_per_member_structs);
287
288 NIR_PASS_V(nir, nir_remove_dead_variables,
289 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
290
291 NIR_PASS_V(nir, nir_lower_system_values);
292 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
293 }
294
295 /* Vulkan uses the separate-shader linking model */
296 nir->info.separate_shader = true;
297
298 nir_shader_gather_info(nir, entry_point->impl);
299
300 static const nir_lower_tex_options tex_options = {
301 .lower_txp = ~0,
302 };
303
304 nir_lower_tex(nir, &tex_options);
305
306 nir_lower_vars_to_ssa(nir);
307
308 if (nir->info.stage == MESA_SHADER_VERTEX ||
309 nir->info.stage == MESA_SHADER_GEOMETRY) {
310 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
311 nir_shader_get_entrypoint(nir), true, true);
312 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
313 nir->info.stage == MESA_SHADER_FRAGMENT) {
314 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
315 nir_shader_get_entrypoint(nir), true, false);
316 }
317
318 nir_split_var_copies(nir);
319
320 nir_lower_global_vars_to_local(nir);
321 nir_remove_dead_variables(nir, nir_var_local);
322 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
323 .subgroup_size = 64,
324 .ballot_bit_size = 64,
325 .lower_to_scalar = 1,
326 .lower_subgroup_masks = 1,
327 .lower_shuffle = 1,
328 .lower_shuffle_to_32bit = 1,
329 .lower_vote_eq_to_ballot = 1,
330 });
331
332 nir_lower_load_const_to_scalar(nir);
333
334 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
335 radv_optimize_nir(nir, false, true);
336
337 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
338 * to remove any copies introduced by nir_opt_find_array_copies().
339 */
340 nir_lower_var_copies(nir);
341
342 /* Indirect lowering must be called after the radv_optimize_nir() loop
343 * has been called at least once. Otherwise indirect lowering can
344 * bloat the instruction count of the loop and cause it to be
345 * considered too large for unrolling.
346 */
347 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
348 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
349
350 return nir;
351 }
352
353 void *
354 radv_alloc_shader_memory(struct radv_device *device,
355 struct radv_shader_variant *shader)
356 {
357 mtx_lock(&device->shader_slab_mutex);
358 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
359 uint64_t offset = 0;
360 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
361 if (s->bo_offset - offset >= shader->code_size) {
362 shader->bo = slab->bo;
363 shader->bo_offset = offset;
364 list_addtail(&shader->slab_list, &s->slab_list);
365 mtx_unlock(&device->shader_slab_mutex);
366 return slab->ptr + offset;
367 }
368 offset = align_u64(s->bo_offset + s->code_size, 256);
369 }
370 if (slab->size - offset >= shader->code_size) {
371 shader->bo = slab->bo;
372 shader->bo_offset = offset;
373 list_addtail(&shader->slab_list, &slab->shaders);
374 mtx_unlock(&device->shader_slab_mutex);
375 return slab->ptr + offset;
376 }
377 }
378
379 mtx_unlock(&device->shader_slab_mutex);
380 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
381
382 slab->size = 256 * 1024;
383 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
384 RADEON_DOMAIN_VRAM,
385 RADEON_FLAG_NO_INTERPROCESS_SHARING |
386 (device->physical_device->cpdma_prefetch_writes_memory ?
387 0 : RADEON_FLAG_READ_ONLY));
388 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
389 list_inithead(&slab->shaders);
390
391 mtx_lock(&device->shader_slab_mutex);
392 list_add(&slab->slabs, &device->shader_slabs);
393
394 shader->bo = slab->bo;
395 shader->bo_offset = 0;
396 list_add(&shader->slab_list, &slab->shaders);
397 mtx_unlock(&device->shader_slab_mutex);
398 return slab->ptr;
399 }
400
401 void
402 radv_destroy_shader_slabs(struct radv_device *device)
403 {
404 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
405 device->ws->buffer_destroy(slab->bo);
406 free(slab);
407 }
408 mtx_destroy(&device->shader_slab_mutex);
409 }
410
411 /* For the UMR disassembler. */
412 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
413 #define DEBUGGER_NUM_MARKERS 5
414
415 static unsigned
416 radv_get_shader_binary_size(struct ac_shader_binary *binary)
417 {
418 return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
419 }
420
421 static void
422 radv_fill_shader_variant(struct radv_device *device,
423 struct radv_shader_variant *variant,
424 struct ac_shader_binary *binary,
425 gl_shader_stage stage)
426 {
427 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
428 struct radv_shader_info *info = &variant->info.info;
429 unsigned vgpr_comp_cnt = 0;
430
431 variant->code_size = radv_get_shader_binary_size(binary);
432 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
433 S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
434 S_00B12C_SCRATCH_EN(scratch_enabled);
435
436 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
437 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
438 S_00B848_DX10_CLAMP(1) |
439 S_00B848_FLOAT_MODE(variant->config.float_mode);
440
441 switch (stage) {
442 case MESA_SHADER_TESS_EVAL:
443 vgpr_comp_cnt = 3;
444 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
445 break;
446 case MESA_SHADER_TESS_CTRL:
447 if (device->physical_device->rad_info.chip_class >= GFX9) {
448 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
449 } else {
450 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
451 }
452 break;
453 case MESA_SHADER_VERTEX:
454 case MESA_SHADER_GEOMETRY:
455 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
456 break;
457 case MESA_SHADER_FRAGMENT:
458 break;
459 case MESA_SHADER_COMPUTE:
460 variant->rsrc2 |=
461 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
462 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
463 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
464 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
465 info->cs.uses_thread_id[1] ? 1 : 0) |
466 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
467 S_00B84C_LDS_SIZE(variant->config.lds_size);
468 break;
469 default:
470 unreachable("unsupported shader type");
471 break;
472 }
473
474 if (device->physical_device->rad_info.chip_class >= GFX9 &&
475 stage == MESA_SHADER_GEOMETRY) {
476 unsigned es_type = variant->info.gs.es_type;
477 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
478
479 if (es_type == MESA_SHADER_VERTEX) {
480 es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
481 } else if (es_type == MESA_SHADER_TESS_EVAL) {
482 es_vgpr_comp_cnt = 3;
483 } else {
484 unreachable("invalid shader ES type");
485 }
486
487 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
488 * VGPR[0:4] are always loaded.
489 */
490 if (info->uses_invocation_id) {
491 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
492 } else if (info->uses_prim_id) {
493 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
494 } else if (variant->info.gs.vertices_in >= 3) {
495 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
496 } else {
497 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
498 }
499
500 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
501 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
502 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
503 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
504 stage == MESA_SHADER_TESS_CTRL) {
505 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
506 } else {
507 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
508 }
509
510 void *ptr = radv_alloc_shader_memory(device, variant);
511 memcpy(ptr, binary->code, binary->code_size);
512
513 /* Add end-of-code markers for the UMR disassembler. */
514 uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
515 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
516 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
517
518 }
519
520 static void radv_init_llvm_target()
521 {
522 LLVMInitializeAMDGPUTargetInfo();
523 LLVMInitializeAMDGPUTarget();
524 LLVMInitializeAMDGPUTargetMC();
525 LLVMInitializeAMDGPUAsmPrinter();
526
527 /* For inline assembly. */
528 LLVMInitializeAMDGPUAsmParser();
529
530 /* Workaround for bug in llvm 4.0 that causes image intrinsics
531 * to disappear.
532 * https://reviews.llvm.org/D26348
533 *
534 * Workaround for bug in llvm that causes the GPU to hang in presence
535 * of nested loops because there is an exec mask issue. The proper
536 * solution is to fix LLVM but this might require a bunch of work.
537 * https://bugs.llvm.org/show_bug.cgi?id=37744
538 *
539 * "mesa" is the prefix for error messages.
540 */
541 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
542 "-amdgpu-skip-threshold=1" };
543 LLVMParseCommandLineOptions(3, argv, NULL);
544 }
545
546 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
547
548 static void radv_init_llvm_once(void)
549 {
550 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
551 }
552
553 static struct radv_shader_variant *
554 shader_variant_create(struct radv_device *device,
555 struct radv_shader_module *module,
556 struct nir_shader * const *shaders,
557 int shader_count,
558 gl_shader_stage stage,
559 struct radv_nir_compiler_options *options,
560 bool gs_copy_shader,
561 void **code_out,
562 unsigned *code_size_out)
563 {
564 enum radeon_family chip_family = device->physical_device->rad_info.family;
565 enum ac_target_machine_options tm_options = 0;
566 struct radv_shader_variant *variant;
567 struct ac_shader_binary binary;
568 struct ac_llvm_compiler ac_llvm;
569 bool thread_compiler;
570 variant = calloc(1, sizeof(struct radv_shader_variant));
571 if (!variant)
572 return NULL;
573
574 options->family = chip_family;
575 options->chip_class = device->physical_device->rad_info.chip_class;
576 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
577 options->dump_preoptir = options->dump_shader &&
578 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
579 options->record_llvm_ir = device->keep_shader_info;
580 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
581 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
582 options->address32_hi = device->physical_device->rad_info.address32_hi;
583
584 if (options->supports_spill)
585 tm_options |= AC_TM_SUPPORTS_SPILL;
586 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
587 tm_options |= AC_TM_SISCHED;
588 if (options->check_ir)
589 tm_options |= AC_TM_CHECK_IR;
590
591 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
592 radv_init_llvm_once();
593 radv_init_llvm_compiler(&ac_llvm, false,
594 thread_compiler,
595 chip_family, tm_options);
596 if (gs_copy_shader) {
597 assert(shader_count == 1);
598 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
599 &variant->config, &variant->info,
600 options);
601 } else {
602 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
603 &variant->info, shaders, shader_count,
604 options);
605 }
606
607 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
608
609 radv_fill_shader_variant(device, variant, &binary, stage);
610
611 if (code_out) {
612 *code_out = binary.code;
613 *code_size_out = binary.code_size;
614 } else
615 free(binary.code);
616 free(binary.config);
617 free(binary.rodata);
618 free(binary.global_symbol_offsets);
619 free(binary.relocs);
620 variant->ref_count = 1;
621
622 if (device->keep_shader_info) {
623 variant->disasm_string = binary.disasm_string;
624 variant->llvm_ir_string = binary.llvm_ir_string;
625 if (!gs_copy_shader && !module->nir) {
626 variant->nir = *shaders;
627 variant->spirv = (uint32_t *)module->data;
628 variant->spirv_size = module->size;
629 }
630 } else {
631 free(binary.disasm_string);
632 }
633
634 return variant;
635 }
636
637 struct radv_shader_variant *
638 radv_shader_variant_create(struct radv_device *device,
639 struct radv_shader_module *module,
640 struct nir_shader *const *shaders,
641 int shader_count,
642 struct radv_pipeline_layout *layout,
643 const struct radv_shader_variant_key *key,
644 void **code_out,
645 unsigned *code_size_out)
646 {
647 struct radv_nir_compiler_options options = {0};
648
649 options.layout = layout;
650 if (key)
651 options.key = *key;
652
653 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
654 options.supports_spill = true;
655
656 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
657 &options, false, code_out, code_size_out);
658 }
659
660 struct radv_shader_variant *
661 radv_create_gs_copy_shader(struct radv_device *device,
662 struct nir_shader *shader,
663 void **code_out,
664 unsigned *code_size_out,
665 bool multiview)
666 {
667 struct radv_nir_compiler_options options = {0};
668
669 options.key.has_multiview_view_index = multiview;
670
671 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
672 &options, true, code_out, code_size_out);
673 }
674
675 void
676 radv_shader_variant_destroy(struct radv_device *device,
677 struct radv_shader_variant *variant)
678 {
679 if (!p_atomic_dec_zero(&variant->ref_count))
680 return;
681
682 mtx_lock(&device->shader_slab_mutex);
683 list_del(&variant->slab_list);
684 mtx_unlock(&device->shader_slab_mutex);
685
686 ralloc_free(variant->nir);
687 free(variant->disasm_string);
688 free(variant->llvm_ir_string);
689 free(variant);
690 }
691
692 const char *
693 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
694 {
695 switch (stage) {
696 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
697 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
698 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
699 case MESA_SHADER_COMPUTE: return "Compute Shader";
700 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
701 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
702 default:
703 return "Unknown shader";
704 };
705 }
706
707 static void
708 generate_shader_stats(struct radv_device *device,
709 struct radv_shader_variant *variant,
710 gl_shader_stage stage,
711 struct _mesa_string_buffer *buf)
712 {
713 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
714 struct ac_shader_config *conf;
715 unsigned max_simd_waves;
716 unsigned lds_per_wave = 0;
717
718 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
719
720 conf = &variant->config;
721
722 if (stage == MESA_SHADER_FRAGMENT) {
723 lds_per_wave = conf->lds_size * lds_increment +
724 align(variant->info.fs.num_interp * 48,
725 lds_increment);
726 }
727
728 if (conf->num_sgprs)
729 max_simd_waves =
730 MIN2(max_simd_waves,
731 radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
732
733 if (conf->num_vgprs)
734 max_simd_waves =
735 MIN2(max_simd_waves,
736 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
737
738 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
739 * that PS can use.
740 */
741 if (lds_per_wave)
742 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
743
744 if (stage == MESA_SHADER_FRAGMENT) {
745 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
746 "SPI_PS_INPUT_ADDR = 0x%04x\n"
747 "SPI_PS_INPUT_ENA = 0x%04x\n",
748 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
749 }
750
751 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
752 "SGPRS: %d\n"
753 "VGPRS: %d\n"
754 "Spilled SGPRs: %d\n"
755 "Spilled VGPRs: %d\n"
756 "PrivMem VGPRS: %d\n"
757 "Code Size: %d bytes\n"
758 "LDS: %d blocks\n"
759 "Scratch: %d bytes per wave\n"
760 "Max Waves: %d\n"
761 "********************\n\n\n",
762 conf->num_sgprs, conf->num_vgprs,
763 conf->spilled_sgprs, conf->spilled_vgprs,
764 variant->info.private_mem_vgprs, variant->code_size,
765 conf->lds_size, conf->scratch_bytes_per_wave,
766 max_simd_waves);
767 }
768
769 void
770 radv_shader_dump_stats(struct radv_device *device,
771 struct radv_shader_variant *variant,
772 gl_shader_stage stage,
773 FILE *file)
774 {
775 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
776
777 generate_shader_stats(device, variant, stage, buf);
778
779 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
780 fprintf(file, "%s", buf->buf);
781
782 _mesa_string_buffer_destroy(buf);
783 }
784
785 VkResult
786 radv_GetShaderInfoAMD(VkDevice _device,
787 VkPipeline _pipeline,
788 VkShaderStageFlagBits shaderStage,
789 VkShaderInfoTypeAMD infoType,
790 size_t* pInfoSize,
791 void* pInfo)
792 {
793 RADV_FROM_HANDLE(radv_device, device, _device);
794 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
795 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
796 struct radv_shader_variant *variant = pipeline->shaders[stage];
797 struct _mesa_string_buffer *buf;
798 VkResult result = VK_SUCCESS;
799
800 /* Spec doesn't indicate what to do if the stage is invalid, so just
801 * return no info for this. */
802 if (!variant)
803 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
804
805 switch (infoType) {
806 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
807 if (!pInfo) {
808 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
809 } else {
810 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
811 struct ac_shader_config *conf = &variant->config;
812
813 VkShaderStatisticsInfoAMD statistics = {};
814 statistics.shaderStageMask = shaderStage;
815 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
816 statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
817 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
818
819 if (stage == MESA_SHADER_COMPUTE) {
820 unsigned *local_size = variant->nir->info.cs.local_size;
821 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
822
823 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
824 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
825
826 statistics.computeWorkGroupSize[0] = local_size[0];
827 statistics.computeWorkGroupSize[1] = local_size[1];
828 statistics.computeWorkGroupSize[2] = local_size[2];
829 } else {
830 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
831 }
832
833 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
834 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
835 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
836 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
837 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
838
839 size_t size = *pInfoSize;
840 *pInfoSize = sizeof(statistics);
841
842 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
843
844 if (size < *pInfoSize)
845 result = VK_INCOMPLETE;
846 }
847
848 break;
849 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
850 buf = _mesa_string_buffer_create(NULL, 1024);
851
852 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
853 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
854 generate_shader_stats(device, variant, stage, buf);
855
856 /* Need to include the null terminator. */
857 size_t length = buf->length + 1;
858
859 if (!pInfo) {
860 *pInfoSize = length;
861 } else {
862 size_t size = *pInfoSize;
863 *pInfoSize = length;
864
865 memcpy(pInfo, buf->buf, MIN2(size, length));
866
867 if (size < length)
868 result = VK_INCOMPLETE;
869 }
870
871 _mesa_string_buffer_destroy(buf);
872 break;
873 default:
874 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
875 result = VK_ERROR_FEATURE_NOT_PRESENT;
876 break;
877 }
878
879 return result;
880 }