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6176a2e590d5b42c857b8f39e093a2440dbc6ca3
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 static const struct nir_shader_compiler_options nir_options = {
50 .vertex_id_zero_based = true,
51 .lower_scmp = true,
52 .lower_flrp32 = true,
53 .lower_fsat = true,
54 .lower_fdiv = true,
55 .lower_sub = true,
56 .lower_pack_snorm_2x16 = true,
57 .lower_pack_snorm_4x8 = true,
58 .lower_pack_unorm_2x16 = true,
59 .lower_pack_unorm_4x8 = true,
60 .lower_unpack_snorm_2x16 = true,
61 .lower_unpack_snorm_4x8 = true,
62 .lower_unpack_unorm_2x16 = true,
63 .lower_unpack_unorm_4x8 = true,
64 .lower_extract_byte = true,
65 .lower_extract_word = true,
66 .lower_ffma = true,
67 .max_unroll_iterations = 32
68 };
69
70 VkResult radv_CreateShaderModule(
71 VkDevice _device,
72 const VkShaderModuleCreateInfo* pCreateInfo,
73 const VkAllocationCallbacks* pAllocator,
74 VkShaderModule* pShaderModule)
75 {
76 RADV_FROM_HANDLE(radv_device, device, _device);
77 struct radv_shader_module *module;
78
79 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
80 assert(pCreateInfo->flags == 0);
81
82 module = vk_alloc2(&device->alloc, pAllocator,
83 sizeof(*module) + pCreateInfo->codeSize, 8,
84 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
85 if (module == NULL)
86 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
87
88 module->nir = NULL;
89 module->size = pCreateInfo->codeSize;
90 memcpy(module->data, pCreateInfo->pCode, module->size);
91
92 _mesa_sha1_compute(module->data, module->size, module->sha1);
93
94 *pShaderModule = radv_shader_module_to_handle(module);
95
96 return VK_SUCCESS;
97 }
98
99 void radv_DestroyShaderModule(
100 VkDevice _device,
101 VkShaderModule _module,
102 const VkAllocationCallbacks* pAllocator)
103 {
104 RADV_FROM_HANDLE(radv_device, device, _device);
105 RADV_FROM_HANDLE(radv_shader_module, module, _module);
106
107 if (!module)
108 return;
109
110 vk_free2(&device->alloc, pAllocator, module);
111 }
112
113 void
114 radv_optimize_nir(struct nir_shader *shader)
115 {
116 bool progress;
117
118 do {
119 progress = false;
120
121 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
122 NIR_PASS_V(shader, nir_lower_64bit_pack);
123 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
124 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
125
126 NIR_PASS(progress, shader, nir_copy_prop);
127 NIR_PASS(progress, shader, nir_opt_remove_phis);
128 NIR_PASS(progress, shader, nir_opt_dce);
129 if (nir_opt_trivial_continues(shader)) {
130 progress = true;
131 NIR_PASS(progress, shader, nir_copy_prop);
132 NIR_PASS(progress, shader, nir_opt_remove_phis);
133 NIR_PASS(progress, shader, nir_opt_dce);
134 }
135 NIR_PASS(progress, shader, nir_opt_if);
136 NIR_PASS(progress, shader, nir_opt_dead_cf);
137 NIR_PASS(progress, shader, nir_opt_cse);
138 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
139 NIR_PASS(progress, shader, nir_opt_algebraic);
140 NIR_PASS(progress, shader, nir_opt_constant_folding);
141 NIR_PASS(progress, shader, nir_opt_undef);
142 NIR_PASS(progress, shader, nir_opt_conditional_discard);
143 if (shader->options->max_unroll_iterations) {
144 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
145 }
146 } while (progress);
147 }
148
149 nir_shader *
150 radv_shader_compile_to_nir(struct radv_device *device,
151 struct radv_shader_module *module,
152 const char *entrypoint_name,
153 gl_shader_stage stage,
154 const VkSpecializationInfo *spec_info)
155 {
156 if (strcmp(entrypoint_name, "main") != 0) {
157 radv_finishme("Multiple shaders per module not really supported");
158 }
159
160 nir_shader *nir;
161 nir_function *entry_point;
162 if (module->nir) {
163 /* Some things such as our meta clear/blit code will give us a NIR
164 * shader directly. In that case, we just ignore the SPIR-V entirely
165 * and just use the NIR shader */
166 nir = module->nir;
167 nir->options = &nir_options;
168 nir_validate_shader(nir);
169
170 assert(exec_list_length(&nir->functions) == 1);
171 struct exec_node *node = exec_list_get_head(&nir->functions);
172 entry_point = exec_node_data(nir_function, node, node);
173 } else {
174 uint32_t *spirv = (uint32_t *) module->data;
175 assert(module->size % 4 == 0);
176
177 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
178 radv_print_spirv(spirv, module->size, stderr);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 if (spec_info->dataSize == 8)
192 spec_entries[i].data64 = *(const uint64_t *)data;
193 else
194 spec_entries[i].data32 = *(const uint32_t *)data;
195 }
196 }
197 const struct nir_spirv_supported_extensions supported_ext = {
198 .draw_parameters = true,
199 .float64 = true,
200 .image_read_without_format = true,
201 .image_write_without_format = true,
202 .tessellation = true,
203 .int64 = true,
204 .multiview = true,
205 .variable_pointers = true,
206 };
207 entry_point = spirv_to_nir(spirv, module->size / 4,
208 spec_entries, num_spec_entries,
209 stage, entrypoint_name, &supported_ext, &nir_options);
210 nir = entry_point->shader;
211 assert(nir->info.stage == stage);
212 nir_validate_shader(nir);
213
214 free(spec_entries);
215
216 /* We have to lower away local constant initializers right before we
217 * inline functions. That way they get properly initialized at the top
218 * of the function and not at the top of its caller.
219 */
220 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
221 NIR_PASS_V(nir, nir_lower_returns);
222 NIR_PASS_V(nir, nir_inline_functions);
223
224 /* Pick off the single entrypoint that we want */
225 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
226 if (func != entry_point)
227 exec_node_remove(&func->node);
228 }
229 assert(exec_list_length(&nir->functions) == 1);
230 entry_point->name = ralloc_strdup(entry_point, "main");
231
232 NIR_PASS_V(nir, nir_remove_dead_variables,
233 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
234
235 /* Now that we've deleted all but the main function, we can go ahead and
236 * lower the rest of the constant initializers.
237 */
238 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
239 NIR_PASS_V(nir, nir_lower_system_values);
240 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
241 }
242
243 /* Vulkan uses the separate-shader linking model */
244 nir->info.separate_shader = true;
245
246 nir_shader_gather_info(nir, entry_point->impl);
247
248 /* While it would be nice not to have this flag, we are constrained
249 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
250 * on GFX9.
251 */
252 bool llvm_has_working_vgpr_indexing =
253 device->physical_device->rad_info.chip_class <= VI;
254
255 /* TODO: Indirect indexing of GS inputs is unimplemented.
256 *
257 * TCS and TES load inputs directly from LDS or offchip memory, so
258 * indirect indexing is trivial.
259 */
260 nir_variable_mode indirect_mask = 0;
261 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
262 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
263 nir->info.stage != MESA_SHADER_TESS_EVAL &&
264 !llvm_has_working_vgpr_indexing)) {
265 indirect_mask |= nir_var_shader_in;
266 }
267 if (!llvm_has_working_vgpr_indexing &&
268 nir->info.stage != MESA_SHADER_TESS_CTRL)
269 indirect_mask |= nir_var_shader_out;
270
271 /* TODO: We shouldn't need to do this, however LLVM isn't currently
272 * smart enough to handle indirects without causing excess spilling
273 * causing the gpu to hang.
274 *
275 * See the following thread for more details of the problem:
276 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
277 */
278 indirect_mask |= nir_var_local;
279
280 nir_lower_indirect_derefs(nir, indirect_mask);
281
282 static const nir_lower_tex_options tex_options = {
283 .lower_txp = ~0,
284 };
285
286 nir_lower_tex(nir, &tex_options);
287
288 nir_lower_vars_to_ssa(nir);
289 nir_lower_var_copies(nir);
290 nir_lower_global_vars_to_local(nir);
291 nir_remove_dead_variables(nir, nir_var_local);
292 radv_optimize_nir(nir);
293
294 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
295 nir_print_shader(nir, stderr);
296
297 return nir;
298 }
299
300 void *
301 radv_alloc_shader_memory(struct radv_device *device,
302 struct radv_shader_variant *shader)
303 {
304 mtx_lock(&device->shader_slab_mutex);
305 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
306 uint64_t offset = 0;
307 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
308 if (s->bo_offset - offset >= shader->code_size) {
309 shader->bo = slab->bo;
310 shader->bo_offset = offset;
311 list_addtail(&shader->slab_list, &s->slab_list);
312 mtx_unlock(&device->shader_slab_mutex);
313 return slab->ptr + offset;
314 }
315 offset = align_u64(s->bo_offset + s->code_size, 256);
316 }
317 if (slab->size - offset >= shader->code_size) {
318 shader->bo = slab->bo;
319 shader->bo_offset = offset;
320 list_addtail(&shader->slab_list, &slab->shaders);
321 mtx_unlock(&device->shader_slab_mutex);
322 return slab->ptr + offset;
323 }
324 }
325
326 mtx_unlock(&device->shader_slab_mutex);
327 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
328
329 slab->size = 256 * 1024;
330 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
331 RADEON_DOMAIN_VRAM, 0);
332 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
333 list_inithead(&slab->shaders);
334
335 mtx_lock(&device->shader_slab_mutex);
336 list_add(&slab->slabs, &device->shader_slabs);
337
338 shader->bo = slab->bo;
339 shader->bo_offset = 0;
340 list_add(&shader->slab_list, &slab->shaders);
341 mtx_unlock(&device->shader_slab_mutex);
342 return slab->ptr;
343 }
344
345 void
346 radv_destroy_shader_slabs(struct radv_device *device)
347 {
348 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
349 device->ws->buffer_destroy(slab->bo);
350 free(slab);
351 }
352 mtx_destroy(&device->shader_slab_mutex);
353 }
354
355 static void
356 radv_fill_shader_variant(struct radv_device *device,
357 struct radv_shader_variant *variant,
358 struct ac_shader_binary *binary,
359 gl_shader_stage stage)
360 {
361 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
362 unsigned vgpr_comp_cnt = 0;
363
364 if (scratch_enabled && !device->llvm_supports_spill)
365 radv_finishme("shader scratch support only available with LLVM 4.0");
366
367 variant->code_size = binary->code_size;
368 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
369 S_00B12C_SCRATCH_EN(scratch_enabled);
370
371 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
372 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
373 S_00B848_DX10_CLAMP(1) |
374 S_00B848_FLOAT_MODE(variant->config.float_mode);
375
376 switch (stage) {
377 case MESA_SHADER_TESS_EVAL:
378 vgpr_comp_cnt = 3;
379 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
380 break;
381 case MESA_SHADER_TESS_CTRL:
382 if (device->physical_device->rad_info.chip_class >= GFX9)
383 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
384 else
385 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
386 break;
387 case MESA_SHADER_VERTEX:
388 case MESA_SHADER_GEOMETRY:
389 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
390 break;
391 case MESA_SHADER_FRAGMENT:
392 break;
393 case MESA_SHADER_COMPUTE:
394 variant->rsrc2 |=
395 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
396 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
397 S_00B84C_TG_SIZE_EN(1) |
398 S_00B84C_LDS_SIZE(variant->config.lds_size);
399 break;
400 default:
401 unreachable("unsupported shader type");
402 break;
403 }
404
405 if (device->physical_device->rad_info.chip_class >= GFX9 &&
406 stage == MESA_SHADER_GEOMETRY) {
407 /* TODO: Figure out how many we actually need. */
408 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(3);
409 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
410 S_00B22C_OC_LDS_EN(1);
411 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
412 stage == MESA_SHADER_TESS_CTRL)
413 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
414 else
415 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
416
417 void *ptr = radv_alloc_shader_memory(device, variant);
418 memcpy(ptr, binary->code, binary->code_size);
419 }
420
421 static struct radv_shader_variant *
422 shader_variant_create(struct radv_device *device,
423 struct radv_shader_module *module,
424 struct nir_shader * const *shaders,
425 int shader_count,
426 gl_shader_stage stage,
427 struct ac_nir_compiler_options *options,
428 bool gs_copy_shader,
429 void **code_out,
430 unsigned *code_size_out)
431 {
432 enum radeon_family chip_family = device->physical_device->rad_info.family;
433 bool dump_shaders = device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS;
434 enum ac_target_machine_options tm_options = 0;
435 struct radv_shader_variant *variant;
436 struct ac_shader_binary binary;
437 LLVMTargetMachineRef tm;
438
439 variant = calloc(1, sizeof(struct radv_shader_variant));
440 if (!variant)
441 return NULL;
442
443 options->family = chip_family;
444 options->chip_class = device->physical_device->rad_info.chip_class;
445
446 if (options->supports_spill)
447 tm_options |= AC_TM_SUPPORTS_SPILL;
448 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
449 tm_options |= AC_TM_SISCHED;
450 tm = ac_create_target_machine(chip_family, tm_options);
451
452 if (gs_copy_shader) {
453 assert(shader_count == 1);
454 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
455 &variant->info, options, dump_shaders);
456 } else {
457 ac_compile_nir_shader(tm, &binary, &variant->config,
458 &variant->info, shaders, shader_count, options,
459 dump_shaders);
460 }
461
462 LLVMDisposeTargetMachine(tm);
463
464 radv_fill_shader_variant(device, variant, &binary, stage);
465
466 if (code_out) {
467 *code_out = binary.code;
468 *code_size_out = binary.code_size;
469 } else
470 free(binary.code);
471 free(binary.config);
472 free(binary.rodata);
473 free(binary.global_symbol_offsets);
474 free(binary.relocs);
475 variant->ref_count = 1;
476
477 if (device->trace_bo) {
478 variant->disasm_string = binary.disasm_string;
479 if (!gs_copy_shader && !module->nir) {
480 variant->nir = *shaders;
481 variant->spirv = (uint32_t *)module->data;
482 variant->spirv_size = module->size;
483 }
484 } else {
485 free(binary.disasm_string);
486 }
487
488 return variant;
489 }
490
491 struct radv_shader_variant *
492 radv_shader_variant_create(struct radv_device *device,
493 struct radv_shader_module *module,
494 struct nir_shader *const *shaders,
495 int shader_count,
496 struct radv_pipeline_layout *layout,
497 const struct ac_shader_variant_key *key,
498 void **code_out,
499 unsigned *code_size_out)
500 {
501 struct ac_nir_compiler_options options = {0};
502
503 options.layout = layout;
504 if (key)
505 options.key = *key;
506
507 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
508 options.supports_spill = device->llvm_supports_spill;
509
510 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
511 &options, false, code_out, code_size_out);
512 }
513
514 struct radv_shader_variant *
515 radv_create_gs_copy_shader(struct radv_device *device,
516 struct nir_shader *shader,
517 void **code_out,
518 unsigned *code_size_out,
519 bool multiview)
520 {
521 struct ac_nir_compiler_options options = {0};
522
523 options.key.has_multiview_view_index = multiview;
524
525 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
526 &options, true, code_out, code_size_out);
527 }
528
529 void
530 radv_shader_variant_destroy(struct radv_device *device,
531 struct radv_shader_variant *variant)
532 {
533 if (!p_atomic_dec_zero(&variant->ref_count))
534 return;
535
536 mtx_lock(&device->shader_slab_mutex);
537 list_del(&variant->slab_list);
538 mtx_unlock(&device->shader_slab_mutex);
539
540 ralloc_free(variant->nir);
541 free(variant->disasm_string);
542 free(variant);
543 }
544
545 uint32_t
546 radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class,
547 bool has_gs, bool has_tess)
548 {
549 switch (stage) {
550 case MESA_SHADER_FRAGMENT:
551 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
552 case MESA_SHADER_VERTEX:
553 if (chip_class >= GFX9) {
554 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
555 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
556 R_00B130_SPI_SHADER_USER_DATA_VS_0;
557 }
558 if (has_tess)
559 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
560 else
561 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
562 case MESA_SHADER_GEOMETRY:
563 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
564 R_00B230_SPI_SHADER_USER_DATA_GS_0;
565 case MESA_SHADER_COMPUTE:
566 return R_00B900_COMPUTE_USER_DATA_0;
567 case MESA_SHADER_TESS_CTRL:
568 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
569 R_00B430_SPI_SHADER_USER_DATA_HS_0;
570 case MESA_SHADER_TESS_EVAL:
571 if (chip_class >= GFX9) {
572 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
573 R_00B130_SPI_SHADER_USER_DATA_VS_0;
574 }
575 if (has_gs)
576 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
577 else
578 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
579 default:
580 unreachable("unknown shader");
581 }
582 }
583
584 const char *
585 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
586 {
587 switch (stage) {
588 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
589 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
590 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
591 case MESA_SHADER_COMPUTE: return "Compute Shader";
592 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
593 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
594 default:
595 return "Unknown shader";
596 };
597 }
598
599 void
600 radv_shader_dump_stats(struct radv_device *device,
601 struct radv_shader_variant *variant,
602 gl_shader_stage stage,
603 FILE *file)
604 {
605 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
606 struct ac_shader_config *conf;
607 unsigned max_simd_waves;
608 unsigned lds_per_wave = 0;
609
610 switch (device->physical_device->rad_info.family) {
611 /* These always have 8 waves: */
612 case CHIP_POLARIS10:
613 case CHIP_POLARIS11:
614 case CHIP_POLARIS12:
615 max_simd_waves = 8;
616 break;
617 default:
618 max_simd_waves = 10;
619 }
620
621 conf = &variant->config;
622
623 if (stage == MESA_SHADER_FRAGMENT) {
624 lds_per_wave = conf->lds_size * lds_increment +
625 align(variant->info.fs.num_interp * 48,
626 lds_increment);
627 }
628
629 if (conf->num_sgprs) {
630 if (device->physical_device->rad_info.chip_class >= VI)
631 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
632 else
633 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
634 }
635
636 if (conf->num_vgprs)
637 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
638
639 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
640 * that PS can use.
641 */
642 if (lds_per_wave)
643 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
644
645 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
646
647 if (stage == MESA_SHADER_FRAGMENT) {
648 fprintf(file, "*** SHADER CONFIG ***\n"
649 "SPI_PS_INPUT_ADDR = 0x%04x\n"
650 "SPI_PS_INPUT_ENA = 0x%04x\n",
651 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
652 }
653
654 fprintf(file, "*** SHADER STATS ***\n"
655 "SGPRS: %d\n"
656 "VGPRS: %d\n"
657 "Spilled SGPRs: %d\n"
658 "Spilled VGPRs: %d\n"
659 "Code Size: %d bytes\n"
660 "LDS: %d blocks\n"
661 "Scratch: %d bytes per wave\n"
662 "Max Waves: %d\n"
663 "********************\n\n\n",
664 conf->num_sgprs, conf->num_vgprs,
665 conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
666 conf->lds_size, conf->scratch_bytes_per_wave,
667 max_simd_waves);
668 }