2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39 #include <llvm-c/Support.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
50 #include "util/string_buffer.h"
52 static const struct nir_shader_compiler_options nir_options
= {
53 .vertex_id_zero_based
= true,
57 .lower_device_index_to_zero
= true,
61 .lower_pack_snorm_2x16
= true,
62 .lower_pack_snorm_4x8
= true,
63 .lower_pack_unorm_2x16
= true,
64 .lower_pack_unorm_4x8
= true,
65 .lower_unpack_snorm_2x16
= true,
66 .lower_unpack_snorm_4x8
= true,
67 .lower_unpack_unorm_2x16
= true,
68 .lower_unpack_unorm_4x8
= true,
69 .lower_extract_byte
= true,
70 .lower_extract_word
= true,
73 .vs_inputs_dual_locations
= true,
74 .max_unroll_iterations
= 32
77 VkResult
radv_CreateShaderModule(
79 const VkShaderModuleCreateInfo
* pCreateInfo
,
80 const VkAllocationCallbacks
* pAllocator
,
81 VkShaderModule
* pShaderModule
)
83 RADV_FROM_HANDLE(radv_device
, device
, _device
);
84 struct radv_shader_module
*module
;
86 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
87 assert(pCreateInfo
->flags
== 0);
89 module
= vk_alloc2(&device
->alloc
, pAllocator
,
90 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
91 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
93 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
96 module
->size
= pCreateInfo
->codeSize
;
97 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
99 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
101 *pShaderModule
= radv_shader_module_to_handle(module
);
106 void radv_DestroyShaderModule(
108 VkShaderModule _module
,
109 const VkAllocationCallbacks
* pAllocator
)
111 RADV_FROM_HANDLE(radv_device
, device
, _device
);
112 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
117 vk_free2(&device
->alloc
, pAllocator
, module
);
121 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
)
128 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
129 NIR_PASS_V(shader
, nir_lower_pack
);
130 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
131 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
133 NIR_PASS(progress
, shader
, nir_copy_prop
);
134 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
135 NIR_PASS(progress
, shader
, nir_opt_dce
);
136 if (nir_opt_trivial_continues(shader
)) {
138 NIR_PASS(progress
, shader
, nir_copy_prop
);
139 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
140 NIR_PASS(progress
, shader
, nir_opt_dce
);
142 NIR_PASS(progress
, shader
, nir_opt_if
);
143 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
144 NIR_PASS(progress
, shader
, nir_opt_cse
);
145 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
146 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
147 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
148 NIR_PASS(progress
, shader
, nir_opt_undef
);
149 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
150 if (shader
->options
->max_unroll_iterations
) {
151 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
153 } while (progress
&& !optimize_conservatively
);
155 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
156 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
160 radv_shader_compile_to_nir(struct radv_device
*device
,
161 struct radv_shader_module
*module
,
162 const char *entrypoint_name
,
163 gl_shader_stage stage
,
164 const VkSpecializationInfo
*spec_info
,
165 const VkPipelineCreateFlags flags
)
168 nir_function
*entry_point
;
170 /* Some things such as our meta clear/blit code will give us a NIR
171 * shader directly. In that case, we just ignore the SPIR-V entirely
172 * and just use the NIR shader */
174 nir
->options
= &nir_options
;
175 nir_validate_shader(nir
);
177 assert(exec_list_length(&nir
->functions
) == 1);
178 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
179 entry_point
= exec_node_data(nir_function
, node
, node
);
181 uint32_t *spirv
= (uint32_t *) module
->data
;
182 assert(module
->size
% 4 == 0);
184 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
185 radv_print_spirv(spirv
, module
->size
, stderr
);
187 uint32_t num_spec_entries
= 0;
188 struct nir_spirv_specialization
*spec_entries
= NULL
;
189 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
190 num_spec_entries
= spec_info
->mapEntryCount
;
191 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
192 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
193 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
194 const void *data
= spec_info
->pData
+ entry
.offset
;
195 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
197 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
198 if (spec_info
->dataSize
== 8)
199 spec_entries
[i
].data64
= *(const uint64_t *)data
;
201 spec_entries
[i
].data32
= *(const uint32_t *)data
;
204 const struct spirv_to_nir_options spirv_options
= {
206 .device_group
= true,
207 .draw_parameters
= true,
209 .image_read_without_format
= true,
210 .image_write_without_format
= true,
211 .tessellation
= true,
214 .subgroup_ballot
= true,
215 .subgroup_basic
= true,
216 .subgroup_quad
= true,
217 .subgroup_shuffle
= true,
218 .subgroup_vote
= true,
219 .variable_pointers
= true,
221 .trinary_minmax
= true,
222 .shader_viewport_index_layer
= true,
223 .descriptor_array_dynamic_indexing
= true,
224 .runtime_descriptor_array
= true,
225 .stencil_export
= true,
228 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
229 spec_entries
, num_spec_entries
,
230 stage
, entrypoint_name
,
231 &spirv_options
, &nir_options
);
232 nir
= entry_point
->shader
;
233 assert(nir
->info
.stage
== stage
);
234 nir_validate_shader(nir
);
238 /* We have to lower away local constant initializers right before we
239 * inline functions. That way they get properly initialized at the top
240 * of the function and not at the top of its caller.
242 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
243 NIR_PASS_V(nir
, nir_lower_returns
);
244 NIR_PASS_V(nir
, nir_inline_functions
);
245 NIR_PASS_V(nir
, nir_copy_prop
);
247 /* Pick off the single entrypoint that we want */
248 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
249 if (func
!= entry_point
)
250 exec_node_remove(&func
->node
);
252 assert(exec_list_length(&nir
->functions
) == 1);
253 entry_point
->name
= ralloc_strdup(entry_point
, "main");
255 /* Make sure we lower constant initializers on output variables so that
256 * nir_remove_dead_variables below sees the corresponding stores
258 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
260 NIR_PASS_V(nir
, nir_remove_dead_variables
,
261 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers.
266 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
268 /* Split member structs. We do this before lower_io_to_temporaries so that
269 * it doesn't lower system values to temporaries by accident.
271 NIR_PASS_V(nir
, nir_split_var_copies
);
272 NIR_PASS_V(nir
, nir_split_per_member_structs
);
274 NIR_PASS_V(nir
, nir_lower_system_values
);
275 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
278 /* Vulkan uses the separate-shader linking model */
279 nir
->info
.separate_shader
= true;
281 nir_shader_gather_info(nir
, entry_point
->impl
);
283 static const nir_lower_tex_options tex_options
= {
287 nir_lower_tex(nir
, &tex_options
);
289 nir_lower_vars_to_ssa(nir
);
291 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
292 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
293 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
294 nir_shader_get_entrypoint(nir
), true, true);
295 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
296 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
297 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
298 nir_shader_get_entrypoint(nir
), true, false);
301 nir_split_var_copies(nir
);
302 nir_lower_var_copies(nir
);
304 nir_lower_global_vars_to_local(nir
);
305 nir_remove_dead_variables(nir
, nir_var_local
);
306 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
308 .ballot_bit_size
= 64,
309 .lower_to_scalar
= 1,
310 .lower_subgroup_masks
= 1,
312 .lower_shuffle_to_32bit
= 1,
313 .lower_vote_eq_to_ballot
= 1,
316 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
317 radv_optimize_nir(nir
, false);
319 /* Indirect lowering must be called after the radv_optimize_nir() loop
320 * has been called at least once. Otherwise indirect lowering can
321 * bloat the instruction count of the loop and cause it to be
322 * considered too large for unrolling.
324 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
325 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
);
331 radv_alloc_shader_memory(struct radv_device
*device
,
332 struct radv_shader_variant
*shader
)
334 mtx_lock(&device
->shader_slab_mutex
);
335 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
337 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
338 if (s
->bo_offset
- offset
>= shader
->code_size
) {
339 shader
->bo
= slab
->bo
;
340 shader
->bo_offset
= offset
;
341 list_addtail(&shader
->slab_list
, &s
->slab_list
);
342 mtx_unlock(&device
->shader_slab_mutex
);
343 return slab
->ptr
+ offset
;
345 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
347 if (slab
->size
- offset
>= shader
->code_size
) {
348 shader
->bo
= slab
->bo
;
349 shader
->bo_offset
= offset
;
350 list_addtail(&shader
->slab_list
, &slab
->shaders
);
351 mtx_unlock(&device
->shader_slab_mutex
);
352 return slab
->ptr
+ offset
;
356 mtx_unlock(&device
->shader_slab_mutex
);
357 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
359 slab
->size
= 256 * 1024;
360 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
362 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
363 device
->physical_device
->cpdma_prefetch_writes_memory
?
364 0 : RADEON_FLAG_READ_ONLY
);
365 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
366 list_inithead(&slab
->shaders
);
368 mtx_lock(&device
->shader_slab_mutex
);
369 list_add(&slab
->slabs
, &device
->shader_slabs
);
371 shader
->bo
= slab
->bo
;
372 shader
->bo_offset
= 0;
373 list_add(&shader
->slab_list
, &slab
->shaders
);
374 mtx_unlock(&device
->shader_slab_mutex
);
379 radv_destroy_shader_slabs(struct radv_device
*device
)
381 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
382 device
->ws
->buffer_destroy(slab
->bo
);
385 mtx_destroy(&device
->shader_slab_mutex
);
388 /* For the UMR disassembler. */
389 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
390 #define DEBUGGER_NUM_MARKERS 5
393 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
395 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
399 radv_fill_shader_variant(struct radv_device
*device
,
400 struct radv_shader_variant
*variant
,
401 struct ac_shader_binary
*binary
,
402 gl_shader_stage stage
)
404 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
405 struct radv_shader_info
*info
= &variant
->info
.info
;
406 unsigned vgpr_comp_cnt
= 0;
408 variant
->code_size
= radv_get_shader_binary_size(binary
);
409 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
410 S_00B12C_SCRATCH_EN(scratch_enabled
);
412 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
413 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
414 S_00B848_DX10_CLAMP(1) |
415 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
418 case MESA_SHADER_TESS_EVAL
:
420 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
422 case MESA_SHADER_TESS_CTRL
:
423 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
424 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
426 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
429 case MESA_SHADER_VERTEX
:
430 case MESA_SHADER_GEOMETRY
:
431 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
433 case MESA_SHADER_FRAGMENT
:
435 case MESA_SHADER_COMPUTE
:
437 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
438 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
439 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
440 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
441 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
442 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
443 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
446 unreachable("unsupported shader type");
450 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
451 stage
== MESA_SHADER_GEOMETRY
) {
452 unsigned es_type
= variant
->info
.gs
.es_type
;
453 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
455 if (es_type
== MESA_SHADER_VERTEX
) {
456 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
457 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
458 es_vgpr_comp_cnt
= 3;
460 unreachable("invalid shader ES type");
463 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
464 * VGPR[0:4] are always loaded.
466 if (info
->uses_invocation_id
) {
467 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
468 } else if (info
->uses_prim_id
) {
469 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
470 } else if (variant
->info
.gs
.vertices_in
>= 3) {
471 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
473 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
476 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
477 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
478 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
479 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
480 stage
== MESA_SHADER_TESS_CTRL
) {
481 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
483 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
486 void *ptr
= radv_alloc_shader_memory(device
, variant
);
487 memcpy(ptr
, binary
->code
, binary
->code_size
);
489 /* Add end-of-code markers for the UMR disassembler. */
490 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
491 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
492 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
496 static void radv_init_llvm_target()
498 LLVMInitializeAMDGPUTargetInfo();
499 LLVMInitializeAMDGPUTarget();
500 LLVMInitializeAMDGPUTargetMC();
501 LLVMInitializeAMDGPUAsmPrinter();
503 /* For inline assembly. */
504 LLVMInitializeAMDGPUAsmParser();
506 /* Workaround for bug in llvm 4.0 that causes image intrinsics
508 * https://reviews.llvm.org/D26348
510 * Workaround for bug in llvm that causes the GPU to hang in presence
511 * of nested loops because there is an exec mask issue. The proper
512 * solution is to fix LLVM but this might require a bunch of work.
513 * https://bugs.llvm.org/show_bug.cgi?id=37744
515 * "mesa" is the prefix for error messages.
517 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
518 "-amdgpu-skip-threshold=1" };
519 LLVMParseCommandLineOptions(3, argv
, NULL
);
522 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
524 static void radv_init_llvm_once(void)
526 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
529 static struct radv_shader_variant
*
530 shader_variant_create(struct radv_device
*device
,
531 struct radv_shader_module
*module
,
532 struct nir_shader
* const *shaders
,
534 gl_shader_stage stage
,
535 struct radv_nir_compiler_options
*options
,
538 unsigned *code_size_out
)
540 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
541 enum ac_target_machine_options tm_options
= 0;
542 struct radv_shader_variant
*variant
;
543 struct ac_shader_binary binary
;
544 LLVMTargetMachineRef tm
;
545 LLVMPassManagerRef passmgr
;
547 variant
= calloc(1, sizeof(struct radv_shader_variant
));
551 options
->family
= chip_family
;
552 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
553 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
554 options
->dump_preoptir
= options
->dump_shader
&&
555 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
556 options
->record_llvm_ir
= device
->keep_shader_info
;
557 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
558 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
559 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
561 if (options
->supports_spill
)
562 tm_options
|= AC_TM_SUPPORTS_SPILL
;
563 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
564 tm_options
|= AC_TM_SISCHED
;
566 radv_init_llvm_once();
567 tm
= ac_create_target_machine(chip_family
, tm_options
, NULL
);
568 passmgr
= ac_create_passmgr(NULL
, options
->check_ir
);
569 if (gs_copy_shader
) {
570 assert(shader_count
== 1);
571 radv_compile_gs_copy_shader(tm
, passmgr
, *shaders
, &binary
,
572 &variant
->config
, &variant
->info
,
575 radv_compile_nir_shader(tm
, passmgr
, &binary
, &variant
->config
,
576 &variant
->info
, shaders
, shader_count
,
580 LLVMDisposePassManager(passmgr
);
581 LLVMDisposeTargetMachine(tm
);
583 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
586 *code_out
= binary
.code
;
587 *code_size_out
= variant
->code_size
;
592 free(binary
.global_symbol_offsets
);
594 variant
->ref_count
= 1;
596 if (device
->keep_shader_info
) {
597 variant
->disasm_string
= binary
.disasm_string
;
598 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
599 if (!gs_copy_shader
&& !module
->nir
) {
600 variant
->nir
= *shaders
;
601 variant
->spirv
= (uint32_t *)module
->data
;
602 variant
->spirv_size
= module
->size
;
605 free(binary
.disasm_string
);
611 struct radv_shader_variant
*
612 radv_shader_variant_create(struct radv_device
*device
,
613 struct radv_shader_module
*module
,
614 struct nir_shader
*const *shaders
,
616 struct radv_pipeline_layout
*layout
,
617 const struct radv_shader_variant_key
*key
,
619 unsigned *code_size_out
)
621 struct radv_nir_compiler_options options
= {0};
623 options
.layout
= layout
;
627 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
628 options
.supports_spill
= true;
630 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
631 &options
, false, code_out
, code_size_out
);
634 struct radv_shader_variant
*
635 radv_create_gs_copy_shader(struct radv_device
*device
,
636 struct nir_shader
*shader
,
638 unsigned *code_size_out
,
641 struct radv_nir_compiler_options options
= {0};
643 options
.key
.has_multiview_view_index
= multiview
;
645 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
646 &options
, true, code_out
, code_size_out
);
650 radv_shader_variant_destroy(struct radv_device
*device
,
651 struct radv_shader_variant
*variant
)
653 if (!p_atomic_dec_zero(&variant
->ref_count
))
656 mtx_lock(&device
->shader_slab_mutex
);
657 list_del(&variant
->slab_list
);
658 mtx_unlock(&device
->shader_slab_mutex
);
660 ralloc_free(variant
->nir
);
661 free(variant
->disasm_string
);
662 free(variant
->llvm_ir_string
);
667 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
670 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
671 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
672 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
673 case MESA_SHADER_COMPUTE
: return "Compute Shader";
674 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
675 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
677 return "Unknown shader";
682 generate_shader_stats(struct radv_device
*device
,
683 struct radv_shader_variant
*variant
,
684 gl_shader_stage stage
,
685 struct _mesa_string_buffer
*buf
)
687 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
688 struct ac_shader_config
*conf
;
689 unsigned max_simd_waves
;
690 unsigned lds_per_wave
= 0;
692 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
694 conf
= &variant
->config
;
696 if (stage
== MESA_SHADER_FRAGMENT
) {
697 lds_per_wave
= conf
->lds_size
* lds_increment
+
698 align(variant
->info
.fs
.num_interp
* 48,
705 radv_get_num_physical_sgprs(device
->physical_device
) / conf
->num_sgprs
);
710 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
712 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
716 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
718 if (stage
== MESA_SHADER_FRAGMENT
) {
719 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
720 "SPI_PS_INPUT_ADDR = 0x%04x\n"
721 "SPI_PS_INPUT_ENA = 0x%04x\n",
722 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
725 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
728 "Spilled SGPRs: %d\n"
729 "Spilled VGPRs: %d\n"
730 "PrivMem VGPRS: %d\n"
731 "Code Size: %d bytes\n"
733 "Scratch: %d bytes per wave\n"
735 "********************\n\n\n",
736 conf
->num_sgprs
, conf
->num_vgprs
,
737 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
738 variant
->info
.private_mem_vgprs
, variant
->code_size
,
739 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
744 radv_shader_dump_stats(struct radv_device
*device
,
745 struct radv_shader_variant
*variant
,
746 gl_shader_stage stage
,
749 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
751 generate_shader_stats(device
, variant
, stage
, buf
);
753 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
754 fprintf(file
, "%s", buf
->buf
);
756 _mesa_string_buffer_destroy(buf
);
760 radv_GetShaderInfoAMD(VkDevice _device
,
761 VkPipeline _pipeline
,
762 VkShaderStageFlagBits shaderStage
,
763 VkShaderInfoTypeAMD infoType
,
767 RADV_FROM_HANDLE(radv_device
, device
, _device
);
768 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
769 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
770 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
771 struct _mesa_string_buffer
*buf
;
772 VkResult result
= VK_SUCCESS
;
774 /* Spec doesn't indicate what to do if the stage is invalid, so just
775 * return no info for this. */
777 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
780 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
782 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
784 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
785 struct ac_shader_config
*conf
= &variant
->config
;
787 VkShaderStatisticsInfoAMD statistics
= {};
788 statistics
.shaderStageMask
= shaderStage
;
789 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
790 statistics
.numPhysicalSgprs
= radv_get_num_physical_sgprs(device
->physical_device
);
791 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
793 if (stage
== MESA_SHADER_COMPUTE
) {
794 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
795 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
797 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
798 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
800 statistics
.computeWorkGroupSize
[0] = local_size
[0];
801 statistics
.computeWorkGroupSize
[1] = local_size
[1];
802 statistics
.computeWorkGroupSize
[2] = local_size
[2];
804 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
807 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
808 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
809 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
810 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
811 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
813 size_t size
= *pInfoSize
;
814 *pInfoSize
= sizeof(statistics
);
816 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
818 if (size
< *pInfoSize
)
819 result
= VK_INCOMPLETE
;
823 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
824 buf
= _mesa_string_buffer_create(NULL
, 1024);
826 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
827 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
828 generate_shader_stats(device
, variant
, stage
, buf
);
830 /* Need to include the null terminator. */
831 size_t length
= buf
->length
+ 1;
836 size_t size
= *pInfoSize
;
839 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
842 result
= VK_INCOMPLETE
;
845 _mesa_string_buffer_destroy(buf
);
848 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
849 result
= VK_ERROR_FEATURE_NOT_PRESENT
;