projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
panfrost: Add routines to calculate stack size/shift
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 unsigned shader_io_get_unique_index(gl_varying_slot slot)
156 {
157 /* handle patch indices separate */
158 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
159 return 0;
160 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
161 return 1;
162 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
163 return 2 + (slot - VARYING_SLOT_PATCH0);
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 if (slot == VARYING_SLOT_CLIP_DIST1)
171 return 3;
172 /* 3 is reserved for clip dist as well */
173 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
174 return 4 + (slot - VARYING_SLOT_VAR0);
175 unreachable("illegal slot in get unique index\n");
176 }
177
178 VkResult radv_CreateShaderModule(
179 VkDevice _device,
180 const VkShaderModuleCreateInfo* pCreateInfo,
181 const VkAllocationCallbacks* pAllocator,
182 VkShaderModule* pShaderModule)
183 {
184 RADV_FROM_HANDLE(radv_device, device, _device);
185 struct radv_shader_module *module;
186
187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
188 assert(pCreateInfo->flags == 0);
189
190 module = vk_alloc2(&device->alloc, pAllocator,
191 sizeof(*module) + pCreateInfo->codeSize, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (module == NULL)
194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 module->nir = NULL;
197 module->size = pCreateInfo->codeSize;
198 memcpy(module->data, pCreateInfo->pCode, module->size);
199
200 _mesa_sha1_compute(module->data, module->size, module->sha1);
201
202 *pShaderModule = radv_shader_module_to_handle(module);
203
204 return VK_SUCCESS;
205 }
206
207 void radv_DestroyShaderModule(
208 VkDevice _device,
209 VkShaderModule _module,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 RADV_FROM_HANDLE(radv_device, device, _device);
213 RADV_FROM_HANDLE(radv_shader_module, module, _module);
214
215 if (!module)
216 return;
217
218 vk_free2(&device->alloc, pAllocator, module);
219 }
220
221 void
222 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
223 bool allow_copies)
224 {
225 bool progress;
226 unsigned lower_flrp =
227 (shader->options->lower_flrp16 ? 16 : 0) |
228 (shader->options->lower_flrp32 ? 32 : 0) |
229 (shader->options->lower_flrp64 ? 64 : 0);
230
231 do {
232 progress = false;
233
234 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
235 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
236
237 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
238 NIR_PASS_V(shader, nir_lower_pack);
239
240 if (allow_copies) {
241 /* Only run this pass in the first call to
242 * radv_optimize_nir. Later calls assume that we've
243 * lowered away any copy_deref instructions and we
244 * don't want to introduce any more.
245 */
246 NIR_PASS(progress, shader, nir_opt_find_array_copies);
247 }
248
249 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
250 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
251 NIR_PASS(progress, shader, nir_remove_dead_variables,
252 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
253
254 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
255 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
256
257 NIR_PASS(progress, shader, nir_copy_prop);
258 NIR_PASS(progress, shader, nir_opt_remove_phis);
259 NIR_PASS(progress, shader, nir_opt_dce);
260 if (nir_opt_trivial_continues(shader)) {
261 progress = true;
262 NIR_PASS(progress, shader, nir_copy_prop);
263 NIR_PASS(progress, shader, nir_opt_remove_phis);
264 NIR_PASS(progress, shader, nir_opt_dce);
265 }
266 NIR_PASS(progress, shader, nir_opt_if, true);
267 NIR_PASS(progress, shader, nir_opt_dead_cf);
268 NIR_PASS(progress, shader, nir_opt_cse);
269 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
270 NIR_PASS(progress, shader, nir_opt_constant_folding);
271 NIR_PASS(progress, shader, nir_opt_algebraic);
272
273 if (lower_flrp != 0) {
274 bool lower_flrp_progress = false;
275 NIR_PASS(lower_flrp_progress,
276 shader,
277 nir_lower_flrp,
278 lower_flrp,
279 false /* always_precise */,
280 shader->options->lower_ffma);
281 if (lower_flrp_progress) {
282 NIR_PASS(progress, shader,
283 nir_opt_constant_folding);
284 progress = true;
285 }
286
287 /* Nothing should rematerialize any flrps, so we only
288 * need to do this lowering once.
289 */
290 lower_flrp = 0;
291 }
292
293 NIR_PASS(progress, shader, nir_opt_undef);
294 if (shader->options->max_unroll_iterations) {
295 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
296 }
297 } while (progress && !optimize_conservatively);
298
299 NIR_PASS(progress, shader, nir_opt_conditional_discard);
300 NIR_PASS(progress, shader, nir_opt_shrink_load);
301 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
302 }
303
304 static void
305 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
306 {
307 assert(glsl_type_is_vector_or_scalar(type));
308
309 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
310 unsigned length = glsl_get_vector_elements(type);
311 *size = comp_size * length,
312 *align = comp_size;
313 }
314
315 nir_shader *
316 radv_shader_compile_to_nir(struct radv_device *device,
317 struct radv_shader_module *module,
318 const char *entrypoint_name,
319 gl_shader_stage stage,
320 const VkSpecializationInfo *spec_info,
321 const VkPipelineCreateFlags flags,
322 const struct radv_pipeline_layout *layout,
323 bool use_aco)
324 {
325 nir_shader *nir;
326 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
327 &nir_options_llvm;
328 if (module->nir) {
329 /* Some things such as our meta clear/blit code will give us a NIR
330 * shader directly. In that case, we just ignore the SPIR-V entirely
331 * and just use the NIR shader */
332 nir = module->nir;
333 nir->options = nir_options;
334 nir_validate_shader(nir, "in internal shader");
335
336 assert(exec_list_length(&nir->functions) == 1);
337 } else {
338 uint32_t *spirv = (uint32_t *) module->data;
339 assert(module->size % 4 == 0);
340
341 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
342 radv_print_spirv(module->data, module->size, stderr);
343
344 uint32_t num_spec_entries = 0;
345 struct nir_spirv_specialization *spec_entries = NULL;
346 if (spec_info && spec_info->mapEntryCount > 0) {
347 num_spec_entries = spec_info->mapEntryCount;
348 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
349 for (uint32_t i = 0; i < num_spec_entries; i++) {
350 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
351 const void *data = spec_info->pData + entry.offset;
352 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
353
354 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
355 if (spec_info->dataSize == 8)
356 spec_entries[i].data64 = *(const uint64_t *)data;
357 else
358 spec_entries[i].data32 = *(const uint32_t *)data;
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_gcn_shader = true,
365 .amd_shader_ballot = device->physical_device->use_shader_ballot,
366 .amd_trinary_minmax = true,
367 .demote_to_helper_invocation = device->physical_device->use_aco,
368 .derivative_group = true,
369 .descriptor_array_dynamic_indexing = true,
370 .descriptor_array_non_uniform_indexing = true,
371 .descriptor_indexing = true,
372 .device_group = true,
373 .draw_parameters = true,
374 .float_controls = true,
375 .float16 = !device->physical_device->use_aco,
376 .float64 = true,
377 .geometry_streams = true,
378 .image_read_without_format = true,
379 .image_write_without_format = true,
380 .int8 = !device->physical_device->use_aco,
381 .int16 = !device->physical_device->use_aco,
382 .int64 = true,
383 .int64_atomics = true,
384 .multiview = true,
385 .physical_storage_buffer_address = true,
386 .post_depth_coverage = true,
387 .runtime_descriptor_array = true,
388 .shader_clock = true,
389 .shader_viewport_index_layer = true,
390 .stencil_export = true,
391 .storage_8bit = !device->physical_device->use_aco,
392 .storage_16bit = !device->physical_device->use_aco,
393 .storage_image_ms = true,
394 .subgroup_arithmetic = true,
395 .subgroup_ballot = true,
396 .subgroup_basic = true,
397 .subgroup_quad = true,
398 .subgroup_shuffle = true,
399 .subgroup_vote = true,
400 .tessellation = true,
401 .transform_feedback = true,
402 .variable_pointers = true,
403 },
404 .ubo_addr_format = nir_address_format_32bit_index_offset,
405 .ssbo_addr_format = nir_address_format_32bit_index_offset,
406 .phys_ssbo_addr_format = nir_address_format_64bit_global,
407 .push_const_addr_format = nir_address_format_logical,
408 .shared_addr_format = nir_address_format_32bit_offset,
409 .frag_coord_is_sysval = true,
410 };
411 nir = spirv_to_nir(spirv, module->size / 4,
412 spec_entries, num_spec_entries,
413 stage, entrypoint_name,
414 &spirv_options, nir_options);
415 assert(nir->info.stage == stage);
416 nir_validate_shader(nir, "after spirv_to_nir");
417
418 free(spec_entries);
419
420 /* We have to lower away local constant initializers right before we
421 * inline functions. That way they get properly initialized at the top
422 * of the function and not at the top of its caller.
423 */
424 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
425 NIR_PASS_V(nir, nir_lower_returns);
426 NIR_PASS_V(nir, nir_inline_functions);
427 NIR_PASS_V(nir, nir_opt_deref);
428
429 /* Pick off the single entrypoint that we want */
430 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
431 if (func->is_entrypoint)
432 func->name = ralloc_strdup(func, "main");
433 else
434 exec_node_remove(&func->node);
435 }
436 assert(exec_list_length(&nir->functions) == 1);
437
438 /* Make sure we lower constant initializers on output variables so that
439 * nir_remove_dead_variables below sees the corresponding stores
440 */
441 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
442
443 /* Now that we've deleted all but the main function, we can go ahead and
444 * lower the rest of the constant initializers.
445 */
446 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
447
448 /* Split member structs. We do this before lower_io_to_temporaries so that
449 * it doesn't lower system values to temporaries by accident.
450 */
451 NIR_PASS_V(nir, nir_split_var_copies);
452 NIR_PASS_V(nir, nir_split_per_member_structs);
453
454 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
455 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
456 if (nir->info.stage == MESA_SHADER_FRAGMENT)
457 NIR_PASS_V(nir, nir_lower_input_attachments, true);
458
459 NIR_PASS_V(nir, nir_remove_dead_variables,
460 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
461
462 NIR_PASS_V(nir, nir_propagate_invariant);
463
464 NIR_PASS_V(nir, nir_lower_system_values);
465 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
466 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
467 }
468
469 /* Vulkan uses the separate-shader linking model */
470 nir->info.separate_shader = true;
471
472 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
473
474 static const nir_lower_tex_options tex_options = {
475 .lower_txp = ~0,
476 .lower_tg4_offsets = true,
477 };
478
479 nir_lower_tex(nir, &tex_options);
480
481 nir_lower_vars_to_ssa(nir);
482
483 if (nir->info.stage == MESA_SHADER_VERTEX ||
484 nir->info.stage == MESA_SHADER_GEOMETRY ||
485 nir->info.stage == MESA_SHADER_FRAGMENT) {
486 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
487 nir_shader_get_entrypoint(nir), true, true);
488 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
489 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
490 nir_shader_get_entrypoint(nir), true, false);
491 }
492
493 nir_split_var_copies(nir);
494
495 nir_lower_global_vars_to_local(nir);
496 nir_remove_dead_variables(nir, nir_var_function_temp);
497 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
498 .subgroup_size = 64,
499 .ballot_bit_size = 64,
500 .lower_to_scalar = 1,
501 .lower_subgroup_masks = 1,
502 .lower_shuffle = 1,
503 .lower_shuffle_to_32bit = 1,
504 .lower_vote_eq_to_ballot = 1,
505 });
506
507 nir_lower_load_const_to_scalar(nir);
508
509 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
510 radv_optimize_nir(nir, false, true);
511
512 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
513 * to remove any copies introduced by nir_opt_find_array_copies().
514 */
515 nir_lower_var_copies(nir);
516
517 /* Lower deref operations for compute shared memory. */
518 if (nir->info.stage == MESA_SHADER_COMPUTE) {
519 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
520 nir_var_mem_shared, shared_var_info);
521 NIR_PASS_V(nir, nir_lower_explicit_io,
522 nir_var_mem_shared, nir_address_format_32bit_offset);
523 }
524
525 /* Lower large variables that are always constant with load_constant
526 * intrinsics, which get turned into PC-relative loads from a data
527 * section next to the shader.
528 */
529 NIR_PASS_V(nir, nir_opt_large_constants,
530 glsl_get_natural_size_align_bytes, 16);
531
532 /* Indirect lowering must be called after the radv_optimize_nir() loop
533 * has been called at least once. Otherwise indirect lowering can
534 * bloat the instruction count of the loop and cause it to be
535 * considered too large for unrolling.
536 */
537 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
538 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
539
540 return nir;
541 }
542
543 static int
544 type_size_vec4(const struct glsl_type *type, bool bindless)
545 {
546 return glsl_count_attribute_slots(type, false);
547 }
548
549 static nir_variable *
550 find_layer_in_var(nir_shader *nir)
551 {
552 nir_foreach_variable(var, &nir->inputs) {
553 if (var->data.location == VARYING_SLOT_LAYER) {
554 return var;
555 }
556 }
557
558 nir_variable *var =
559 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
560 var->data.location = VARYING_SLOT_LAYER;
561 var->data.interpolation = INTERP_MODE_FLAT;
562 return var;
563 }
564
565 /* We use layered rendering to implement multiview, which means we need to map
566 * view_index to gl_Layer. The attachment lowering also uses needs to know the
567 * layer so that it can sample from the correct layer. The code generates a
568 * load from the layer_id sysval, but since we don't have a way to get at this
569 * information from the fragment shader, we also need to lower this to the
570 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
571 * slot, before lowering io, so that nir_assign_var_locations() will give the
572 * LAYER varying the correct driver_location.
573 */
574
575 static bool
576 lower_view_index(nir_shader *nir)
577 {
578 bool progress = false;
579 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
580 nir_builder b;
581 nir_builder_init(&b, entry);
582
583 nir_variable *layer = NULL;
584 nir_foreach_block(block, entry) {
585 nir_foreach_instr_safe(instr, block) {
586 if (instr->type != nir_instr_type_intrinsic)
587 continue;
588
589 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
590 if (load->intrinsic != nir_intrinsic_load_view_index &&
591 load->intrinsic != nir_intrinsic_load_layer_id)
592 continue;
593
594 if (!layer)
595 layer = find_layer_in_var(nir);
596
597 b.cursor = nir_before_instr(instr);
598 nir_ssa_def *def = nir_load_var(&b, layer);
599 nir_ssa_def_rewrite_uses(&load->dest.ssa,
600 nir_src_for_ssa(def));
601
602 nir_instr_remove(instr);
603 progress = true;
604 }
605 }
606
607 return progress;
608 }
609
610 void
611 radv_lower_fs_io(nir_shader *nir)
612 {
613 NIR_PASS_V(nir, lower_view_index);
614 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
615 MESA_SHADER_FRAGMENT);
616
617 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
618
619 /* This pass needs actual constants */
620 nir_opt_constant_folding(nir);
621
622 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
623 }
624
625
626 void *
627 radv_alloc_shader_memory(struct radv_device *device,
628 struct radv_shader_variant *shader)
629 {
630 mtx_lock(&device->shader_slab_mutex);
631 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
632 uint64_t offset = 0;
633 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
634 if (s->bo_offset - offset >= shader->code_size) {
635 shader->bo = slab->bo;
636 shader->bo_offset = offset;
637 list_addtail(&shader->slab_list, &s->slab_list);
638 mtx_unlock(&device->shader_slab_mutex);
639 return slab->ptr + offset;
640 }
641 offset = align_u64(s->bo_offset + s->code_size, 256);
642 }
643 if (slab->size - offset >= shader->code_size) {
644 shader->bo = slab->bo;
645 shader->bo_offset = offset;
646 list_addtail(&shader->slab_list, &slab->shaders);
647 mtx_unlock(&device->shader_slab_mutex);
648 return slab->ptr + offset;
649 }
650 }
651
652 mtx_unlock(&device->shader_slab_mutex);
653 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
654
655 slab->size = 256 * 1024;
656 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
657 RADEON_DOMAIN_VRAM,
658 RADEON_FLAG_NO_INTERPROCESS_SHARING |
659 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
660 0 : RADEON_FLAG_READ_ONLY),
661 RADV_BO_PRIORITY_SHADER);
662 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
663 list_inithead(&slab->shaders);
664
665 mtx_lock(&device->shader_slab_mutex);
666 list_add(&slab->slabs, &device->shader_slabs);
667
668 shader->bo = slab->bo;
669 shader->bo_offset = 0;
670 list_add(&shader->slab_list, &slab->shaders);
671 mtx_unlock(&device->shader_slab_mutex);
672 return slab->ptr;
673 }
674
675 void
676 radv_destroy_shader_slabs(struct radv_device *device)
677 {
678 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
679 device->ws->buffer_destroy(slab->bo);
680 free(slab);
681 }
682 mtx_destroy(&device->shader_slab_mutex);
683 }
684
685 /* For the UMR disassembler. */
686 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
687 #define DEBUGGER_NUM_MARKERS 5
688
689 static unsigned
690 radv_get_shader_binary_size(size_t code_size)
691 {
692 return code_size + DEBUGGER_NUM_MARKERS * 4;
693 }
694
695 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
696 const struct ac_shader_config *config_in,
697 const struct radv_shader_info *info,
698 gl_shader_stage stage,
699 struct ac_shader_config *config_out)
700 {
701 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
702 unsigned vgpr_comp_cnt = 0;
703 unsigned num_input_vgprs = info->num_input_vgprs;
704
705 if (stage == MESA_SHADER_FRAGMENT) {
706 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
707 }
708
709 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
710 /* +3 for scratch wave offset and VCC */
711 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
712 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
713 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
714 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
715 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
716 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
717
718 *config_out = *config_in;
719 config_out->num_vgprs = num_vgprs;
720 config_out->num_sgprs = num_sgprs;
721 config_out->num_shared_vgprs = num_shared_vgprs;
722
723 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
724 S_00B12C_SCRATCH_EN(scratch_enabled);
725
726 if (!pdevice->use_ngg_streamout) {
727 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
728 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
729 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
730 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
731 S_00B12C_SO_EN(!!info->so.num_outputs);
732 }
733
734 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
735 (info->wave_size == 32 ? 8 : 4)) |
736 S_00B848_DX10_CLAMP(1) |
737 S_00B848_FLOAT_MODE(config_out->float_mode);
738
739 if (pdevice->rad_info.chip_class >= GFX10) {
740 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
741 } else {
742 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
743 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
744 }
745
746 switch (stage) {
747 case MESA_SHADER_TESS_EVAL:
748 if (info->is_ngg) {
749 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
750 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
751 } else if (info->tes.as_es) {
752 assert(pdevice->rad_info.chip_class <= GFX8);
753 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
754
755 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
756 } else {
757 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
758 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
759
760 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
761 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
762 }
763 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
764 break;
765 case MESA_SHADER_TESS_CTRL:
766 if (pdevice->rad_info.chip_class >= GFX9) {
767 /* We need at least 2 components for LS.
768 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
769 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
770 */
771 if (pdevice->rad_info.chip_class >= GFX10) {
772 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
773 } else {
774 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
775 }
776 } else {
777 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
778 }
779 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
780 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
781 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
782 break;
783 case MESA_SHADER_VERTEX:
784 if (info->is_ngg) {
785 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
786 } else if (info->vs.as_ls) {
787 assert(pdevice->rad_info.chip_class <= GFX8);
788 /* We need at least 2 components for LS.
789 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
790 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
791 */
792 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
793 } else if (info->vs.as_es) {
794 assert(pdevice->rad_info.chip_class <= GFX8);
795 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
796 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
797 } else {
798 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
799 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
800 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
801 */
802 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
803 vgpr_comp_cnt = 3;
804 } else if (info->vs.export_prim_id) {
805 vgpr_comp_cnt = 2;
806 } else if (info->vs.needs_instance_id) {
807 vgpr_comp_cnt = 1;
808 } else {
809 vgpr_comp_cnt = 0;
810 }
811
812 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
813 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
814 }
815 break;
816 case MESA_SHADER_FRAGMENT:
817 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
818 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
819 break;
820 case MESA_SHADER_GEOMETRY:
821 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
822 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
823 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
824 break;
825 case MESA_SHADER_COMPUTE:
826 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
827 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
828 config_out->rsrc2 |=
829 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
830 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
831 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
832 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
833 info->cs.uses_thread_id[1] ? 1 : 0) |
834 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
835 S_00B84C_LDS_SIZE(config_in->lds_size);
836 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
837
838 break;
839 default:
840 unreachable("unsupported shader type");
841 break;
842 }
843
844 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
845 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
846 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
847 gl_shader_stage es_stage = stage;
848 if (stage == MESA_SHADER_GEOMETRY)
849 es_stage = info->gs.es_type;
850
851 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
852 if (es_stage == MESA_SHADER_VERTEX) {
853 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
854 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
855 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
856 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
857 } else
858 unreachable("Unexpected ES shader stage");
859
860 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
861 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
862 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
863 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
864 } else if (info->uses_prim_id) {
865 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
866 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
867 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
868 } else {
869 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
870 }
871
872 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
873 S_00B228_WGP_MODE(1);
874 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
875 S_00B22C_LDS_SIZE(config_in->lds_size) |
876 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
877 } else if (pdevice->rad_info.chip_class >= GFX9 &&
878 stage == MESA_SHADER_GEOMETRY) {
879 unsigned es_type = info->gs.es_type;
880 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
881
882 if (es_type == MESA_SHADER_VERTEX) {
883 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
884 if (info->vs.needs_instance_id) {
885 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
886 } else {
887 es_vgpr_comp_cnt = 0;
888 }
889 } else if (es_type == MESA_SHADER_TESS_EVAL) {
890 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
891 } else {
892 unreachable("invalid shader ES type");
893 }
894
895 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
896 * VGPR[0:4] are always loaded.
897 */
898 if (info->uses_invocation_id) {
899 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
900 } else if (info->uses_prim_id) {
901 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
902 } else if (info->gs.vertices_in >= 3) {
903 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
904 } else {
905 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
906 }
907
908 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
909 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
911 } else if (pdevice->rad_info.chip_class >= GFX9 &&
912 stage == MESA_SHADER_TESS_CTRL) {
913 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
914 } else {
915 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
916 }
917 }
918
919 struct radv_shader_variant *
920 radv_shader_variant_create(struct radv_device *device,
921 const struct radv_shader_binary *binary,
922 bool keep_shader_info)
923 {
924 struct ac_shader_config config = {0};
925 struct ac_rtld_binary rtld_binary = {0};
926 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
927 if (!variant)
928 return NULL;
929
930 variant->ref_count = 1;
931
932 if (binary->type == RADV_BINARY_TYPE_RTLD) {
933 struct ac_rtld_symbol lds_symbols[2];
934 unsigned num_lds_symbols = 0;
935 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
936 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
937
938 if (device->physical_device->rad_info.chip_class >= GFX9 &&
939 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
940 !binary->is_gs_copy_shader) {
941 /* We add this symbol even on LLVM <= 8 to ensure that
942 * shader->config.lds_size is set correctly below.
943 */
944 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
945 sym->name = "esgs_ring";
946 sym->size = binary->info.ngg_info.esgs_ring_size;
947 sym->align = 64 * 1024;
948 }
949
950 if (binary->info.is_ngg &&
951 binary->stage == MESA_SHADER_GEOMETRY) {
952 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
953 sym->name = "ngg_emit";
954 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
955 sym->align = 4;
956 }
957
958 struct ac_rtld_open_info open_info = {
959 .info = &device->physical_device->rad_info,
960 .shader_type = binary->stage,
961 .wave_size = binary->info.wave_size,
962 .num_parts = 1,
963 .elf_ptrs = &elf_data,
964 .elf_sizes = &elf_size,
965 .num_shared_lds_symbols = num_lds_symbols,
966 .shared_lds_symbols = lds_symbols,
967 };
968
969 if (!ac_rtld_open(&rtld_binary, open_info)) {
970 free(variant);
971 return NULL;
972 }
973
974 if (!ac_rtld_read_config(&rtld_binary, &config)) {
975 ac_rtld_close(&rtld_binary);
976 free(variant);
977 return NULL;
978 }
979
980 /* Enable 64-bit and 16-bit denormals, because there is no performance
981 * cost.
982 *
983 * If denormals are enabled, all floating-point output modifiers are
984 * ignored.
985 *
986 * Don't enable denormals for 32-bit floats, because:
987 * - Floating-point output modifiers would be ignored by the hw.
988 * - Some opcodes don't support denormals, such as v_mad_f32. We would
989 * have to stop using those.
990 * - GFX6 & GFX7 would be very slow.
991 */
992 config.float_mode |= V_00B028_FP_64_DENORMS;
993
994 if (rtld_binary.lds_size > 0) {
995 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
996 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
997 }
998
999 variant->code_size = rtld_binary.rx_size;
1000 variant->exec_size = rtld_binary.exec_size;
1001 } else {
1002 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1003 config = ((struct radv_shader_binary_legacy *)binary)->config;
1004 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1005 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1006 }
1007
1008 variant->info = binary->info;
1009 radv_postprocess_config(device->physical_device, &config, &binary->info,
1010 binary->stage, &variant->config);
1011
1012 if (radv_device_use_secure_compile(device->instance)) {
1013 if (binary->type == RADV_BINARY_TYPE_RTLD)
1014 ac_rtld_close(&rtld_binary);
1015
1016 return variant;
1017 }
1018
1019 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1020
1021 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1022 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1023 struct ac_rtld_upload_info info = {
1024 .binary = &rtld_binary,
1025 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1026 .rx_ptr = dest_ptr,
1027 };
1028
1029 if (!ac_rtld_upload(&info)) {
1030 radv_shader_variant_destroy(device, variant);
1031 ac_rtld_close(&rtld_binary);
1032 return NULL;
1033 }
1034
1035 if (keep_shader_info ||
1036 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1037 const char *disasm_data;
1038 size_t disasm_size;
1039 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1040 radv_shader_variant_destroy(device, variant);
1041 ac_rtld_close(&rtld_binary);
1042 return NULL;
1043 }
1044
1045 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1046 variant->disasm_string = malloc(disasm_size + 1);
1047 memcpy(variant->disasm_string, disasm_data, disasm_size);
1048 variant->disasm_string[disasm_size] = 0;
1049 }
1050
1051 ac_rtld_close(&rtld_binary);
1052 } else {
1053 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1054 memcpy(dest_ptr, bin->data, bin->code_size);
1055
1056 /* Add end-of-code markers for the UMR disassembler. */
1057 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1058 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1059 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1060
1061 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1062 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1063 }
1064 return variant;
1065 }
1066
1067 static char *
1068 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1069 int shader_count)
1070 {
1071 char *data = NULL;
1072 char *ret = NULL;
1073 size_t size = 0;
1074 FILE *f = open_memstream(&data, &size);
1075 if (f) {
1076 for (int i = 0; i < shader_count; ++i)
1077 nir_print_shader(shaders[i], f);
1078 fclose(f);
1079 }
1080
1081 ret = malloc(size + 1);
1082 if (ret) {
1083 memcpy(ret, data, size);
1084 ret[size] = 0;
1085 }
1086 free(data);
1087 return ret;
1088 }
1089
1090 static struct radv_shader_variant *
1091 shader_variant_compile(struct radv_device *device,
1092 struct radv_shader_module *module,
1093 struct nir_shader * const *shaders,
1094 int shader_count,
1095 gl_shader_stage stage,
1096 struct radv_shader_info *info,
1097 struct radv_nir_compiler_options *options,
1098 bool gs_copy_shader,
1099 bool keep_shader_info,
1100 bool use_aco,
1101 struct radv_shader_binary **binary_out)
1102 {
1103 enum radeon_family chip_family = device->physical_device->rad_info.family;
1104 struct radv_shader_binary *binary = NULL;
1105
1106 options->family = chip_family;
1107 options->chip_class = device->physical_device->rad_info.chip_class;
1108 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1109 options->dump_preoptir = options->dump_shader &&
1110 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1111 options->record_ir = keep_shader_info;
1112 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1113 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1114 options->address32_hi = device->physical_device->rad_info.address32_hi;
1115 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1116 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1117
1118 struct radv_shader_args args = {};
1119 args.options = options;
1120 args.shader_info = info;
1121 args.is_gs_copy_shader = gs_copy_shader;
1122 radv_declare_shader_args(&args,
1123 gs_copy_shader ? MESA_SHADER_VERTEX
1124 : shaders[shader_count - 1]->info.stage,
1125 shader_count >= 2,
1126 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1127 : MESA_SHADER_VERTEX);
1128
1129 if (!use_aco || options->dump_shader || options->record_ir)
1130 ac_init_llvm_once();
1131
1132 if (use_aco) {
1133 aco_compile_shader(shader_count, shaders, &binary, &args);
1134 binary->info = *info;
1135 } else {
1136 enum ac_target_machine_options tm_options = 0;
1137 struct ac_llvm_compiler ac_llvm;
1138 bool thread_compiler;
1139
1140 tm_options |= AC_TM_SUPPORTS_SPILL;
1141 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1142 tm_options |= AC_TM_SISCHED;
1143 if (options->check_ir)
1144 tm_options |= AC_TM_CHECK_IR;
1145 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1146 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1147
1148 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1149 radv_init_llvm_compiler(&ac_llvm,
1150 thread_compiler,
1151 chip_family, tm_options,
1152 info->wave_size);
1153
1154 if (gs_copy_shader) {
1155 assert(shader_count == 1);
1156 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1157 &args);
1158 } else {
1159 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1160 shaders, shader_count);
1161 }
1162
1163 binary->info = *info;
1164 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1165 }
1166
1167 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1168 keep_shader_info);
1169 if (!variant) {
1170 free(binary);
1171 return NULL;
1172 }
1173 variant->aco_used = use_aco;
1174
1175 if (options->dump_shader) {
1176 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1177 }
1178
1179
1180 if (keep_shader_info) {
1181 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1182 if (!gs_copy_shader && !module->nir) {
1183 variant->spirv = malloc(module->size);
1184 if (!variant->spirv) {
1185 free(variant);
1186 free(binary);
1187 return NULL;
1188 }
1189
1190 memcpy(variant->spirv, module->data, module->size);
1191 variant->spirv_size = module->size;
1192 }
1193 }
1194
1195 if (binary_out)
1196 *binary_out = binary;
1197 else
1198 free(binary);
1199
1200 return variant;
1201 }
1202
1203 struct radv_shader_variant *
1204 radv_shader_variant_compile(struct radv_device *device,
1205 struct radv_shader_module *module,
1206 struct nir_shader *const *shaders,
1207 int shader_count,
1208 struct radv_pipeline_layout *layout,
1209 const struct radv_shader_variant_key *key,
1210 struct radv_shader_info *info,
1211 bool keep_shader_info,
1212 bool use_aco,
1213 struct radv_shader_binary **binary_out)
1214 {
1215 struct radv_nir_compiler_options options = {0};
1216
1217 options.layout = layout;
1218 if (key)
1219 options.key = *key;
1220
1221 options.explicit_scratch_args = use_aco;
1222 options.robust_buffer_access = device->robust_buffer_access;
1223
1224 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1225 &options, false, keep_shader_info, use_aco, binary_out);
1226 }
1227
1228 struct radv_shader_variant *
1229 radv_create_gs_copy_shader(struct radv_device *device,
1230 struct nir_shader *shader,
1231 struct radv_shader_info *info,
1232 struct radv_shader_binary **binary_out,
1233 bool keep_shader_info,
1234 bool multiview)
1235 {
1236 struct radv_nir_compiler_options options = {0};
1237
1238 options.key.has_multiview_view_index = multiview;
1239
1240 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1241 info, &options, true, keep_shader_info, false, binary_out);
1242 }
1243
1244 void
1245 radv_shader_variant_destroy(struct radv_device *device,
1246 struct radv_shader_variant *variant)
1247 {
1248 if (!p_atomic_dec_zero(&variant->ref_count))
1249 return;
1250
1251 mtx_lock(&device->shader_slab_mutex);
1252 list_del(&variant->slab_list);
1253 mtx_unlock(&device->shader_slab_mutex);
1254
1255 free(variant->spirv);
1256 free(variant->nir_string);
1257 free(variant->disasm_string);
1258 free(variant->ir_string);
1259 free(variant);
1260 }
1261
1262 const char *
1263 radv_get_shader_name(struct radv_shader_info *info,
1264 gl_shader_stage stage)
1265 {
1266 switch (stage) {
1267 case MESA_SHADER_VERTEX:
1268 if (info->vs.as_ls)
1269 return "Vertex Shader as LS";
1270 else if (info->vs.as_es)
1271 return "Vertex Shader as ES";
1272 else if (info->is_ngg)
1273 return "Vertex Shader as ESGS";
1274 else
1275 return "Vertex Shader as VS";
1276 case MESA_SHADER_TESS_CTRL:
1277 return "Tessellation Control Shader";
1278 case MESA_SHADER_TESS_EVAL:
1279 if (info->tes.as_es)
1280 return "Tessellation Evaluation Shader as ES";
1281 else if (info->is_ngg)
1282 return "Tessellation Evaluation Shader as ESGS";
1283 else
1284 return "Tessellation Evaluation Shader as VS";
1285 case MESA_SHADER_GEOMETRY:
1286 return "Geometry Shader";
1287 case MESA_SHADER_FRAGMENT:
1288 return "Pixel Shader";
1289 case MESA_SHADER_COMPUTE:
1290 return "Compute Shader";
1291 default:
1292 return "Unknown shader";
1293 };
1294 }
1295
1296 unsigned
1297 radv_get_max_workgroup_size(enum chip_class chip_class,
1298 gl_shader_stage stage,
1299 const unsigned *sizes)
1300 {
1301 switch (stage) {
1302 case MESA_SHADER_TESS_CTRL:
1303 return chip_class >= GFX7 ? 128 : 64;
1304 case MESA_SHADER_GEOMETRY:
1305 return chip_class >= GFX9 ? 128 : 64;
1306 case MESA_SHADER_COMPUTE:
1307 break;
1308 default:
1309 return 0;
1310 }
1311
1312 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1313 return max_workgroup_size;
1314 }
1315
1316 unsigned
1317 radv_get_max_waves(struct radv_device *device,
1318 struct radv_shader_variant *variant,
1319 gl_shader_stage stage)
1320 {
1321 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1322 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1323 uint8_t wave_size = variant->info.wave_size;
1324 struct ac_shader_config *conf = &variant->config;
1325 unsigned max_simd_waves;
1326 unsigned lds_per_wave = 0;
1327
1328 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1329
1330 if (stage == MESA_SHADER_FRAGMENT) {
1331 lds_per_wave = conf->lds_size * lds_increment +
1332 align(variant->info.ps.num_interp * 48,
1333 lds_increment);
1334 } else if (stage == MESA_SHADER_COMPUTE) {
1335 unsigned max_workgroup_size =
1336 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1337 lds_per_wave = (conf->lds_size * lds_increment) /
1338 DIV_ROUND_UP(max_workgroup_size, wave_size);
1339 }
1340
1341 if (conf->num_sgprs) {
1342 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1343 max_simd_waves =
1344 MIN2(max_simd_waves,
1345 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1346 sgprs);
1347 }
1348
1349 if (conf->num_vgprs) {
1350 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1351 max_simd_waves =
1352 MIN2(max_simd_waves,
1353 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1354 }
1355
1356 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1357 * that PS can use.
1358 */
1359 if (lds_per_wave)
1360 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1361
1362 return max_simd_waves;
1363 }
1364
1365 static void
1366 generate_shader_stats(struct radv_device *device,
1367 struct radv_shader_variant *variant,
1368 gl_shader_stage stage,
1369 struct _mesa_string_buffer *buf)
1370 {
1371 struct ac_shader_config *conf = &variant->config;
1372 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1373
1374 if (stage == MESA_SHADER_FRAGMENT) {
1375 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1376 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1377 "SPI_PS_INPUT_ENA = 0x%04x\n",
1378 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1379 }
1380
1381 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1382 "SGPRS: %d\n"
1383 "VGPRS: %d\n"
1384 "Spilled SGPRs: %d\n"
1385 "Spilled VGPRs: %d\n"
1386 "PrivMem VGPRS: %d\n"
1387 "Code Size: %d bytes\n"
1388 "LDS: %d blocks\n"
1389 "Scratch: %d bytes per wave\n"
1390 "Max Waves: %d\n"
1391 "********************\n\n\n",
1392 conf->num_sgprs, conf->num_vgprs,
1393 conf->spilled_sgprs, conf->spilled_vgprs,
1394 variant->info.private_mem_vgprs, variant->exec_size,
1395 conf->lds_size, conf->scratch_bytes_per_wave,
1396 max_simd_waves);
1397 }
1398
1399 void
1400 radv_shader_dump_stats(struct radv_device *device,
1401 struct radv_shader_variant *variant,
1402 gl_shader_stage stage,
1403 FILE *file)
1404 {
1405 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1406
1407 generate_shader_stats(device, variant, stage, buf);
1408
1409 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1410 fprintf(file, "%s", buf->buf);
1411
1412 _mesa_string_buffer_destroy(buf);
1413 }
1414
1415 VkResult
1416 radv_GetShaderInfoAMD(VkDevice _device,
1417 VkPipeline _pipeline,
1418 VkShaderStageFlagBits shaderStage,
1419 VkShaderInfoTypeAMD infoType,
1420 size_t* pInfoSize,
1421 void* pInfo)
1422 {
1423 RADV_FROM_HANDLE(radv_device, device, _device);
1424 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1425 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1426 struct radv_shader_variant *variant = pipeline->shaders[stage];
1427 struct _mesa_string_buffer *buf;
1428 VkResult result = VK_SUCCESS;
1429
1430 /* Spec doesn't indicate what to do if the stage is invalid, so just
1431 * return no info for this. */
1432 if (!variant)
1433 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1434
1435 switch (infoType) {
1436 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1437 if (!pInfo) {
1438 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1439 } else {
1440 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1441 struct ac_shader_config *conf = &variant->config;
1442
1443 VkShaderStatisticsInfoAMD statistics = {};
1444 statistics.shaderStageMask = shaderStage;
1445 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1446 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1447 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1448
1449 if (stage == MESA_SHADER_COMPUTE) {
1450 unsigned *local_size = variant->info.cs.block_size;
1451 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1452
1453 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1454 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1455
1456 statistics.computeWorkGroupSize[0] = local_size[0];
1457 statistics.computeWorkGroupSize[1] = local_size[1];
1458 statistics.computeWorkGroupSize[2] = local_size[2];
1459 } else {
1460 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1461 }
1462
1463 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1464 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1465 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1466 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1467 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1468
1469 size_t size = *pInfoSize;
1470 *pInfoSize = sizeof(statistics);
1471
1472 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1473
1474 if (size < *pInfoSize)
1475 result = VK_INCOMPLETE;
1476 }
1477
1478 break;
1479 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1480 buf = _mesa_string_buffer_create(NULL, 1024);
1481
1482 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1483 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1484 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1485 generate_shader_stats(device, variant, stage, buf);
1486
1487 /* Need to include the null terminator. */
1488 size_t length = buf->length + 1;
1489
1490 if (!pInfo) {
1491 *pInfoSize = length;
1492 } else {
1493 size_t size = *pInfoSize;
1494 *pInfoSize = length;
1495
1496 memcpy(pInfo, buf->buf, MIN2(size, length));
1497
1498 if (size < length)
1499 result = VK_INCOMPLETE;
1500 }
1501
1502 _mesa_string_buffer_destroy(buf);
1503 break;
1504 default:
1505 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1506 result = VK_ERROR_FEATURE_NOT_PRESENT;
1507 break;
1508 }
1509
1510 return result;
1511 }