2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
63 .lower_pack_snorm_2x16
= true,
64 .lower_pack_snorm_4x8
= true,
65 .lower_pack_unorm_2x16
= true,
66 .lower_pack_unorm_4x8
= true,
67 .lower_unpack_snorm_2x16
= true,
68 .lower_unpack_snorm_4x8
= true,
69 .lower_unpack_unorm_2x16
= true,
70 .lower_unpack_unorm_4x8
= true,
71 .lower_extract_byte
= true,
72 .lower_extract_word
= true,
75 .lower_mul_2x32_64
= true,
76 .max_unroll_iterations
= 32
79 VkResult
radv_CreateShaderModule(
81 const VkShaderModuleCreateInfo
* pCreateInfo
,
82 const VkAllocationCallbacks
* pAllocator
,
83 VkShaderModule
* pShaderModule
)
85 RADV_FROM_HANDLE(radv_device
, device
, _device
);
86 struct radv_shader_module
*module
;
88 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
89 assert(pCreateInfo
->flags
== 0);
91 module
= vk_alloc2(&device
->alloc
, pAllocator
,
92 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
93 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
95 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
98 module
->size
= pCreateInfo
->codeSize
;
99 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
101 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
103 *pShaderModule
= radv_shader_module_to_handle(module
);
108 void radv_DestroyShaderModule(
110 VkShaderModule _module
,
111 const VkAllocationCallbacks
* pAllocator
)
113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
114 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
119 vk_free2(&device
->alloc
, pAllocator
, module
);
123 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
131 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
132 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
134 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
135 NIR_PASS_V(shader
, nir_lower_pack
);
138 /* Only run this pass in the first call to
139 * radv_optimize_nir. Later calls assume that we've
140 * lowered away any copy_deref instructions and we
141 * don't want to introduce any more.
143 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
146 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
147 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
149 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
150 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
152 NIR_PASS(progress
, shader
, nir_copy_prop
);
153 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
154 NIR_PASS(progress
, shader
, nir_opt_dce
);
155 if (nir_opt_trivial_continues(shader
)) {
157 NIR_PASS(progress
, shader
, nir_copy_prop
);
158 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
159 NIR_PASS(progress
, shader
, nir_opt_dce
);
161 NIR_PASS(progress
, shader
, nir_opt_if
, true);
162 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
163 NIR_PASS(progress
, shader
, nir_opt_cse
);
164 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
165 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
166 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
167 NIR_PASS(progress
, shader
, nir_opt_undef
);
168 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
169 if (shader
->options
->max_unroll_iterations
) {
170 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
172 } while (progress
&& !optimize_conservatively
);
174 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
175 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
179 radv_shader_compile_to_nir(struct radv_device
*device
,
180 struct radv_shader_module
*module
,
181 const char *entrypoint_name
,
182 gl_shader_stage stage
,
183 const VkSpecializationInfo
*spec_info
,
184 const VkPipelineCreateFlags flags
,
185 const struct radv_pipeline_layout
*layout
)
188 nir_function
*entry_point
;
190 /* Some things such as our meta clear/blit code will give us a NIR
191 * shader directly. In that case, we just ignore the SPIR-V entirely
192 * and just use the NIR shader */
194 nir
->options
= &nir_options
;
195 nir_validate_shader(nir
, "in internal shader");
197 assert(exec_list_length(&nir
->functions
) == 1);
198 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
199 entry_point
= exec_node_data(nir_function
, node
, node
);
201 uint32_t *spirv
= (uint32_t *) module
->data
;
202 assert(module
->size
% 4 == 0);
204 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
205 radv_print_spirv(spirv
, module
->size
, stderr
);
207 uint32_t num_spec_entries
= 0;
208 struct nir_spirv_specialization
*spec_entries
= NULL
;
209 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
210 num_spec_entries
= spec_info
->mapEntryCount
;
211 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
212 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
213 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
214 const void *data
= spec_info
->pData
+ entry
.offset
;
215 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
217 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
218 if (spec_info
->dataSize
== 8)
219 spec_entries
[i
].data64
= *(const uint64_t *)data
;
221 spec_entries
[i
].data32
= *(const uint32_t *)data
;
224 const struct spirv_to_nir_options spirv_options
= {
225 .lower_ubo_ssbo_access_to_offsets
= true,
227 .derivative_group
= true,
228 .descriptor_array_dynamic_indexing
= true,
229 .descriptor_array_non_uniform_indexing
= true,
230 .descriptor_indexing
= true,
231 .device_group
= true,
232 .draw_parameters
= true,
236 .geometry_streams
= true,
237 .image_read_without_format
= true,
238 .image_write_without_format
= true,
242 .int64_atomics
= true,
244 .physical_storage_buffer_address
= true,
245 .runtime_descriptor_array
= true,
246 .shader_viewport_index_layer
= true,
247 .stencil_export
= true,
248 .storage_8bit
= true,
249 .storage_16bit
= true,
250 .storage_image_ms
= true,
251 .subgroup_arithmetic
= true,
252 .subgroup_ballot
= true,
253 .subgroup_basic
= true,
254 .subgroup_quad
= true,
255 .subgroup_shuffle
= true,
256 .subgroup_vote
= true,
257 .tessellation
= true,
258 .transform_feedback
= true,
259 .trinary_minmax
= true,
260 .variable_pointers
= true,
262 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
263 .ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
264 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
265 .push_const_ptr_type
= glsl_uint_type(),
266 .shared_ptr_type
= glsl_uint_type(),
268 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
269 spec_entries
, num_spec_entries
,
270 stage
, entrypoint_name
,
271 &spirv_options
, &nir_options
);
272 nir
= entry_point
->shader
;
273 assert(nir
->info
.stage
== stage
);
274 nir_validate_shader(nir
, "after spirv_to_nir");
278 /* We have to lower away local constant initializers right before we
279 * inline functions. That way they get properly initialized at the top
280 * of the function and not at the top of its caller.
282 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
283 NIR_PASS_V(nir
, nir_lower_returns
);
284 NIR_PASS_V(nir
, nir_inline_functions
);
285 NIR_PASS_V(nir
, nir_opt_deref
);
287 /* Pick off the single entrypoint that we want */
288 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
289 if (func
!= entry_point
)
290 exec_node_remove(&func
->node
);
292 assert(exec_list_length(&nir
->functions
) == 1);
293 entry_point
->name
= ralloc_strdup(entry_point
, "main");
295 /* Make sure we lower constant initializers on output variables so that
296 * nir_remove_dead_variables below sees the corresponding stores
298 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
300 /* Now that we've deleted all but the main function, we can go ahead and
301 * lower the rest of the constant initializers.
303 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
305 /* Split member structs. We do this before lower_io_to_temporaries so that
306 * it doesn't lower system values to temporaries by accident.
308 NIR_PASS_V(nir
, nir_split_var_copies
);
309 NIR_PASS_V(nir
, nir_split_per_member_structs
);
311 NIR_PASS_V(nir
, nir_remove_dead_variables
,
312 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
314 NIR_PASS_V(nir
, nir_lower_system_values
);
315 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
316 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
319 /* Vulkan uses the separate-shader linking model */
320 nir
->info
.separate_shader
= true;
322 nir_shader_gather_info(nir
, entry_point
->impl
);
324 static const nir_lower_tex_options tex_options
= {
326 .lower_tg4_offsets
= true,
329 nir_lower_tex(nir
, &tex_options
);
331 nir_lower_vars_to_ssa(nir
);
333 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
334 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
335 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
336 nir_shader_get_entrypoint(nir
), true, true);
337 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
338 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
339 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
340 nir_shader_get_entrypoint(nir
), true, false);
343 nir_split_var_copies(nir
);
345 nir_lower_global_vars_to_local(nir
);
346 nir_remove_dead_variables(nir
, nir_var_function_temp
);
347 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
349 .ballot_bit_size
= 64,
350 .lower_to_scalar
= 1,
351 .lower_subgroup_masks
= 1,
353 .lower_shuffle_to_32bit
= 1,
354 .lower_vote_eq_to_ballot
= 1,
357 nir_lower_load_const_to_scalar(nir
);
359 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
360 radv_optimize_nir(nir
, false, true);
362 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
363 * to remove any copies introduced by nir_opt_find_array_copies().
365 nir_lower_var_copies(nir
);
367 /* Indirect lowering must be called after the radv_optimize_nir() loop
368 * has been called at least once. Otherwise indirect lowering can
369 * bloat the instruction count of the loop and cause it to be
370 * considered too large for unrolling.
372 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
373 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
379 radv_alloc_shader_memory(struct radv_device
*device
,
380 struct radv_shader_variant
*shader
)
382 mtx_lock(&device
->shader_slab_mutex
);
383 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
385 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
386 if (s
->bo_offset
- offset
>= shader
->code_size
) {
387 shader
->bo
= slab
->bo
;
388 shader
->bo_offset
= offset
;
389 list_addtail(&shader
->slab_list
, &s
->slab_list
);
390 mtx_unlock(&device
->shader_slab_mutex
);
391 return slab
->ptr
+ offset
;
393 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
395 if (slab
->size
- offset
>= shader
->code_size
) {
396 shader
->bo
= slab
->bo
;
397 shader
->bo_offset
= offset
;
398 list_addtail(&shader
->slab_list
, &slab
->shaders
);
399 mtx_unlock(&device
->shader_slab_mutex
);
400 return slab
->ptr
+ offset
;
404 mtx_unlock(&device
->shader_slab_mutex
);
405 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
407 slab
->size
= 256 * 1024;
408 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
410 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
411 (device
->physical_device
->cpdma_prefetch_writes_memory
?
412 0 : RADEON_FLAG_READ_ONLY
),
413 RADV_BO_PRIORITY_SHADER
);
414 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
415 list_inithead(&slab
->shaders
);
417 mtx_lock(&device
->shader_slab_mutex
);
418 list_add(&slab
->slabs
, &device
->shader_slabs
);
420 shader
->bo
= slab
->bo
;
421 shader
->bo_offset
= 0;
422 list_add(&shader
->slab_list
, &slab
->shaders
);
423 mtx_unlock(&device
->shader_slab_mutex
);
428 radv_destroy_shader_slabs(struct radv_device
*device
)
430 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
431 device
->ws
->buffer_destroy(slab
->bo
);
434 mtx_destroy(&device
->shader_slab_mutex
);
437 /* For the UMR disassembler. */
438 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
439 #define DEBUGGER_NUM_MARKERS 5
442 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
444 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
448 radv_fill_shader_variant(struct radv_device
*device
,
449 struct radv_shader_variant
*variant
,
450 struct ac_shader_binary
*binary
,
451 gl_shader_stage stage
)
453 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
454 struct radv_shader_info
*info
= &variant
->info
.info
;
455 unsigned vgpr_comp_cnt
= 0;
457 variant
->code_size
= radv_get_shader_binary_size(binary
);
458 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
459 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
460 S_00B12C_SCRATCH_EN(scratch_enabled
) |
461 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
462 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
463 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
464 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
465 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
467 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
468 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
469 S_00B848_DX10_CLAMP(1) |
470 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
473 case MESA_SHADER_TESS_EVAL
:
475 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
477 case MESA_SHADER_TESS_CTRL
:
478 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
479 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
481 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
484 case MESA_SHADER_VERTEX
:
485 case MESA_SHADER_GEOMETRY
:
486 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
488 case MESA_SHADER_FRAGMENT
:
490 case MESA_SHADER_COMPUTE
:
492 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
493 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
494 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
495 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
496 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
497 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
498 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
501 unreachable("unsupported shader type");
505 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
506 stage
== MESA_SHADER_GEOMETRY
) {
507 unsigned es_type
= variant
->info
.gs
.es_type
;
508 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
510 if (es_type
== MESA_SHADER_VERTEX
) {
511 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
512 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
513 es_vgpr_comp_cnt
= 3;
515 unreachable("invalid shader ES type");
518 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
519 * VGPR[0:4] are always loaded.
521 if (info
->uses_invocation_id
) {
522 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
523 } else if (info
->uses_prim_id
) {
524 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
525 } else if (variant
->info
.gs
.vertices_in
>= 3) {
526 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
528 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
531 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
532 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
533 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
534 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
535 stage
== MESA_SHADER_TESS_CTRL
) {
536 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
538 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
541 void *ptr
= radv_alloc_shader_memory(device
, variant
);
542 memcpy(ptr
, binary
->code
, binary
->code_size
);
544 /* Add end-of-code markers for the UMR disassembler. */
545 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
546 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
547 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
551 static void radv_init_llvm_target()
553 LLVMInitializeAMDGPUTargetInfo();
554 LLVMInitializeAMDGPUTarget();
555 LLVMInitializeAMDGPUTargetMC();
556 LLVMInitializeAMDGPUAsmPrinter();
558 /* For inline assembly. */
559 LLVMInitializeAMDGPUAsmParser();
561 /* Workaround for bug in llvm 4.0 that causes image intrinsics
563 * https://reviews.llvm.org/D26348
565 * Workaround for bug in llvm that causes the GPU to hang in presence
566 * of nested loops because there is an exec mask issue. The proper
567 * solution is to fix LLVM but this might require a bunch of work.
568 * https://bugs.llvm.org/show_bug.cgi?id=37744
570 * "mesa" is the prefix for error messages.
572 if (HAVE_LLVM
>= 0x0800) {
573 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
574 LLVMParseCommandLineOptions(2, argv
, NULL
);
577 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
578 "-amdgpu-skip-threshold=1" };
579 LLVMParseCommandLineOptions(3, argv
, NULL
);
583 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
585 static void radv_init_llvm_once(void)
587 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
590 static struct radv_shader_variant
*
591 shader_variant_create(struct radv_device
*device
,
592 struct radv_shader_module
*module
,
593 struct nir_shader
* const *shaders
,
595 gl_shader_stage stage
,
596 struct radv_nir_compiler_options
*options
,
599 unsigned *code_size_out
)
601 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
602 enum ac_target_machine_options tm_options
= 0;
603 struct radv_shader_variant
*variant
;
604 struct ac_shader_binary binary
;
605 struct ac_llvm_compiler ac_llvm
;
606 bool thread_compiler
;
607 variant
= calloc(1, sizeof(struct radv_shader_variant
));
611 options
->family
= chip_family
;
612 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
613 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
614 options
->dump_preoptir
= options
->dump_shader
&&
615 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
616 options
->record_llvm_ir
= device
->keep_shader_info
;
617 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
618 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
619 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
621 if (options
->supports_spill
)
622 tm_options
|= AC_TM_SUPPORTS_SPILL
;
623 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
624 tm_options
|= AC_TM_SISCHED
;
625 if (options
->check_ir
)
626 tm_options
|= AC_TM_CHECK_IR
;
628 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
629 radv_init_llvm_once();
630 radv_init_llvm_compiler(&ac_llvm
,
632 chip_family
, tm_options
);
633 if (gs_copy_shader
) {
634 assert(shader_count
== 1);
635 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
636 &variant
->config
, &variant
->info
,
639 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
640 &variant
->info
, shaders
, shader_count
,
644 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
646 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
649 *code_out
= binary
.code
;
650 *code_size_out
= binary
.code_size
;
655 free(binary
.global_symbol_offsets
);
657 variant
->ref_count
= 1;
659 if (device
->keep_shader_info
) {
660 variant
->disasm_string
= binary
.disasm_string
;
661 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
662 if (!gs_copy_shader
&& !module
->nir
) {
663 variant
->nir
= *shaders
;
664 variant
->spirv
= (uint32_t *)module
->data
;
665 variant
->spirv_size
= module
->size
;
668 free(binary
.disasm_string
);
674 struct radv_shader_variant
*
675 radv_shader_variant_create(struct radv_device
*device
,
676 struct radv_shader_module
*module
,
677 struct nir_shader
*const *shaders
,
679 struct radv_pipeline_layout
*layout
,
680 const struct radv_shader_variant_key
*key
,
682 unsigned *code_size_out
)
684 struct radv_nir_compiler_options options
= {0};
686 options
.layout
= layout
;
690 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
691 options
.supports_spill
= true;
693 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
694 &options
, false, code_out
, code_size_out
);
697 struct radv_shader_variant
*
698 radv_create_gs_copy_shader(struct radv_device
*device
,
699 struct nir_shader
*shader
,
701 unsigned *code_size_out
,
704 struct radv_nir_compiler_options options
= {0};
706 options
.key
.has_multiview_view_index
= multiview
;
708 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
709 &options
, true, code_out
, code_size_out
);
713 radv_shader_variant_destroy(struct radv_device
*device
,
714 struct radv_shader_variant
*variant
)
716 if (!p_atomic_dec_zero(&variant
->ref_count
))
719 mtx_lock(&device
->shader_slab_mutex
);
720 list_del(&variant
->slab_list
);
721 mtx_unlock(&device
->shader_slab_mutex
);
723 ralloc_free(variant
->nir
);
724 free(variant
->disasm_string
);
725 free(variant
->llvm_ir_string
);
730 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
733 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
734 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
735 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
736 case MESA_SHADER_COMPUTE
: return "Compute Shader";
737 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
738 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
740 return "Unknown shader";
745 generate_shader_stats(struct radv_device
*device
,
746 struct radv_shader_variant
*variant
,
747 gl_shader_stage stage
,
748 struct _mesa_string_buffer
*buf
)
750 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
751 unsigned lds_increment
= chip_class
>= CIK
? 512 : 256;
752 struct ac_shader_config
*conf
;
753 unsigned max_simd_waves
;
754 unsigned lds_per_wave
= 0;
756 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
758 conf
= &variant
->config
;
760 if (stage
== MESA_SHADER_FRAGMENT
) {
761 lds_per_wave
= conf
->lds_size
* lds_increment
+
762 align(variant
->info
.fs
.num_interp
* 48,
764 } else if (stage
== MESA_SHADER_COMPUTE
) {
765 unsigned max_workgroup_size
=
766 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
767 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
768 DIV_ROUND_UP(max_workgroup_size
, 64);
774 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
779 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
781 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
785 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
787 if (stage
== MESA_SHADER_FRAGMENT
) {
788 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
789 "SPI_PS_INPUT_ADDR = 0x%04x\n"
790 "SPI_PS_INPUT_ENA = 0x%04x\n",
791 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
794 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
797 "Spilled SGPRs: %d\n"
798 "Spilled VGPRs: %d\n"
799 "PrivMem VGPRS: %d\n"
800 "Code Size: %d bytes\n"
802 "Scratch: %d bytes per wave\n"
804 "********************\n\n\n",
805 conf
->num_sgprs
, conf
->num_vgprs
,
806 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
807 variant
->info
.private_mem_vgprs
, variant
->code_size
,
808 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
813 radv_shader_dump_stats(struct radv_device
*device
,
814 struct radv_shader_variant
*variant
,
815 gl_shader_stage stage
,
818 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
820 generate_shader_stats(device
, variant
, stage
, buf
);
822 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
823 fprintf(file
, "%s", buf
->buf
);
825 _mesa_string_buffer_destroy(buf
);
829 radv_GetShaderInfoAMD(VkDevice _device
,
830 VkPipeline _pipeline
,
831 VkShaderStageFlagBits shaderStage
,
832 VkShaderInfoTypeAMD infoType
,
836 RADV_FROM_HANDLE(radv_device
, device
, _device
);
837 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
838 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
839 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
840 struct _mesa_string_buffer
*buf
;
841 VkResult result
= VK_SUCCESS
;
843 /* Spec doesn't indicate what to do if the stage is invalid, so just
844 * return no info for this. */
846 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
849 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
851 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
853 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
854 struct ac_shader_config
*conf
= &variant
->config
;
856 VkShaderStatisticsInfoAMD statistics
= {};
857 statistics
.shaderStageMask
= shaderStage
;
858 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
859 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
860 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
862 if (stage
== MESA_SHADER_COMPUTE
) {
863 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
864 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
866 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
867 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
869 statistics
.computeWorkGroupSize
[0] = local_size
[0];
870 statistics
.computeWorkGroupSize
[1] = local_size
[1];
871 statistics
.computeWorkGroupSize
[2] = local_size
[2];
873 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
876 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
877 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
878 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
879 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
880 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
882 size_t size
= *pInfoSize
;
883 *pInfoSize
= sizeof(statistics
);
885 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
887 if (size
< *pInfoSize
)
888 result
= VK_INCOMPLETE
;
892 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
893 buf
= _mesa_string_buffer_create(NULL
, 1024);
895 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
896 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
897 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
898 generate_shader_stats(device
, variant
, stage
, buf
);
900 /* Need to include the null terminator. */
901 size_t length
= buf
->length
+ 1;
906 size_t size
= *pInfoSize
;
909 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
912 result
= VK_INCOMPLETE
;
915 _mesa_string_buffer_destroy(buf
);
918 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
919 result
= VK_ERROR_FEATURE_NOT_PRESENT
;