src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 #include "util/string_buffer.h"
  50
  51 static const struct nir_shader_compiler_options nir_options = {
  52         .vertex_id_zero_based = true,
  53         .lower_scmp = true,
  54         .lower_flrp32 = true,
  55         .lower_fsat = true,
  56         .lower_fdiv = true,
  57         .lower_sub = true,
  58         .lower_pack_snorm_2x16 = true,
  59         .lower_pack_snorm_4x8 = true,
  60         .lower_pack_unorm_2x16 = true,
  61         .lower_pack_unorm_4x8 = true,
  62         .lower_unpack_snorm_2x16 = true,
  63         .lower_unpack_snorm_4x8 = true,
  64         .lower_unpack_unorm_2x16 = true,
  65         .lower_unpack_unorm_4x8 = true,
  66         .lower_extract_byte = true,
  67         .lower_extract_word = true,
  68         .lower_ffma = true,
  69         .max_unroll_iterations = 32
  70 };
  71
  72 VkResult radv_CreateShaderModule(
  73         VkDevice                                    _device,
  74         const VkShaderModuleCreateInfo*             pCreateInfo,
  75         const VkAllocationCallbacks*                pAllocator,
  76         VkShaderModule*                             pShaderModule)
  77 {
  78         RADV_FROM_HANDLE(radv_device, device, _device);
  79         struct radv_shader_module *module;
  80
  81         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  82         assert(pCreateInfo->flags == 0);
  83
  84         module = vk_alloc2(&device->alloc, pAllocator,
  85                              sizeof(*module) + pCreateInfo->codeSize, 8,
  86                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  87         if (module == NULL)
  88                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  89
  90         module->nir = NULL;
  91         module->size = pCreateInfo->codeSize;
  92         memcpy(module->data, pCreateInfo->pCode, module->size);
  93
  94         _mesa_sha1_compute(module->data, module->size, module->sha1);
  95
  96         *pShaderModule = radv_shader_module_to_handle(module);
  97
  98         return VK_SUCCESS;
  99 }
 100
 101 void radv_DestroyShaderModule(
 102         VkDevice                                    _device,
 103         VkShaderModule                              _module,
 104         const VkAllocationCallbacks*                pAllocator)
 105 {
 106         RADV_FROM_HANDLE(radv_device, device, _device);
 107         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 108
 109         if (!module)
 110                 return;
 111
 112         vk_free2(&device->alloc, pAllocator, module);
 113 }
 114
 115 void
 116 radv_optimize_nir(struct nir_shader *shader)
 117 {
 118         bool progress;
 119
 120         do {
 121                 progress = false;
 122
 123                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 124                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 125                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 126                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 127
 128                 NIR_PASS(progress, shader, nir_copy_prop);
 129                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 130                 NIR_PASS(progress, shader, nir_opt_dce);
 131                 if (nir_opt_trivial_continues(shader)) {
 132                         progress = true;
 133                         NIR_PASS(progress, shader, nir_copy_prop);
 134                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 135                         NIR_PASS(progress, shader, nir_opt_dce);
 136                 }
 137                 NIR_PASS(progress, shader, nir_opt_if);
 138                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 139                 NIR_PASS(progress, shader, nir_opt_cse);
 140                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 141                 NIR_PASS(progress, shader, nir_opt_algebraic);
 142                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 143                 NIR_PASS(progress, shader, nir_opt_undef);
 144                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 145                 if (shader->options->max_unroll_iterations) {
 146                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 147                 }
 148         } while (progress);
 149 }
 150
 151 nir_shader *
 152 radv_shader_compile_to_nir(struct radv_device *device,
 153                            struct radv_shader_module *module,
 154                            const char *entrypoint_name,
 155                            gl_shader_stage stage,
 156                            const VkSpecializationInfo *spec_info)
 157 {
 158         if (strcmp(entrypoint_name, "main") != 0) {
 159                 radv_finishme("Multiple shaders per module not really supported");
 160         }
 161
 162         nir_shader *nir;
 163         nir_function *entry_point;
 164         if (module->nir) {
 165                 /* Some things such as our meta clear/blit code will give us a NIR
 166                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 167                  * and just use the NIR shader */
 168                 nir = module->nir;
 169                 nir->options = &nir_options;
 170                 nir_validate_shader(nir);
 171
 172                 assert(exec_list_length(&nir->functions) == 1);
 173                 struct exec_node *node = exec_list_get_head(&nir->functions);
 174                 entry_point = exec_node_data(nir_function, node, node);
 175         } else {
 176                 uint32_t *spirv = (uint32_t *) module->data;
 177                 assert(module->size % 4 == 0);
 178
 179                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 180                         radv_print_spirv(spirv, module->size, stderr);
 181
 182                 uint32_t num_spec_entries = 0;
 183                 struct nir_spirv_specialization *spec_entries = NULL;
 184                 if (spec_info && spec_info->mapEntryCount > 0) {
 185                         num_spec_entries = spec_info->mapEntryCount;
 186                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 187                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 188                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 189                                 const void *data = spec_info->pData + entry.offset;
 190                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 191
 192                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 193                                 if (spec_info->dataSize == 8)
 194                                         spec_entries[i].data64 = *(const uint64_t *)data;
 195                                 else
 196                                         spec_entries[i].data32 = *(const uint32_t *)data;
 197                         }
 198                 }
 199                 const struct spirv_to_nir_options spirv_options = {
 200                         .caps = {
 201                                 .draw_parameters = true,
 202                                 .float64 = true,
 203                                 .image_read_without_format = true,
 204                                 .image_write_without_format = true,
 205                                 .tessellation = true,
 206                                 .int64 = true,
 207                                 .multiview = true,
 208                                 .variable_pointers = true,
 209                         },
 210                 };
 211                 entry_point = spirv_to_nir(spirv, module->size / 4,
 212                                            spec_entries, num_spec_entries,
 213                                            stage, entrypoint_name,
 214                                            &spirv_options, &nir_options);
 215                 nir = entry_point->shader;
 216                 assert(nir->info.stage == stage);
 217                 nir_validate_shader(nir);
 218
 219                 free(spec_entries);
 220
 221                 /* We have to lower away local constant initializers right before we
 222                  * inline functions.  That way they get properly initialized at the top
 223                  * of the function and not at the top of its caller.
 224                  */
 225                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 226                 NIR_PASS_V(nir, nir_lower_returns);
 227                 NIR_PASS_V(nir, nir_inline_functions);
 228
 229                 /* Pick off the single entrypoint that we want */
 230                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 231                         if (func != entry_point)
 232                                 exec_node_remove(&func->node);
 233                 }
 234                 assert(exec_list_length(&nir->functions) == 1);
 235                 entry_point->name = ralloc_strdup(entry_point, "main");
 236
 237                 NIR_PASS_V(nir, nir_remove_dead_variables,
 238                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 239
 240                 /* Now that we've deleted all but the main function, we can go ahead and
 241                  * lower the rest of the constant initializers.
 242                  */
 243                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 244                 NIR_PASS_V(nir, nir_lower_system_values);
 245                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 246         }
 247
 248         /* Vulkan uses the separate-shader linking model */
 249         nir->info.separate_shader = true;
 250
 251         nir_shader_gather_info(nir, entry_point->impl);
 252
 253         /* While it would be nice not to have this flag, we are constrained
 254          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 255          * on GFX9.
 256          */
 257         bool llvm_has_working_vgpr_indexing =
 258                 device->physical_device->rad_info.chip_class <= VI;
 259
 260         /* TODO: Indirect indexing of GS inputs is unimplemented.
 261          *
 262          * TCS and TES load inputs directly from LDS or offchip memory, so
 263          * indirect indexing is trivial.
 264          */
 265         nir_variable_mode indirect_mask = 0;
 266         if (nir->info.stage == MESA_SHADER_GEOMETRY ||
 267             (nir->info.stage != MESA_SHADER_TESS_CTRL &&
 268              nir->info.stage != MESA_SHADER_TESS_EVAL &&
 269              !llvm_has_working_vgpr_indexing)) {
 270                 indirect_mask |= nir_var_shader_in;
 271         }
 272         if (!llvm_has_working_vgpr_indexing &&
 273             nir->info.stage != MESA_SHADER_TESS_CTRL)
 274                 indirect_mask |= nir_var_shader_out;
 275
 276         /* TODO: We shouldn't need to do this, however LLVM isn't currently
 277          * smart enough to handle indirects without causing excess spilling
 278          * causing the gpu to hang.
 279          *
 280          * See the following thread for more details of the problem:
 281          * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
 282          */
 283         indirect_mask |= nir_var_local;
 284
 285         nir_lower_indirect_derefs(nir, indirect_mask);
 286
 287         static const nir_lower_tex_options tex_options = {
 288           .lower_txp = ~0,
 289         };
 290
 291         nir_lower_tex(nir, &tex_options);
 292
 293         nir_lower_vars_to_ssa(nir);
 294         nir_lower_var_copies(nir);
 295         nir_lower_global_vars_to_local(nir);
 296         nir_remove_dead_variables(nir, nir_var_local);
 297         radv_optimize_nir(nir);
 298
 299         return nir;
 300 }
 301
 302 void *
 303 radv_alloc_shader_memory(struct radv_device *device,
 304                          struct radv_shader_variant *shader)
 305 {
 306         mtx_lock(&device->shader_slab_mutex);
 307         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 308                 uint64_t offset = 0;
 309                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 310                         if (s->bo_offset - offset >= shader->code_size) {
 311                                 shader->bo = slab->bo;
 312                                 shader->bo_offset = offset;
 313                                 list_addtail(&shader->slab_list, &s->slab_list);
 314                                 mtx_unlock(&device->shader_slab_mutex);
 315                                 return slab->ptr + offset;
 316                         }
 317                         offset = align_u64(s->bo_offset + s->code_size, 256);
 318                 }
 319                 if (slab->size - offset >= shader->code_size) {
 320                         shader->bo = slab->bo;
 321                         shader->bo_offset = offset;
 322                         list_addtail(&shader->slab_list, &slab->shaders);
 323                         mtx_unlock(&device->shader_slab_mutex);
 324                         return slab->ptr + offset;
 325                 }
 326         }
 327
 328         mtx_unlock(&device->shader_slab_mutex);
 329         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 330
 331         slab->size = 256 * 1024;
 332         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 333                                              RADEON_DOMAIN_VRAM,
 334                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 335                                              device->physical_device->cpdma_prefetch_writes_memory ?
 336                                                      0 : RADEON_FLAG_READ_ONLY);
 337         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 338         list_inithead(&slab->shaders);
 339
 340         mtx_lock(&device->shader_slab_mutex);
 341         list_add(&slab->slabs, &device->shader_slabs);
 342
 343         shader->bo = slab->bo;
 344         shader->bo_offset = 0;
 345         list_add(&shader->slab_list, &slab->shaders);
 346         mtx_unlock(&device->shader_slab_mutex);
 347         return slab->ptr;
 348 }
 349
 350 void
 351 radv_destroy_shader_slabs(struct radv_device *device)
 352 {
 353         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 354                 device->ws->buffer_destroy(slab->bo);
 355                 free(slab);
 356         }
 357         mtx_destroy(&device->shader_slab_mutex);
 358 }
 359
 360 static void
 361 radv_fill_shader_variant(struct radv_device *device,
 362                          struct radv_shader_variant *variant,
 363                          struct ac_shader_binary *binary,
 364                          gl_shader_stage stage)
 365 {
 366         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 367         unsigned vgpr_comp_cnt = 0;
 368
 369         if (scratch_enabled && !device->llvm_supports_spill)
 370                 radv_finishme("shader scratch support only available with LLVM 4.0");
 371
 372         variant->code_size = binary->code_size;
 373         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 374                         S_00B12C_SCRATCH_EN(scratch_enabled);
 375
 376         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 377                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 378                 S_00B848_DX10_CLAMP(1) |
 379                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 380
 381         switch (stage) {
 382         case MESA_SHADER_TESS_EVAL:
 383                 vgpr_comp_cnt = 3;
 384                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 385                 break;
 386         case MESA_SHADER_TESS_CTRL:
 387                 if (device->physical_device->rad_info.chip_class >= GFX9)
 388                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 389                 else
 390                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 391                 break;
 392         case MESA_SHADER_VERTEX:
 393         case MESA_SHADER_GEOMETRY:
 394                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 395                 break;
 396         case MESA_SHADER_FRAGMENT:
 397                 break;
 398         case MESA_SHADER_COMPUTE: {
 399                 struct ac_shader_info *info = &variant->info.info;
 400                 variant->rsrc2 |=
 401                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 402                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 403                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 404                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 405                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 406                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 407                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 408                 break;
 409         }
 410         default:
 411                 unreachable("unsupported shader type");
 412                 break;
 413         }
 414
 415         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 416             stage == MESA_SHADER_GEOMETRY) {
 417                 struct ac_shader_info *info = &variant->info.info;
 418                 unsigned es_type = variant->info.gs.es_type;
 419                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 420
 421                 if (es_type == MESA_SHADER_VERTEX) {
 422                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 423                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 424                         es_vgpr_comp_cnt = 3;
 425                 } else {
 426                         assert(!"invalid shader ES type");
 427                 }
 428
 429                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 430                  * VGPR[0:4] are always loaded.
 431                  */
 432                 if (info->uses_invocation_id)
 433                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 434                 else if (info->uses_prim_id)
 435                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 436                 else if (variant->info.gs.vertices_in >= 3)
 437                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 438                 else
 439                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 440
 441                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 442                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 443                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 444         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 445             stage == MESA_SHADER_TESS_CTRL)
 446                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 447         else
 448                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 449
 450         void *ptr = radv_alloc_shader_memory(device, variant);
 451         memcpy(ptr, binary->code, binary->code_size);
 452 }
 453
 454 static struct radv_shader_variant *
 455 shader_variant_create(struct radv_device *device,
 456                       struct radv_shader_module *module,
 457                       struct nir_shader * const *shaders,
 458                       int shader_count,
 459                       gl_shader_stage stage,
 460                       struct ac_nir_compiler_options *options,
 461                       bool gs_copy_shader,
 462                       void **code_out,
 463                       unsigned *code_size_out)
 464 {
 465         enum radeon_family chip_family = device->physical_device->rad_info.family;
 466         bool dump_shaders = radv_can_dump_shader(device, module);
 467         enum ac_target_machine_options tm_options = 0;
 468         struct radv_shader_variant *variant;
 469         struct ac_shader_binary binary;
 470         LLVMTargetMachineRef tm;
 471
 472         variant = calloc(1, sizeof(struct radv_shader_variant));
 473         if (!variant)
 474                 return NULL;
 475
 476         options->family = chip_family;
 477         options->chip_class = device->physical_device->rad_info.chip_class;
 478
 479         if (options->supports_spill)
 480                 tm_options |= AC_TM_SUPPORTS_SPILL;
 481         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 482                 tm_options |= AC_TM_SISCHED;
 483         tm = ac_create_target_machine(chip_family, tm_options);
 484
 485         if (gs_copy_shader) {
 486                 assert(shader_count == 1);
 487                 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
 488                                          &variant->info, options, dump_shaders);
 489         } else {
 490                 ac_compile_nir_shader(tm, &binary, &variant->config,
 491                                       &variant->info, shaders, shader_count, options,
 492                                       dump_shaders);
 493         }
 494
 495         LLVMDisposeTargetMachine(tm);
 496
 497         radv_fill_shader_variant(device, variant, &binary, stage);
 498
 499         if (code_out) {
 500                 *code_out = binary.code;
 501                 *code_size_out = binary.code_size;
 502         } else
 503                 free(binary.code);
 504         free(binary.config);
 505         free(binary.rodata);
 506         free(binary.global_symbol_offsets);
 507         free(binary.relocs);
 508         variant->ref_count = 1;
 509
 510         if (device->keep_shader_info) {
 511                 variant->disasm_string = binary.disasm_string;
 512                 if (!gs_copy_shader && !module->nir) {
 513                         variant->nir = *shaders;
 514                         variant->spirv = (uint32_t *)module->data;
 515                         variant->spirv_size = module->size;
 516                 }
 517         } else {
 518                 free(binary.disasm_string);
 519         }
 520
 521         return variant;
 522 }
 523
 524 struct radv_shader_variant *
 525 radv_shader_variant_create(struct radv_device *device,
 526                            struct radv_shader_module *module,
 527                            struct nir_shader *const *shaders,
 528                            int shader_count,
 529                            struct radv_pipeline_layout *layout,
 530                            const struct ac_shader_variant_key *key,
 531                            void **code_out,
 532                            unsigned *code_size_out)
 533 {
 534         struct ac_nir_compiler_options options = {0};
 535
 536         options.layout = layout;
 537         if (key)
 538                 options.key = *key;
 539
 540         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 541         options.supports_spill = device->llvm_supports_spill;
 542
 543         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 544                                      &options, false, code_out, code_size_out);
 545 }
 546
 547 struct radv_shader_variant *
 548 radv_create_gs_copy_shader(struct radv_device *device,
 549                            struct nir_shader *shader,
 550                            void **code_out,
 551                            unsigned *code_size_out,
 552                            bool multiview)
 553 {
 554         struct ac_nir_compiler_options options = {0};
 555
 556         options.key.has_multiview_view_index = multiview;
 557
 558         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 559                                      &options, true, code_out, code_size_out);
 560 }
 561
 562 void
 563 radv_shader_variant_destroy(struct radv_device *device,
 564                             struct radv_shader_variant *variant)
 565 {
 566         if (!p_atomic_dec_zero(&variant->ref_count))
 567                 return;
 568
 569         mtx_lock(&device->shader_slab_mutex);
 570         list_del(&variant->slab_list);
 571         mtx_unlock(&device->shader_slab_mutex);
 572
 573         ralloc_free(variant->nir);
 574         free(variant->disasm_string);
 575         free(variant);
 576 }
 577
 578 const char *
 579 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 580 {
 581         switch (stage) {
 582         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 583         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 584         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 585         case MESA_SHADER_COMPUTE: return "Compute Shader";
 586         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 587         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 588         default:
 589                 return "Unknown shader";
 590         };
 591 }
 592
 593 static uint32_t
 594 get_total_sgprs(struct radv_device *device)
 595 {
 596         if (device->physical_device->rad_info.chip_class >= VI)
 597                 return 800;
 598         else
 599                 return 512;
 600 }
 601
 602 static void
 603 generate_shader_stats(struct radv_device *device,
 604                       struct radv_shader_variant *variant,
 605                       gl_shader_stage stage,
 606                       struct _mesa_string_buffer *buf)
 607 {
 608         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 609         struct ac_shader_config *conf;
 610         unsigned max_simd_waves;
 611         unsigned lds_per_wave = 0;
 612
 613         switch (device->physical_device->rad_info.family) {
 614         /* These always have 8 waves: */
 615         case CHIP_POLARIS10:
 616         case CHIP_POLARIS11:
 617         case CHIP_POLARIS12:
 618                 max_simd_waves = 8;
 619                 break;
 620         default:
 621                 max_simd_waves = 10;
 622         }
 623
 624         conf = &variant->config;
 625
 626         if (stage == MESA_SHADER_FRAGMENT) {
 627                 lds_per_wave = conf->lds_size * lds_increment +
 628                                align(variant->info.fs.num_interp * 48,
 629                                      lds_increment);
 630         }
 631
 632         if (conf->num_sgprs)
 633                 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
 634
 635         if (conf->num_vgprs)
 636                 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 637
 638         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 639          * that PS can use.
 640          */
 641         if (lds_per_wave)
 642                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 643
 644         if (stage == MESA_SHADER_FRAGMENT) {
 645                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 646                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 647                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 648                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 649         }
 650
 651         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 652                                    "SGPRS: %d\n"
 653                                    "VGPRS: %d\n"
 654                                    "Spilled SGPRs: %d\n"
 655                                    "Spilled VGPRs: %d\n"
 656                                    "Code Size: %d bytes\n"
 657                                    "LDS: %d blocks\n"
 658                                    "Scratch: %d bytes per wave\n"
 659                                    "Max Waves: %d\n"
 660                                    "********************\n\n\n",
 661                                    conf->num_sgprs, conf->num_vgprs,
 662                                    conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
 663                                    conf->lds_size, conf->scratch_bytes_per_wave,
 664                                    max_simd_waves);
 665 }
 666
 667 void
 668 radv_shader_dump_stats(struct radv_device *device,
 669                        struct radv_shader_variant *variant,
 670                        gl_shader_stage stage,
 671                        FILE *file)
 672 {
 673         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 674
 675         generate_shader_stats(device, variant, stage, buf);
 676
 677         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 678         fprintf(file, "%s", buf->buf);
 679
 680         _mesa_string_buffer_destroy(buf);
 681 }
 682
 683 VkResult
 684 radv_GetShaderInfoAMD(VkDevice _device,
 685                       VkPipeline _pipeline,
 686                       VkShaderStageFlagBits shaderStage,
 687                       VkShaderInfoTypeAMD infoType,
 688                       size_t* pInfoSize,
 689                       void* pInfo)
 690 {
 691         RADV_FROM_HANDLE(radv_device, device, _device);
 692         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 693         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 694         struct radv_shader_variant *variant = pipeline->shaders[stage];
 695         struct _mesa_string_buffer *buf;
 696         VkResult result = VK_SUCCESS;
 697
 698         /* Spec doesn't indicate what to do if the stage is invalid, so just
 699          * return no info for this. */
 700         if (!variant)
 701                 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
 702
 703         switch (infoType) {
 704         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 705                 if (!pInfo) {
 706                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 707                 } else {
 708                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 709                         struct ac_shader_config *conf = &variant->config;
 710
 711                         VkShaderStatisticsInfoAMD statistics = {};
 712                         statistics.shaderStageMask = shaderStage;
 713                         statistics.numPhysicalVgprs = 256;
 714                         statistics.numPhysicalSgprs = get_total_sgprs(device);
 715                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 716
 717                         if (stage == MESA_SHADER_COMPUTE) {
 718                                 unsigned *local_size = variant->nir->info.cs.local_size;
 719                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 720
 721                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 722                                                                ceil(workgroup_size / statistics.numPhysicalVgprs);
 723
 724                                 statistics.computeWorkGroupSize[0] = local_size[0];
 725                                 statistics.computeWorkGroupSize[1] = local_size[1];
 726                                 statistics.computeWorkGroupSize[2] = local_size[2];
 727                         } else {
 728                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 729                         }
 730
 731                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 732                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 733                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 734                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 735                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 736
 737                         size_t size = *pInfoSize;
 738                         *pInfoSize = sizeof(statistics);
 739
 740                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 741
 742                         if (size < *pInfoSize)
 743                                 result = VK_INCOMPLETE;
 744                 }
 745
 746                 break;
 747         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 748                 buf = _mesa_string_buffer_create(NULL, 1024);
 749
 750                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 751                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 752                 generate_shader_stats(device, variant, stage, buf);
 753
 754                 /* Need to include the null terminator. */
 755                 size_t length = buf->length + 1;
 756
 757                 if (!pInfo) {
 758                         *pInfoSize = length;
 759                 } else {
 760                         size_t size = *pInfoSize;
 761                         *pInfoSize = length;
 762
 763                         memcpy(pInfo, buf->buf, MIN2(size, length));
 764
 765                         if (size < length)
 766                                 result = VK_INCOMPLETE;
 767                 }
 768
 769                 _mesa_string_buffer_destroy(buf);
 770                 break;
 771         default:
 772                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 773                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 774                 break;
 775         }
 776
 777         return result;
 778 }