src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "r600d_common.h"
  43 #include "ac_binary.h"
  44 #include "ac_llvm_util.h"
  45 #include "ac_nir_to_llvm.h"
  46 #include "vk_format.h"
  47 #include "util/debug.h"
  48 #include "ac_exp_param.h"
  49
  50 static const struct nir_shader_compiler_options nir_options = {
  51         .vertex_id_zero_based = true,
  52         .lower_scmp = true,
  53         .lower_flrp32 = true,
  54         .lower_fsat = true,
  55         .lower_fdiv = true,
  56         .lower_sub = true,
  57         .lower_pack_snorm_2x16 = true,
  58         .lower_pack_snorm_4x8 = true,
  59         .lower_pack_unorm_2x16 = true,
  60         .lower_pack_unorm_4x8 = true,
  61         .lower_unpack_snorm_2x16 = true,
  62         .lower_unpack_snorm_4x8 = true,
  63         .lower_unpack_unorm_2x16 = true,
  64         .lower_unpack_unorm_4x8 = true,
  65         .lower_extract_byte = true,
  66         .lower_extract_word = true,
  67         .max_unroll_iterations = 32
  68 };
  69
  70 VkResult radv_CreateShaderModule(
  71         VkDevice                                    _device,
  72         const VkShaderModuleCreateInfo*             pCreateInfo,
  73         const VkAllocationCallbacks*                pAllocator,
  74         VkShaderModule*                             pShaderModule)
  75 {
  76         RADV_FROM_HANDLE(radv_device, device, _device);
  77         struct radv_shader_module *module;
  78
  79         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  80         assert(pCreateInfo->flags == 0);
  81
  82         module = vk_alloc2(&device->alloc, pAllocator,
  83                              sizeof(*module) + pCreateInfo->codeSize, 8,
  84                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  85         if (module == NULL)
  86                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  87
  88         module->nir = NULL;
  89         module->size = pCreateInfo->codeSize;
  90         memcpy(module->data, pCreateInfo->pCode, module->size);
  91
  92         _mesa_sha1_compute(module->data, module->size, module->sha1);
  93
  94         *pShaderModule = radv_shader_module_to_handle(module);
  95
  96         return VK_SUCCESS;
  97 }
  98
  99 void radv_DestroyShaderModule(
 100         VkDevice                                    _device,
 101         VkShaderModule                              _module,
 102         const VkAllocationCallbacks*                pAllocator)
 103 {
 104         RADV_FROM_HANDLE(radv_device, device, _device);
 105         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 106
 107         if (!module)
 108                 return;
 109
 110         vk_free2(&device->alloc, pAllocator, module);
 111 }
 112
 113 static void
 114 radv_optimize_nir(struct nir_shader *shader)
 115 {
 116         bool progress;
 117
 118         do {
 119                 progress = false;
 120
 121                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 122                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 123                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 124                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 125
 126                 NIR_PASS(progress, shader, nir_copy_prop);
 127                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 128                 NIR_PASS(progress, shader, nir_opt_dce);
 129                 if (nir_opt_trivial_continues(shader)) {
 130                         progress = true;
 131                         NIR_PASS(progress, shader, nir_copy_prop);
 132                         NIR_PASS(progress, shader, nir_opt_dce);
 133                 }
 134                 NIR_PASS(progress, shader, nir_opt_if);
 135                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 136                 NIR_PASS(progress, shader, nir_opt_cse);
 137                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 138                 NIR_PASS(progress, shader, nir_opt_algebraic);
 139                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 140                 NIR_PASS(progress, shader, nir_opt_undef);
 141                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 142                 if (shader->options->max_unroll_iterations) {
 143                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 144                 }
 145         } while (progress);
 146 }
 147
 148 nir_shader *
 149 radv_shader_compile_to_nir(struct radv_device *device,
 150                            struct radv_shader_module *module,
 151                            const char *entrypoint_name,
 152                            gl_shader_stage stage,
 153                            const VkSpecializationInfo *spec_info,
 154                            bool dump)
 155 {
 156         if (strcmp(entrypoint_name, "main") != 0) {
 157                 radv_finishme("Multiple shaders per module not really supported");
 158         }
 159
 160         nir_shader *nir;
 161         nir_function *entry_point;
 162         if (module->nir) {
 163                 /* Some things such as our meta clear/blit code will give us a NIR
 164                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 165                  * and just use the NIR shader */
 166                 nir = module->nir;
 167                 nir->options = &nir_options;
 168                 nir_validate_shader(nir);
 169
 170                 assert(exec_list_length(&nir->functions) == 1);
 171                 struct exec_node *node = exec_list_get_head(&nir->functions);
 172                 entry_point = exec_node_data(nir_function, node, node);
 173         } else {
 174                 uint32_t *spirv = (uint32_t *) module->data;
 175                 assert(module->size % 4 == 0);
 176
 177                 if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 178                         radv_print_spirv(module, stderr);
 179
 180                 uint32_t num_spec_entries = 0;
 181                 struct nir_spirv_specialization *spec_entries = NULL;
 182                 if (spec_info && spec_info->mapEntryCount > 0) {
 183                         num_spec_entries = spec_info->mapEntryCount;
 184                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 185                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 186                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 187                                 const void *data = spec_info->pData + entry.offset;
 188                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 189
 190                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 191                                 if (spec_info->dataSize == 8)
 192                                         spec_entries[i].data64 = *(const uint64_t *)data;
 193                                 else
 194                                         spec_entries[i].data32 = *(const uint32_t *)data;
 195                         }
 196                 }
 197                 const struct nir_spirv_supported_extensions supported_ext = {
 198                         .draw_parameters = true,
 199                         .float64 = true,
 200                         .image_read_without_format = true,
 201                         .image_write_without_format = true,
 202                         .tessellation = true,
 203                         .int64 = true,
 204                         .multiview = true,
 205                         .variable_pointers = true,
 206                 };
 207                 entry_point = spirv_to_nir(spirv, module->size / 4,
 208                                            spec_entries, num_spec_entries,
 209                                            stage, entrypoint_name, &supported_ext, &nir_options);
 210                 nir = entry_point->shader;
 211                 assert(nir->stage == stage);
 212                 nir_validate_shader(nir);
 213
 214                 free(spec_entries);
 215
 216                 /* We have to lower away local constant initializers right before we
 217                  * inline functions.  That way they get properly initialized at the top
 218                  * of the function and not at the top of its caller.
 219                  */
 220                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 221                 NIR_PASS_V(nir, nir_lower_returns);
 222                 NIR_PASS_V(nir, nir_inline_functions);
 223
 224                 /* Pick off the single entrypoint that we want */
 225                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 226                         if (func != entry_point)
 227                                 exec_node_remove(&func->node);
 228                 }
 229                 assert(exec_list_length(&nir->functions) == 1);
 230                 entry_point->name = ralloc_strdup(entry_point, "main");
 231
 232                 NIR_PASS_V(nir, nir_remove_dead_variables,
 233                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 234
 235                 /* Now that we've deleted all but the main function, we can go ahead and
 236                  * lower the rest of the constant initializers.
 237                  */
 238                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 239                 NIR_PASS_V(nir, nir_lower_system_values);
 240                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 241         }
 242
 243         /* Vulkan uses the separate-shader linking model */
 244         nir->info.separate_shader = true;
 245
 246         nir_shader_gather_info(nir, entry_point->impl);
 247
 248         nir_variable_mode indirect_mask = 0;
 249         indirect_mask |= nir_var_shader_in;
 250         indirect_mask |= nir_var_local;
 251
 252         nir_lower_indirect_derefs(nir, indirect_mask);
 253
 254         static const nir_lower_tex_options tex_options = {
 255           .lower_txp = ~0,
 256         };
 257
 258         nir_lower_tex(nir, &tex_options);
 259
 260         nir_lower_vars_to_ssa(nir);
 261         nir_lower_var_copies(nir);
 262         nir_lower_global_vars_to_local(nir);
 263         nir_remove_dead_variables(nir, nir_var_local);
 264         radv_optimize_nir(nir);
 265
 266         if (dump)
 267                 nir_print_shader(nir, stderr);
 268
 269         return nir;
 270 }
 271
 272 void *
 273 radv_alloc_shader_memory(struct radv_device *device,
 274                          struct radv_shader_variant *shader)
 275 {
 276         mtx_lock(&device->shader_slab_mutex);
 277         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 278                 uint64_t offset = 0;
 279                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 280                         if (s->bo_offset - offset >= shader->code_size) {
 281                                 shader->bo = slab->bo;
 282                                 shader->bo_offset = offset;
 283                                 list_addtail(&shader->slab_list, &s->slab_list);
 284                                 mtx_unlock(&device->shader_slab_mutex);
 285                                 return slab->ptr + offset;
 286                         }
 287                         offset = align_u64(s->bo_offset + s->code_size, 256);
 288                 }
 289                 if (slab->size - offset >= shader->code_size) {
 290                         shader->bo = slab->bo;
 291                         shader->bo_offset = offset;
 292                         list_addtail(&shader->slab_list, &slab->shaders);
 293                         mtx_unlock(&device->shader_slab_mutex);
 294                         return slab->ptr + offset;
 295                 }
 296         }
 297
 298         mtx_unlock(&device->shader_slab_mutex);
 299         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 300
 301         slab->size = 256 * 1024;
 302         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 303                                              RADEON_DOMAIN_VRAM, 0);
 304         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 305         list_inithead(&slab->shaders);
 306
 307         mtx_lock(&device->shader_slab_mutex);
 308         list_add(&slab->slabs, &device->shader_slabs);
 309
 310         shader->bo = slab->bo;
 311         shader->bo_offset = 0;
 312         list_add(&shader->slab_list, &slab->shaders);
 313         mtx_unlock(&device->shader_slab_mutex);
 314         return slab->ptr;
 315 }
 316
 317 void
 318 radv_destroy_shader_slabs(struct radv_device *device)
 319 {
 320         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 321                 device->ws->buffer_destroy(slab->bo);
 322                 free(slab);
 323         }
 324         mtx_destroy(&device->shader_slab_mutex);
 325 }
 326
 327 static void
 328 radv_fill_shader_variant(struct radv_device *device,
 329                          struct radv_shader_variant *variant,
 330                          struct ac_shader_binary *binary,
 331                          gl_shader_stage stage)
 332 {
 333         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 334         unsigned vgpr_comp_cnt = 0;
 335
 336         if (scratch_enabled && !device->llvm_supports_spill)
 337                 radv_finishme("shader scratch support only available with LLVM 4.0");
 338
 339         variant->code_size = binary->code_size;
 340         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 341                         S_00B12C_SCRATCH_EN(scratch_enabled);
 342
 343         switch (stage) {
 344         case MESA_SHADER_TESS_EVAL:
 345                 vgpr_comp_cnt = 3;
 346                 /* fallthrough */
 347         case MESA_SHADER_TESS_CTRL:
 348                 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
 349                 break;
 350         case MESA_SHADER_VERTEX:
 351         case MESA_SHADER_GEOMETRY:
 352                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 353                 break;
 354         case MESA_SHADER_FRAGMENT:
 355                 break;
 356         case MESA_SHADER_COMPUTE:
 357                 variant->rsrc2 |=
 358                         S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 359                         S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 360                         S_00B84C_TG_SIZE_EN(1) |
 361                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 362                 break;
 363         default:
 364                 unreachable("unsupported shader type");
 365                 break;
 366         }
 367
 368         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 369                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 370                 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
 371                 S_00B848_DX10_CLAMP(1) |
 372                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 373
 374         void *ptr = radv_alloc_shader_memory(device, variant);
 375         memcpy(ptr, binary->code, binary->code_size);
 376 }
 377
 378 struct radv_shader_variant *
 379 radv_shader_variant_create(struct radv_device *device,
 380                            struct nir_shader *shader,
 381                            struct radv_pipeline_layout *layout,
 382                            const struct ac_shader_variant_key *key,
 383                            void **code_out,
 384                            unsigned *code_size_out,
 385                            bool dump)
 386 {
 387         struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
 388         enum radeon_family chip_family = device->physical_device->rad_info.family;
 389         LLVMTargetMachineRef tm;
 390         if (!variant)
 391                 return NULL;
 392
 393         struct ac_nir_compiler_options options = {0};
 394         options.layout = layout;
 395         if (key)
 396                 options.key = *key;
 397
 398         struct ac_shader_binary binary;
 399         enum ac_target_machine_options tm_options = 0;
 400         options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 401         options.family = chip_family;
 402         options.chip_class = device->physical_device->rad_info.chip_class;
 403         options.supports_spill = device->llvm_supports_spill;
 404         if (options.supports_spill)
 405                 tm_options |= AC_TM_SUPPORTS_SPILL;
 406         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 407                 tm_options |= AC_TM_SISCHED;
 408         tm = ac_create_target_machine(chip_family, tm_options);
 409         ac_compile_nir_shader(tm, &binary, &variant->config,
 410                               &variant->info, shader, &options, dump);
 411         LLVMDisposeTargetMachine(tm);
 412
 413         radv_fill_shader_variant(device, variant, &binary, shader->stage);
 414
 415         if (code_out) {
 416                 *code_out = binary.code;
 417                 *code_size_out = binary.code_size;
 418         } else
 419                 free(binary.code);
 420         free(binary.config);
 421         free(binary.rodata);
 422         free(binary.global_symbol_offsets);
 423         free(binary.relocs);
 424         free(binary.disasm_string);
 425         variant->ref_count = 1;
 426         return variant;
 427 }
 428
 429 struct radv_shader_variant *
 430 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 431                            void **code_out, unsigned *code_size_out,
 432                            bool dump_shader, bool multiview)
 433 {
 434         struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
 435         enum radeon_family chip_family = device->physical_device->rad_info.family;
 436         LLVMTargetMachineRef tm;
 437         if (!variant)
 438                 return NULL;
 439
 440         struct ac_nir_compiler_options options = {0};
 441         struct ac_shader_binary binary;
 442         enum ac_target_machine_options tm_options = 0;
 443         options.family = chip_family;
 444         options.chip_class = device->physical_device->rad_info.chip_class;
 445         options.key.has_multiview_view_index = multiview;
 446         if (options.supports_spill)
 447                 tm_options |= AC_TM_SUPPORTS_SPILL;
 448         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 449                 tm_options |= AC_TM_SISCHED;
 450         tm = ac_create_target_machine(chip_family, tm_options);
 451         ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
 452         LLVMDisposeTargetMachine(tm);
 453
 454         radv_fill_shader_variant(device, variant, &binary, MESA_SHADER_VERTEX);
 455
 456         if (code_out) {
 457                 *code_out = binary.code;
 458                 *code_size_out = binary.code_size;
 459         } else
 460                 free(binary.code);
 461         free(binary.config);
 462         free(binary.rodata);
 463         free(binary.global_symbol_offsets);
 464         free(binary.relocs);
 465         free(binary.disasm_string);
 466         variant->ref_count = 1;
 467         return variant;
 468 }
 469
 470 void
 471 radv_shader_variant_destroy(struct radv_device *device,
 472                             struct radv_shader_variant *variant)
 473 {
 474         if (!p_atomic_dec_zero(&variant->ref_count))
 475                 return;
 476
 477         mtx_lock(&device->shader_slab_mutex);
 478         list_del(&variant->slab_list);
 479         mtx_unlock(&device->shader_slab_mutex);
 480
 481         free(variant);
 482 }
 483
 484 uint32_t
 485 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs,
 486                                  bool has_tess)
 487 {
 488         switch (stage) {
 489         case MESA_SHADER_FRAGMENT:
 490                 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
 491         case MESA_SHADER_VERTEX:
 492                 if (has_tess)
 493                         return R_00B530_SPI_SHADER_USER_DATA_LS_0;
 494                 else
 495                         return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
 496         case MESA_SHADER_GEOMETRY:
 497                 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
 498         case MESA_SHADER_COMPUTE:
 499                 return R_00B900_COMPUTE_USER_DATA_0;
 500         case MESA_SHADER_TESS_CTRL:
 501                 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
 502         case MESA_SHADER_TESS_EVAL:
 503                 if (has_gs)
 504                         return R_00B330_SPI_SHADER_USER_DATA_ES_0;
 505                 else
 506                         return R_00B130_SPI_SHADER_USER_DATA_VS_0;
 507         default:
 508                 unreachable("unknown shader");
 509         }
 510 }
 511
 512 const char *
 513 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 514 {
 515         switch (stage) {
 516         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 517         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 518         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 519         case MESA_SHADER_COMPUTE: return "Compute Shader";
 520         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 521         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 522         default:
 523                 return "Unknown shader";
 524         };
 525 }
 526