2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
49 #include "util/string_buffer.h"
51 static const struct nir_shader_compiler_options nir_options
= {
52 .vertex_id_zero_based
= true,
56 .lower_device_index_to_zero
= true,
60 .lower_pack_snorm_2x16
= true,
61 .lower_pack_snorm_4x8
= true,
62 .lower_pack_unorm_2x16
= true,
63 .lower_pack_unorm_4x8
= true,
64 .lower_unpack_snorm_2x16
= true,
65 .lower_unpack_snorm_4x8
= true,
66 .lower_unpack_unorm_2x16
= true,
67 .lower_unpack_unorm_4x8
= true,
68 .lower_extract_byte
= true,
69 .lower_extract_word
= true,
72 .vs_inputs_dual_locations
= true,
73 .max_unroll_iterations
= 32
76 VkResult
radv_CreateShaderModule(
78 const VkShaderModuleCreateInfo
* pCreateInfo
,
79 const VkAllocationCallbacks
* pAllocator
,
80 VkShaderModule
* pShaderModule
)
82 RADV_FROM_HANDLE(radv_device
, device
, _device
);
83 struct radv_shader_module
*module
;
85 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
86 assert(pCreateInfo
->flags
== 0);
88 module
= vk_alloc2(&device
->alloc
, pAllocator
,
89 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
90 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
92 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
95 module
->size
= pCreateInfo
->codeSize
;
96 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
98 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
100 *pShaderModule
= radv_shader_module_to_handle(module
);
105 void radv_DestroyShaderModule(
107 VkShaderModule _module
,
108 const VkAllocationCallbacks
* pAllocator
)
110 RADV_FROM_HANDLE(radv_device
, device
, _device
);
111 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
116 vk_free2(&device
->alloc
, pAllocator
, module
);
120 radv_optimize_nir(struct nir_shader
*shader
)
127 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
128 NIR_PASS_V(shader
, nir_lower_64bit_pack
);
129 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
130 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
132 NIR_PASS(progress
, shader
, nir_copy_prop
);
133 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
134 NIR_PASS(progress
, shader
, nir_opt_dce
);
135 if (nir_opt_trivial_continues(shader
)) {
137 NIR_PASS(progress
, shader
, nir_copy_prop
);
138 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
139 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_if
);
142 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
143 NIR_PASS(progress
, shader
, nir_opt_cse
);
144 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
145 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
146 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
147 NIR_PASS(progress
, shader
, nir_opt_undef
);
148 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
149 if (shader
->options
->max_unroll_iterations
) {
150 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
154 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
155 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
159 radv_shader_compile_to_nir(struct radv_device
*device
,
160 struct radv_shader_module
*module
,
161 const char *entrypoint_name
,
162 gl_shader_stage stage
,
163 const VkSpecializationInfo
*spec_info
)
165 if (strcmp(entrypoint_name
, "main") != 0) {
166 radv_finishme("Multiple shaders per module not really supported");
170 nir_function
*entry_point
;
172 /* Some things such as our meta clear/blit code will give us a NIR
173 * shader directly. In that case, we just ignore the SPIR-V entirely
174 * and just use the NIR shader */
176 nir
->options
= &nir_options
;
177 nir_validate_shader(nir
);
179 assert(exec_list_length(&nir
->functions
) == 1);
180 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
181 entry_point
= exec_node_data(nir_function
, node
, node
);
183 uint32_t *spirv
= (uint32_t *) module
->data
;
184 assert(module
->size
% 4 == 0);
186 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
187 radv_print_spirv(spirv
, module
->size
, stderr
);
189 uint32_t num_spec_entries
= 0;
190 struct nir_spirv_specialization
*spec_entries
= NULL
;
191 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
192 num_spec_entries
= spec_info
->mapEntryCount
;
193 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
194 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
195 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
196 const void *data
= spec_info
->pData
+ entry
.offset
;
197 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
199 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
200 if (spec_info
->dataSize
== 8)
201 spec_entries
[i
].data64
= *(const uint64_t *)data
;
203 spec_entries
[i
].data32
= *(const uint32_t *)data
;
206 const struct spirv_to_nir_options spirv_options
= {
208 .device_group
= true,
209 .draw_parameters
= true,
211 .image_read_without_format
= true,
212 .image_write_without_format
= true,
213 .tessellation
= true,
216 .subgroup_basic
= true,
217 .variable_pointers
= true,
221 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
222 spec_entries
, num_spec_entries
,
223 stage
, entrypoint_name
,
224 &spirv_options
, &nir_options
);
225 nir
= entry_point
->shader
;
226 assert(nir
->info
.stage
== stage
);
227 nir_validate_shader(nir
);
231 /* We have to lower away local constant initializers right before we
232 * inline functions. That way they get properly initialized at the top
233 * of the function and not at the top of its caller.
235 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
236 NIR_PASS_V(nir
, nir_lower_returns
);
237 NIR_PASS_V(nir
, nir_inline_functions
);
239 /* Pick off the single entrypoint that we want */
240 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
241 if (func
!= entry_point
)
242 exec_node_remove(&func
->node
);
244 assert(exec_list_length(&nir
->functions
) == 1);
245 entry_point
->name
= ralloc_strdup(entry_point
, "main");
247 /* Make sure we lower constant initializers on output variables so that
248 * nir_remove_dead_variables below sees the corresponding stores
250 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
252 NIR_PASS_V(nir
, nir_remove_dead_variables
,
253 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
255 /* Now that we've deleted all but the main function, we can go ahead and
256 * lower the rest of the constant initializers.
258 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
259 NIR_PASS_V(nir
, nir_lower_system_values
);
260 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
263 /* Vulkan uses the separate-shader linking model */
264 nir
->info
.separate_shader
= true;
266 nir_shader_gather_info(nir
, entry_point
->impl
);
268 static const nir_lower_tex_options tex_options
= {
272 nir_lower_tex(nir
, &tex_options
);
274 nir_lower_vars_to_ssa(nir
);
275 nir_lower_var_copies(nir
);
276 nir_lower_global_vars_to_local(nir
);
277 nir_remove_dead_variables(nir
, nir_var_local
);
278 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
279 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
281 .ballot_bit_size
= 64,
282 .lower_to_scalar
= 1,
283 .lower_subgroup_masks
= 1,
288 radv_optimize_nir(nir
);
294 radv_alloc_shader_memory(struct radv_device
*device
,
295 struct radv_shader_variant
*shader
)
297 mtx_lock(&device
->shader_slab_mutex
);
298 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
300 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
301 if (s
->bo_offset
- offset
>= shader
->code_size
) {
302 shader
->bo
= slab
->bo
;
303 shader
->bo_offset
= offset
;
304 list_addtail(&shader
->slab_list
, &s
->slab_list
);
305 mtx_unlock(&device
->shader_slab_mutex
);
306 return slab
->ptr
+ offset
;
308 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
310 if (slab
->size
- offset
>= shader
->code_size
) {
311 shader
->bo
= slab
->bo
;
312 shader
->bo_offset
= offset
;
313 list_addtail(&shader
->slab_list
, &slab
->shaders
);
314 mtx_unlock(&device
->shader_slab_mutex
);
315 return slab
->ptr
+ offset
;
319 mtx_unlock(&device
->shader_slab_mutex
);
320 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
322 slab
->size
= 256 * 1024;
323 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
325 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
326 device
->physical_device
->cpdma_prefetch_writes_memory
?
327 0 : RADEON_FLAG_READ_ONLY
);
328 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
329 list_inithead(&slab
->shaders
);
331 mtx_lock(&device
->shader_slab_mutex
);
332 list_add(&slab
->slabs
, &device
->shader_slabs
);
334 shader
->bo
= slab
->bo
;
335 shader
->bo_offset
= 0;
336 list_add(&shader
->slab_list
, &slab
->shaders
);
337 mtx_unlock(&device
->shader_slab_mutex
);
342 radv_destroy_shader_slabs(struct radv_device
*device
)
344 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
345 device
->ws
->buffer_destroy(slab
->bo
);
348 mtx_destroy(&device
->shader_slab_mutex
);
352 radv_fill_shader_variant(struct radv_device
*device
,
353 struct radv_shader_variant
*variant
,
354 struct ac_shader_binary
*binary
,
355 gl_shader_stage stage
)
357 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
358 unsigned vgpr_comp_cnt
= 0;
360 if (scratch_enabled
&& !device
->llvm_supports_spill
)
361 radv_finishme("shader scratch support only available with LLVM 4.0");
363 variant
->code_size
= binary
->code_size
;
364 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
365 S_00B12C_SCRATCH_EN(scratch_enabled
);
367 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
368 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
369 S_00B848_DX10_CLAMP(1) |
370 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
373 case MESA_SHADER_TESS_EVAL
:
375 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
377 case MESA_SHADER_TESS_CTRL
:
378 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
379 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
381 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
383 case MESA_SHADER_VERTEX
:
384 case MESA_SHADER_GEOMETRY
:
385 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
387 case MESA_SHADER_FRAGMENT
:
389 case MESA_SHADER_COMPUTE
: {
390 struct radv_shader_info
*info
= &variant
->info
.info
;
392 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
393 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
394 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
395 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
396 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
397 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
398 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
402 unreachable("unsupported shader type");
406 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
407 stage
== MESA_SHADER_GEOMETRY
) {
408 struct radv_shader_info
*info
= &variant
->info
.info
;
409 unsigned es_type
= variant
->info
.gs
.es_type
;
410 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
412 if (es_type
== MESA_SHADER_VERTEX
) {
413 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
414 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
415 es_vgpr_comp_cnt
= 3;
417 unreachable("invalid shader ES type");
420 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
421 * VGPR[0:4] are always loaded.
423 if (info
->uses_invocation_id
)
424 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
425 else if (info
->uses_prim_id
)
426 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
427 else if (variant
->info
.gs
.vertices_in
>= 3)
428 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
430 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
432 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
433 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
434 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
435 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
436 stage
== MESA_SHADER_TESS_CTRL
)
437 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
439 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
441 void *ptr
= radv_alloc_shader_memory(device
, variant
);
442 memcpy(ptr
, binary
->code
, binary
->code_size
);
445 static struct radv_shader_variant
*
446 shader_variant_create(struct radv_device
*device
,
447 struct radv_shader_module
*module
,
448 struct nir_shader
* const *shaders
,
450 gl_shader_stage stage
,
451 struct radv_nir_compiler_options
*options
,
454 unsigned *code_size_out
)
456 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
457 enum ac_target_machine_options tm_options
= 0;
458 struct radv_shader_variant
*variant
;
459 struct ac_shader_binary binary
;
460 LLVMTargetMachineRef tm
;
462 variant
= calloc(1, sizeof(struct radv_shader_variant
));
466 options
->family
= chip_family
;
467 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
468 options
->dump_shader
= radv_can_dump_shader(device
, module
);
469 options
->dump_preoptir
= options
->dump_shader
&&
470 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
471 options
->record_llvm_ir
= device
->keep_shader_info
;
472 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
474 if (options
->supports_spill
)
475 tm_options
|= AC_TM_SUPPORTS_SPILL
;
476 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
477 tm_options
|= AC_TM_SISCHED
;
478 tm
= ac_create_target_machine(chip_family
, tm_options
);
480 if (gs_copy_shader
) {
481 assert(shader_count
== 1);
482 radv_compile_gs_copy_shader(tm
, *shaders
, &binary
,
483 &variant
->config
, &variant
->info
,
486 radv_compile_nir_shader(tm
, &binary
, &variant
->config
,
487 &variant
->info
, shaders
, shader_count
,
491 LLVMDisposeTargetMachine(tm
);
493 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
496 *code_out
= binary
.code
;
497 *code_size_out
= binary
.code_size
;
502 free(binary
.global_symbol_offsets
);
504 variant
->ref_count
= 1;
506 if (device
->keep_shader_info
) {
507 variant
->disasm_string
= binary
.disasm_string
;
508 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
509 if (!gs_copy_shader
&& !module
->nir
) {
510 variant
->nir
= *shaders
;
511 variant
->spirv
= (uint32_t *)module
->data
;
512 variant
->spirv_size
= module
->size
;
515 free(binary
.disasm_string
);
521 struct radv_shader_variant
*
522 radv_shader_variant_create(struct radv_device
*device
,
523 struct radv_shader_module
*module
,
524 struct nir_shader
*const *shaders
,
526 struct radv_pipeline_layout
*layout
,
527 const struct radv_shader_variant_key
*key
,
529 unsigned *code_size_out
)
531 struct radv_nir_compiler_options options
= {0};
533 options
.layout
= layout
;
537 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
538 options
.supports_spill
= device
->llvm_supports_spill
;
540 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
541 &options
, false, code_out
, code_size_out
);
544 struct radv_shader_variant
*
545 radv_create_gs_copy_shader(struct radv_device
*device
,
546 struct nir_shader
*shader
,
548 unsigned *code_size_out
,
551 struct radv_nir_compiler_options options
= {0};
553 options
.key
.has_multiview_view_index
= multiview
;
555 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
556 &options
, true, code_out
, code_size_out
);
560 radv_shader_variant_destroy(struct radv_device
*device
,
561 struct radv_shader_variant
*variant
)
563 if (!p_atomic_dec_zero(&variant
->ref_count
))
566 mtx_lock(&device
->shader_slab_mutex
);
567 list_del(&variant
->slab_list
);
568 mtx_unlock(&device
->shader_slab_mutex
);
570 ralloc_free(variant
->nir
);
571 free(variant
->disasm_string
);
572 free(variant
->llvm_ir_string
);
577 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
580 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
581 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
582 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
583 case MESA_SHADER_COMPUTE
: return "Compute Shader";
584 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
585 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
587 return "Unknown shader";
592 get_total_sgprs(struct radv_device
*device
)
594 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
601 generate_shader_stats(struct radv_device
*device
,
602 struct radv_shader_variant
*variant
,
603 gl_shader_stage stage
,
604 struct _mesa_string_buffer
*buf
)
606 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
607 struct ac_shader_config
*conf
;
608 unsigned max_simd_waves
;
609 unsigned lds_per_wave
= 0;
611 switch (device
->physical_device
->rad_info
.family
) {
612 /* These always have 8 waves: */
622 conf
= &variant
->config
;
624 if (stage
== MESA_SHADER_FRAGMENT
) {
625 lds_per_wave
= conf
->lds_size
* lds_increment
+
626 align(variant
->info
.fs
.num_interp
* 48,
631 max_simd_waves
= MIN2(max_simd_waves
, get_total_sgprs(device
) / conf
->num_sgprs
);
634 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
636 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
640 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
642 if (stage
== MESA_SHADER_FRAGMENT
) {
643 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
644 "SPI_PS_INPUT_ADDR = 0x%04x\n"
645 "SPI_PS_INPUT_ENA = 0x%04x\n",
646 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
649 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
652 "Spilled SGPRs: %d\n"
653 "Spilled VGPRs: %d\n"
654 "PrivMem VGPRS: %d\n"
655 "Code Size: %d bytes\n"
657 "Scratch: %d bytes per wave\n"
659 "********************\n\n\n",
660 conf
->num_sgprs
, conf
->num_vgprs
,
661 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
662 variant
->info
.private_mem_vgprs
, variant
->code_size
,
663 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
668 radv_shader_dump_stats(struct radv_device
*device
,
669 struct radv_shader_variant
*variant
,
670 gl_shader_stage stage
,
673 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
675 generate_shader_stats(device
, variant
, stage
, buf
);
677 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
678 fprintf(file
, "%s", buf
->buf
);
680 _mesa_string_buffer_destroy(buf
);
684 radv_GetShaderInfoAMD(VkDevice _device
,
685 VkPipeline _pipeline
,
686 VkShaderStageFlagBits shaderStage
,
687 VkShaderInfoTypeAMD infoType
,
691 RADV_FROM_HANDLE(radv_device
, device
, _device
);
692 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
693 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
694 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
695 struct _mesa_string_buffer
*buf
;
696 VkResult result
= VK_SUCCESS
;
698 /* Spec doesn't indicate what to do if the stage is invalid, so just
699 * return no info for this. */
701 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
704 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
706 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
708 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
709 struct ac_shader_config
*conf
= &variant
->config
;
711 VkShaderStatisticsInfoAMD statistics
= {};
712 statistics
.shaderStageMask
= shaderStage
;
713 statistics
.numPhysicalVgprs
= 256;
714 statistics
.numPhysicalSgprs
= get_total_sgprs(device
);
715 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
717 if (stage
== MESA_SHADER_COMPUTE
) {
718 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
719 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
721 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
722 ceil(workgroup_size
/ statistics
.numPhysicalVgprs
);
724 statistics
.computeWorkGroupSize
[0] = local_size
[0];
725 statistics
.computeWorkGroupSize
[1] = local_size
[1];
726 statistics
.computeWorkGroupSize
[2] = local_size
[2];
728 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
731 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
732 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
733 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
734 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
735 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
737 size_t size
= *pInfoSize
;
738 *pInfoSize
= sizeof(statistics
);
740 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
742 if (size
< *pInfoSize
)
743 result
= VK_INCOMPLETE
;
747 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
748 buf
= _mesa_string_buffer_create(NULL
, 1024);
750 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
751 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
752 generate_shader_stats(device
, variant
, stage
, buf
);
754 /* Need to include the null terminator. */
755 size_t length
= buf
->length
+ 1;
760 size_t size
= *pInfoSize
;
763 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
766 result
= VK_INCOMPLETE
;
769 _mesa_string_buffer_destroy(buf
);
772 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
773 result
= VK_ERROR_FEATURE_NOT_PRESENT
;