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af094e6220fb1366fb9ccaac8862e9d6bc158f3d
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 #include "util/string_buffer.h"
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_flrp64 = true,
56 .lower_fsat = true,
57 .lower_fdiv = true,
58 .lower_sub = true,
59 .lower_pack_snorm_2x16 = true,
60 .lower_pack_snorm_4x8 = true,
61 .lower_pack_unorm_2x16 = true,
62 .lower_pack_unorm_4x8 = true,
63 .lower_unpack_snorm_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_unorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_extract_byte = true,
68 .lower_extract_word = true,
69 .lower_ffma = true,
70 .vs_inputs_dual_locations = true,
71 .max_unroll_iterations = 32
72 };
73
74 VkResult radv_CreateShaderModule(
75 VkDevice _device,
76 const VkShaderModuleCreateInfo* pCreateInfo,
77 const VkAllocationCallbacks* pAllocator,
78 VkShaderModule* pShaderModule)
79 {
80 RADV_FROM_HANDLE(radv_device, device, _device);
81 struct radv_shader_module *module;
82
83 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
84 assert(pCreateInfo->flags == 0);
85
86 module = vk_alloc2(&device->alloc, pAllocator,
87 sizeof(*module) + pCreateInfo->codeSize, 8,
88 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
89 if (module == NULL)
90 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
91
92 module->nir = NULL;
93 module->size = pCreateInfo->codeSize;
94 memcpy(module->data, pCreateInfo->pCode, module->size);
95
96 _mesa_sha1_compute(module->data, module->size, module->sha1);
97
98 *pShaderModule = radv_shader_module_to_handle(module);
99
100 return VK_SUCCESS;
101 }
102
103 void radv_DestroyShaderModule(
104 VkDevice _device,
105 VkShaderModule _module,
106 const VkAllocationCallbacks* pAllocator)
107 {
108 RADV_FROM_HANDLE(radv_device, device, _device);
109 RADV_FROM_HANDLE(radv_shader_module, module, _module);
110
111 if (!module)
112 return;
113
114 vk_free2(&device->alloc, pAllocator, module);
115 }
116
117 void
118 radv_optimize_nir(struct nir_shader *shader)
119 {
120 bool progress;
121
122 do {
123 progress = false;
124
125 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
126 NIR_PASS_V(shader, nir_lower_64bit_pack);
127 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
128 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
129
130 NIR_PASS(progress, shader, nir_copy_prop);
131 NIR_PASS(progress, shader, nir_opt_remove_phis);
132 NIR_PASS(progress, shader, nir_opt_dce);
133 if (nir_opt_trivial_continues(shader)) {
134 progress = true;
135 NIR_PASS(progress, shader, nir_copy_prop);
136 NIR_PASS(progress, shader, nir_opt_remove_phis);
137 NIR_PASS(progress, shader, nir_opt_dce);
138 }
139 NIR_PASS(progress, shader, nir_opt_if);
140 NIR_PASS(progress, shader, nir_opt_dead_cf);
141 NIR_PASS(progress, shader, nir_opt_cse);
142 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
143 NIR_PASS(progress, shader, nir_opt_algebraic);
144 NIR_PASS(progress, shader, nir_opt_constant_folding);
145 NIR_PASS(progress, shader, nir_opt_undef);
146 NIR_PASS(progress, shader, nir_opt_conditional_discard);
147 if (shader->options->max_unroll_iterations) {
148 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
149 }
150 } while (progress);
151 }
152
153 nir_shader *
154 radv_shader_compile_to_nir(struct radv_device *device,
155 struct radv_shader_module *module,
156 const char *entrypoint_name,
157 gl_shader_stage stage,
158 const VkSpecializationInfo *spec_info)
159 {
160 if (strcmp(entrypoint_name, "main") != 0) {
161 radv_finishme("Multiple shaders per module not really supported");
162 }
163
164 nir_shader *nir;
165 nir_function *entry_point;
166 if (module->nir) {
167 /* Some things such as our meta clear/blit code will give us a NIR
168 * shader directly. In that case, we just ignore the SPIR-V entirely
169 * and just use the NIR shader */
170 nir = module->nir;
171 nir->options = &nir_options;
172 nir_validate_shader(nir);
173
174 assert(exec_list_length(&nir->functions) == 1);
175 struct exec_node *node = exec_list_get_head(&nir->functions);
176 entry_point = exec_node_data(nir_function, node, node);
177 } else {
178 uint32_t *spirv = (uint32_t *) module->data;
179 assert(module->size % 4 == 0);
180
181 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
182 radv_print_spirv(spirv, module->size, stderr);
183
184 uint32_t num_spec_entries = 0;
185 struct nir_spirv_specialization *spec_entries = NULL;
186 if (spec_info && spec_info->mapEntryCount > 0) {
187 num_spec_entries = spec_info->mapEntryCount;
188 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
189 for (uint32_t i = 0; i < num_spec_entries; i++) {
190 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
191 const void *data = spec_info->pData + entry.offset;
192 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
193
194 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
195 if (spec_info->dataSize == 8)
196 spec_entries[i].data64 = *(const uint64_t *)data;
197 else
198 spec_entries[i].data32 = *(const uint32_t *)data;
199 }
200 }
201 const struct spirv_to_nir_options spirv_options = {
202 .caps = {
203 .draw_parameters = true,
204 .float64 = true,
205 .image_read_without_format = true,
206 .image_write_without_format = true,
207 .tessellation = true,
208 .int64 = true,
209 .multiview = true,
210 .variable_pointers = true,
211 },
212 };
213 entry_point = spirv_to_nir(spirv, module->size / 4,
214 spec_entries, num_spec_entries,
215 stage, entrypoint_name,
216 &spirv_options, &nir_options);
217 nir = entry_point->shader;
218 assert(nir->info.stage == stage);
219 nir_validate_shader(nir);
220
221 free(spec_entries);
222
223 /* We have to lower away local constant initializers right before we
224 * inline functions. That way they get properly initialized at the top
225 * of the function and not at the top of its caller.
226 */
227 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
228 NIR_PASS_V(nir, nir_lower_returns);
229 NIR_PASS_V(nir, nir_inline_functions);
230
231 /* Pick off the single entrypoint that we want */
232 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
233 if (func != entry_point)
234 exec_node_remove(&func->node);
235 }
236 assert(exec_list_length(&nir->functions) == 1);
237 entry_point->name = ralloc_strdup(entry_point, "main");
238
239 NIR_PASS_V(nir, nir_remove_dead_variables,
240 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
241
242 /* Now that we've deleted all but the main function, we can go ahead and
243 * lower the rest of the constant initializers.
244 */
245 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
246 NIR_PASS_V(nir, nir_lower_system_values);
247 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
248 }
249
250 /* Vulkan uses the separate-shader linking model */
251 nir->info.separate_shader = true;
252
253 nir_shader_gather_info(nir, entry_point->impl);
254
255 /* While it would be nice not to have this flag, we are constrained
256 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
257 * on GFX9.
258 */
259 bool llvm_has_working_vgpr_indexing =
260 device->physical_device->rad_info.chip_class <= VI;
261
262 /* TODO: Indirect indexing of GS inputs is unimplemented.
263 *
264 * TCS and TES load inputs directly from LDS or offchip memory, so
265 * indirect indexing is trivial.
266 */
267 nir_variable_mode indirect_mask = 0;
268 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
269 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
270 nir->info.stage != MESA_SHADER_TESS_EVAL &&
271 !llvm_has_working_vgpr_indexing)) {
272 indirect_mask |= nir_var_shader_in;
273 }
274 if (!llvm_has_working_vgpr_indexing &&
275 nir->info.stage != MESA_SHADER_TESS_CTRL)
276 indirect_mask |= nir_var_shader_out;
277
278 /* TODO: We shouldn't need to do this, however LLVM isn't currently
279 * smart enough to handle indirects without causing excess spilling
280 * causing the gpu to hang.
281 *
282 * See the following thread for more details of the problem:
283 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
284 */
285 indirect_mask |= nir_var_local;
286
287 nir_lower_indirect_derefs(nir, indirect_mask);
288
289 static const nir_lower_tex_options tex_options = {
290 .lower_txp = ~0,
291 };
292
293 nir_lower_tex(nir, &tex_options);
294
295 nir_lower_vars_to_ssa(nir);
296 nir_lower_var_copies(nir);
297 nir_lower_global_vars_to_local(nir);
298 nir_remove_dead_variables(nir, nir_var_local);
299 radv_optimize_nir(nir);
300
301 return nir;
302 }
303
304 void *
305 radv_alloc_shader_memory(struct radv_device *device,
306 struct radv_shader_variant *shader)
307 {
308 mtx_lock(&device->shader_slab_mutex);
309 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
310 uint64_t offset = 0;
311 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
312 if (s->bo_offset - offset >= shader->code_size) {
313 shader->bo = slab->bo;
314 shader->bo_offset = offset;
315 list_addtail(&shader->slab_list, &s->slab_list);
316 mtx_unlock(&device->shader_slab_mutex);
317 return slab->ptr + offset;
318 }
319 offset = align_u64(s->bo_offset + s->code_size, 256);
320 }
321 if (slab->size - offset >= shader->code_size) {
322 shader->bo = slab->bo;
323 shader->bo_offset = offset;
324 list_addtail(&shader->slab_list, &slab->shaders);
325 mtx_unlock(&device->shader_slab_mutex);
326 return slab->ptr + offset;
327 }
328 }
329
330 mtx_unlock(&device->shader_slab_mutex);
331 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
332
333 slab->size = 256 * 1024;
334 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
335 RADEON_DOMAIN_VRAM,
336 RADEON_FLAG_NO_INTERPROCESS_SHARING |
337 device->physical_device->cpdma_prefetch_writes_memory ?
338 0 : RADEON_FLAG_READ_ONLY);
339 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
340 list_inithead(&slab->shaders);
341
342 mtx_lock(&device->shader_slab_mutex);
343 list_add(&slab->slabs, &device->shader_slabs);
344
345 shader->bo = slab->bo;
346 shader->bo_offset = 0;
347 list_add(&shader->slab_list, &slab->shaders);
348 mtx_unlock(&device->shader_slab_mutex);
349 return slab->ptr;
350 }
351
352 void
353 radv_destroy_shader_slabs(struct radv_device *device)
354 {
355 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
356 device->ws->buffer_destroy(slab->bo);
357 free(slab);
358 }
359 mtx_destroy(&device->shader_slab_mutex);
360 }
361
362 static void
363 radv_fill_shader_variant(struct radv_device *device,
364 struct radv_shader_variant *variant,
365 struct ac_shader_binary *binary,
366 gl_shader_stage stage)
367 {
368 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
369 unsigned vgpr_comp_cnt = 0;
370
371 if (scratch_enabled && !device->llvm_supports_spill)
372 radv_finishme("shader scratch support only available with LLVM 4.0");
373
374 variant->code_size = binary->code_size;
375 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
376 S_00B12C_SCRATCH_EN(scratch_enabled);
377
378 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
379 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
380 S_00B848_DX10_CLAMP(1) |
381 S_00B848_FLOAT_MODE(variant->config.float_mode);
382
383 switch (stage) {
384 case MESA_SHADER_TESS_EVAL:
385 vgpr_comp_cnt = 3;
386 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
387 break;
388 case MESA_SHADER_TESS_CTRL:
389 if (device->physical_device->rad_info.chip_class >= GFX9)
390 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
391 else
392 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
393 break;
394 case MESA_SHADER_VERTEX:
395 case MESA_SHADER_GEOMETRY:
396 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
397 break;
398 case MESA_SHADER_FRAGMENT:
399 break;
400 case MESA_SHADER_COMPUTE: {
401 struct ac_shader_info *info = &variant->info.info;
402 variant->rsrc2 |=
403 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
404 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
405 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
406 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
407 info->cs.uses_thread_id[1] ? 1 : 0) |
408 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
409 S_00B84C_LDS_SIZE(variant->config.lds_size);
410 break;
411 }
412 default:
413 unreachable("unsupported shader type");
414 break;
415 }
416
417 if (device->physical_device->rad_info.chip_class >= GFX9 &&
418 stage == MESA_SHADER_GEOMETRY) {
419 struct ac_shader_info *info = &variant->info.info;
420 unsigned es_type = variant->info.gs.es_type;
421 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
422
423 if (es_type == MESA_SHADER_VERTEX) {
424 es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
425 } else if (es_type == MESA_SHADER_TESS_EVAL) {
426 es_vgpr_comp_cnt = 3;
427 } else {
428 unreachable("invalid shader ES type");
429 }
430
431 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
432 * VGPR[0:4] are always loaded.
433 */
434 if (info->uses_invocation_id)
435 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
436 else if (info->uses_prim_id)
437 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
438 else if (variant->info.gs.vertices_in >= 3)
439 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
440 else
441 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
442
443 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
444 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
445 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
446 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
447 stage == MESA_SHADER_TESS_CTRL)
448 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
449 else
450 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
451
452 void *ptr = radv_alloc_shader_memory(device, variant);
453 memcpy(ptr, binary->code, binary->code_size);
454 }
455
456 static struct radv_shader_variant *
457 shader_variant_create(struct radv_device *device,
458 struct radv_shader_module *module,
459 struct nir_shader * const *shaders,
460 int shader_count,
461 gl_shader_stage stage,
462 struct ac_nir_compiler_options *options,
463 bool gs_copy_shader,
464 void **code_out,
465 unsigned *code_size_out)
466 {
467 enum radeon_family chip_family = device->physical_device->rad_info.family;
468 bool dump_shaders = radv_can_dump_shader(device, module);
469 enum ac_target_machine_options tm_options = 0;
470 struct radv_shader_variant *variant;
471 struct ac_shader_binary binary;
472 LLVMTargetMachineRef tm;
473
474 variant = calloc(1, sizeof(struct radv_shader_variant));
475 if (!variant)
476 return NULL;
477
478 options->family = chip_family;
479 options->chip_class = device->physical_device->rad_info.chip_class;
480 options->dump_preoptir = radv_can_dump_shader(device, module) &&
481 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
482
483 if (options->supports_spill)
484 tm_options |= AC_TM_SUPPORTS_SPILL;
485 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
486 tm_options |= AC_TM_SISCHED;
487 tm = ac_create_target_machine(chip_family, tm_options);
488
489 if (gs_copy_shader) {
490 assert(shader_count == 1);
491 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
492 &variant->info, options, dump_shaders);
493 } else {
494 ac_compile_nir_shader(tm, &binary, &variant->config,
495 &variant->info, shaders, shader_count, options,
496 dump_shaders);
497 }
498
499 LLVMDisposeTargetMachine(tm);
500
501 radv_fill_shader_variant(device, variant, &binary, stage);
502
503 if (code_out) {
504 *code_out = binary.code;
505 *code_size_out = binary.code_size;
506 } else
507 free(binary.code);
508 free(binary.config);
509 free(binary.rodata);
510 free(binary.global_symbol_offsets);
511 free(binary.relocs);
512 variant->ref_count = 1;
513
514 if (device->keep_shader_info) {
515 variant->disasm_string = binary.disasm_string;
516 if (!gs_copy_shader && !module->nir) {
517 variant->nir = *shaders;
518 variant->spirv = (uint32_t *)module->data;
519 variant->spirv_size = module->size;
520 }
521 } else {
522 free(binary.disasm_string);
523 }
524
525 return variant;
526 }
527
528 struct radv_shader_variant *
529 radv_shader_variant_create(struct radv_device *device,
530 struct radv_shader_module *module,
531 struct nir_shader *const *shaders,
532 int shader_count,
533 struct radv_pipeline_layout *layout,
534 const struct ac_shader_variant_key *key,
535 void **code_out,
536 unsigned *code_size_out)
537 {
538 struct ac_nir_compiler_options options = {0};
539
540 options.layout = layout;
541 if (key)
542 options.key = *key;
543
544 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
545 options.supports_spill = device->llvm_supports_spill;
546
547 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
548 &options, false, code_out, code_size_out);
549 }
550
551 struct radv_shader_variant *
552 radv_create_gs_copy_shader(struct radv_device *device,
553 struct nir_shader *shader,
554 void **code_out,
555 unsigned *code_size_out,
556 bool multiview)
557 {
558 struct ac_nir_compiler_options options = {0};
559
560 options.key.has_multiview_view_index = multiview;
561
562 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
563 &options, true, code_out, code_size_out);
564 }
565
566 void
567 radv_shader_variant_destroy(struct radv_device *device,
568 struct radv_shader_variant *variant)
569 {
570 if (!p_atomic_dec_zero(&variant->ref_count))
571 return;
572
573 mtx_lock(&device->shader_slab_mutex);
574 list_del(&variant->slab_list);
575 mtx_unlock(&device->shader_slab_mutex);
576
577 ralloc_free(variant->nir);
578 free(variant->disasm_string);
579 free(variant);
580 }
581
582 const char *
583 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
584 {
585 switch (stage) {
586 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
587 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
588 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
589 case MESA_SHADER_COMPUTE: return "Compute Shader";
590 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
591 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
592 default:
593 return "Unknown shader";
594 };
595 }
596
597 static uint32_t
598 get_total_sgprs(struct radv_device *device)
599 {
600 if (device->physical_device->rad_info.chip_class >= VI)
601 return 800;
602 else
603 return 512;
604 }
605
606 static void
607 generate_shader_stats(struct radv_device *device,
608 struct radv_shader_variant *variant,
609 gl_shader_stage stage,
610 struct _mesa_string_buffer *buf)
611 {
612 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
613 struct ac_shader_config *conf;
614 unsigned max_simd_waves;
615 unsigned lds_per_wave = 0;
616
617 switch (device->physical_device->rad_info.family) {
618 /* These always have 8 waves: */
619 case CHIP_POLARIS10:
620 case CHIP_POLARIS11:
621 case CHIP_POLARIS12:
622 max_simd_waves = 8;
623 break;
624 default:
625 max_simd_waves = 10;
626 }
627
628 conf = &variant->config;
629
630 if (stage == MESA_SHADER_FRAGMENT) {
631 lds_per_wave = conf->lds_size * lds_increment +
632 align(variant->info.fs.num_interp * 48,
633 lds_increment);
634 }
635
636 if (conf->num_sgprs)
637 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
638
639 if (conf->num_vgprs)
640 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
641
642 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
643 * that PS can use.
644 */
645 if (lds_per_wave)
646 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
647
648 if (stage == MESA_SHADER_FRAGMENT) {
649 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
650 "SPI_PS_INPUT_ADDR = 0x%04x\n"
651 "SPI_PS_INPUT_ENA = 0x%04x\n",
652 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
653 }
654
655 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
656 "SGPRS: %d\n"
657 "VGPRS: %d\n"
658 "Spilled SGPRs: %d\n"
659 "Spilled VGPRs: %d\n"
660 "Code Size: %d bytes\n"
661 "LDS: %d blocks\n"
662 "Scratch: %d bytes per wave\n"
663 "Max Waves: %d\n"
664 "********************\n\n\n",
665 conf->num_sgprs, conf->num_vgprs,
666 conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
667 conf->lds_size, conf->scratch_bytes_per_wave,
668 max_simd_waves);
669 }
670
671 void
672 radv_shader_dump_stats(struct radv_device *device,
673 struct radv_shader_variant *variant,
674 gl_shader_stage stage,
675 FILE *file)
676 {
677 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
678
679 generate_shader_stats(device, variant, stage, buf);
680
681 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
682 fprintf(file, "%s", buf->buf);
683
684 _mesa_string_buffer_destroy(buf);
685 }
686
687 VkResult
688 radv_GetShaderInfoAMD(VkDevice _device,
689 VkPipeline _pipeline,
690 VkShaderStageFlagBits shaderStage,
691 VkShaderInfoTypeAMD infoType,
692 size_t* pInfoSize,
693 void* pInfo)
694 {
695 RADV_FROM_HANDLE(radv_device, device, _device);
696 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
697 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
698 struct radv_shader_variant *variant = pipeline->shaders[stage];
699 struct _mesa_string_buffer *buf;
700 VkResult result = VK_SUCCESS;
701
702 /* Spec doesn't indicate what to do if the stage is invalid, so just
703 * return no info for this. */
704 if (!variant)
705 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
706
707 switch (infoType) {
708 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
709 if (!pInfo) {
710 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
711 } else {
712 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
713 struct ac_shader_config *conf = &variant->config;
714
715 VkShaderStatisticsInfoAMD statistics = {};
716 statistics.shaderStageMask = shaderStage;
717 statistics.numPhysicalVgprs = 256;
718 statistics.numPhysicalSgprs = get_total_sgprs(device);
719 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
720
721 if (stage == MESA_SHADER_COMPUTE) {
722 unsigned *local_size = variant->nir->info.cs.local_size;
723 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
724
725 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
726 ceil(workgroup_size / statistics.numPhysicalVgprs);
727
728 statistics.computeWorkGroupSize[0] = local_size[0];
729 statistics.computeWorkGroupSize[1] = local_size[1];
730 statistics.computeWorkGroupSize[2] = local_size[2];
731 } else {
732 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
733 }
734
735 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
736 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
737 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
738 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
739 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
740
741 size_t size = *pInfoSize;
742 *pInfoSize = sizeof(statistics);
743
744 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
745
746 if (size < *pInfoSize)
747 result = VK_INCOMPLETE;
748 }
749
750 break;
751 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
752 buf = _mesa_string_buffer_create(NULL, 1024);
753
754 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
755 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
756 generate_shader_stats(device, variant, stage, buf);
757
758 /* Need to include the null terminator. */
759 size_t length = buf->length + 1;
760
761 if (!pInfo) {
762 *pInfoSize = length;
763 } else {
764 size_t size = *pInfoSize;
765 *pInfoSize = length;
766
767 memcpy(pInfo, buf->buf, MIN2(size, length));
768
769 if (size < length)
770 result = VK_INCOMPLETE;
771 }
772
773 _mesa_string_buffer_destroy(buf);
774 break;
775 default:
776 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
777 result = VK_ERROR_FEATURE_NOT_PRESENT;
778 break;
779 }
780
781 return result;
782 }