2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
62 .lower_bitfield_insert_to_bitfield_select
= true,
63 .lower_bitfield_extract
= true,
65 .lower_pack_snorm_2x16
= true,
66 .lower_pack_snorm_4x8
= true,
67 .lower_pack_unorm_2x16
= true,
68 .lower_pack_unorm_4x8
= true,
69 .lower_unpack_snorm_2x16
= true,
70 .lower_unpack_snorm_4x8
= true,
71 .lower_unpack_unorm_2x16
= true,
72 .lower_unpack_unorm_4x8
= true,
73 .lower_extract_byte
= true,
74 .lower_extract_word
= true,
77 .lower_mul_2x32_64
= true,
79 .max_unroll_iterations
= 32,
80 .use_interpolated_input_intrinsics
= true,
84 radv_can_dump_shader(struct radv_device
*device
,
85 struct radv_shader_module
*module
,
86 bool is_gs_copy_shader
)
88 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
91 /* Only dump non-meta shaders, useful for debugging purposes. */
92 return (module
&& !module
->nir
) || is_gs_copy_shader
;
96 radv_can_dump_shader_stats(struct radv_device
*device
,
97 struct radv_shader_module
*module
)
99 /* Only dump non-meta shader stats. */
100 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
101 module
&& !module
->nir
;
104 unsigned shader_io_get_unique_index(gl_varying_slot slot
)
106 /* handle patch indices separate */
107 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
109 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
111 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
112 return 2 + (slot
- VARYING_SLOT_PATCH0
);
113 if (slot
== VARYING_SLOT_POS
)
115 if (slot
== VARYING_SLOT_PSIZ
)
117 if (slot
== VARYING_SLOT_CLIP_DIST0
)
119 if (slot
== VARYING_SLOT_CLIP_DIST1
)
121 /* 3 is reserved for clip dist as well */
122 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
123 return 4 + (slot
- VARYING_SLOT_VAR0
);
124 unreachable("illegal slot in get unique index\n");
127 VkResult
radv_CreateShaderModule(
129 const VkShaderModuleCreateInfo
* pCreateInfo
,
130 const VkAllocationCallbacks
* pAllocator
,
131 VkShaderModule
* pShaderModule
)
133 RADV_FROM_HANDLE(radv_device
, device
, _device
);
134 struct radv_shader_module
*module
;
136 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
137 assert(pCreateInfo
->flags
== 0);
139 module
= vk_alloc2(&device
->alloc
, pAllocator
,
140 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
143 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
146 module
->size
= pCreateInfo
->codeSize
;
147 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
149 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
151 *pShaderModule
= radv_shader_module_to_handle(module
);
156 void radv_DestroyShaderModule(
158 VkShaderModule _module
,
159 const VkAllocationCallbacks
* pAllocator
)
161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
162 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
167 vk_free2(&device
->alloc
, pAllocator
, module
);
171 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
175 unsigned lower_flrp
=
176 (shader
->options
->lower_flrp16
? 16 : 0) |
177 (shader
->options
->lower_flrp32
? 32 : 0) |
178 (shader
->options
->lower_flrp64
? 64 : 0);
183 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
184 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
186 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
187 NIR_PASS_V(shader
, nir_lower_pack
);
190 /* Only run this pass in the first call to
191 * radv_optimize_nir. Later calls assume that we've
192 * lowered away any copy_deref instructions and we
193 * don't want to introduce any more.
195 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
198 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
199 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
200 NIR_PASS(progress
, shader
, nir_remove_dead_variables
,
201 nir_var_function_temp
);
203 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
);
204 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
206 NIR_PASS(progress
, shader
, nir_copy_prop
);
207 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
208 NIR_PASS(progress
, shader
, nir_opt_dce
);
209 if (nir_opt_trivial_continues(shader
)) {
211 NIR_PASS(progress
, shader
, nir_copy_prop
);
212 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
213 NIR_PASS(progress
, shader
, nir_opt_dce
);
215 NIR_PASS(progress
, shader
, nir_opt_if
, true);
216 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
217 NIR_PASS(progress
, shader
, nir_opt_cse
);
218 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
219 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
220 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
222 if (lower_flrp
!= 0) {
223 bool lower_flrp_progress
= false;
224 NIR_PASS(lower_flrp_progress
,
228 false /* always_precise */,
229 shader
->options
->lower_ffma
);
230 if (lower_flrp_progress
) {
231 NIR_PASS(progress
, shader
,
232 nir_opt_constant_folding
);
236 /* Nothing should rematerialize any flrps, so we only
237 * need to do this lowering once.
242 NIR_PASS(progress
, shader
, nir_opt_undef
);
243 if (shader
->options
->max_unroll_iterations
) {
244 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
246 } while (progress
&& !optimize_conservatively
);
248 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
249 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
250 NIR_PASS(progress
, shader
, nir_opt_move
, nir_move_load_ubo
);
254 radv_shader_compile_to_nir(struct radv_device
*device
,
255 struct radv_shader_module
*module
,
256 const char *entrypoint_name
,
257 gl_shader_stage stage
,
258 const VkSpecializationInfo
*spec_info
,
259 const VkPipelineCreateFlags flags
,
260 const struct radv_pipeline_layout
*layout
)
264 /* Some things such as our meta clear/blit code will give us a NIR
265 * shader directly. In that case, we just ignore the SPIR-V entirely
266 * and just use the NIR shader */
268 nir
->options
= &nir_options
;
269 nir_validate_shader(nir
, "in internal shader");
271 assert(exec_list_length(&nir
->functions
) == 1);
273 uint32_t *spirv
= (uint32_t *) module
->data
;
274 assert(module
->size
% 4 == 0);
276 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
277 radv_print_spirv(spirv
, module
->size
, stderr
);
279 uint32_t num_spec_entries
= 0;
280 struct nir_spirv_specialization
*spec_entries
= NULL
;
281 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
282 num_spec_entries
= spec_info
->mapEntryCount
;
283 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
284 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
285 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
286 const void *data
= spec_info
->pData
+ entry
.offset
;
287 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
289 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
290 if (spec_info
->dataSize
== 8)
291 spec_entries
[i
].data64
= *(const uint64_t *)data
;
293 spec_entries
[i
].data32
= *(const uint32_t *)data
;
296 const struct spirv_to_nir_options spirv_options
= {
297 .lower_ubo_ssbo_access_to_offsets
= true,
299 .amd_gcn_shader
= true,
300 .amd_shader_ballot
= device
->physical_device
->use_shader_ballot
,
301 .amd_trinary_minmax
= true,
302 .derivative_group
= true,
303 .descriptor_array_dynamic_indexing
= true,
304 .descriptor_array_non_uniform_indexing
= true,
305 .descriptor_indexing
= true,
306 .device_group
= true,
307 .draw_parameters
= true,
310 .geometry_streams
= true,
311 .image_read_without_format
= true,
312 .image_write_without_format
= true,
316 .int64_atomics
= true,
318 .physical_storage_buffer_address
= true,
319 .post_depth_coverage
= true,
320 .runtime_descriptor_array
= true,
321 .shader_viewport_index_layer
= true,
322 .stencil_export
= true,
323 .storage_8bit
= true,
324 .storage_16bit
= true,
325 .storage_image_ms
= true,
326 .subgroup_arithmetic
= true,
327 .subgroup_ballot
= true,
328 .subgroup_basic
= true,
329 .subgroup_quad
= true,
330 .subgroup_shuffle
= true,
331 .subgroup_vote
= true,
332 .tessellation
= true,
333 .transform_feedback
= true,
334 .variable_pointers
= true,
336 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
337 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
338 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
339 .push_const_addr_format
= nir_address_format_logical
,
340 .shared_addr_format
= nir_address_format_32bit_offset
,
341 .frag_coord_is_sysval
= true,
343 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
344 spec_entries
, num_spec_entries
,
345 stage
, entrypoint_name
,
346 &spirv_options
, &nir_options
);
347 assert(nir
->info
.stage
== stage
);
348 nir_validate_shader(nir
, "after spirv_to_nir");
352 /* We have to lower away local constant initializers right before we
353 * inline functions. That way they get properly initialized at the top
354 * of the function and not at the top of its caller.
356 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
357 NIR_PASS_V(nir
, nir_lower_returns
);
358 NIR_PASS_V(nir
, nir_inline_functions
);
359 NIR_PASS_V(nir
, nir_opt_deref
);
361 /* Pick off the single entrypoint that we want */
362 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
363 if (func
->is_entrypoint
)
364 func
->name
= ralloc_strdup(func
, "main");
366 exec_node_remove(&func
->node
);
368 assert(exec_list_length(&nir
->functions
) == 1);
370 /* Make sure we lower constant initializers on output variables so that
371 * nir_remove_dead_variables below sees the corresponding stores
373 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
375 /* Now that we've deleted all but the main function, we can go ahead and
376 * lower the rest of the constant initializers.
378 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
380 /* Split member structs. We do this before lower_io_to_temporaries so that
381 * it doesn't lower system values to temporaries by accident.
383 NIR_PASS_V(nir
, nir_split_var_copies
);
384 NIR_PASS_V(nir
, nir_split_per_member_structs
);
386 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
387 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
389 NIR_PASS_V(nir
, nir_remove_dead_variables
,
390 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
392 NIR_PASS_V(nir
, nir_lower_system_values
);
393 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
394 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
397 /* Vulkan uses the separate-shader linking model */
398 nir
->info
.separate_shader
= true;
400 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
402 static const nir_lower_tex_options tex_options
= {
404 .lower_tg4_offsets
= true,
407 nir_lower_tex(nir
, &tex_options
);
409 nir_lower_vars_to_ssa(nir
);
411 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
412 nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
413 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
414 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
415 nir_shader_get_entrypoint(nir
), true, true);
416 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
417 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
418 nir_shader_get_entrypoint(nir
), true, false);
421 nir_split_var_copies(nir
);
423 nir_lower_global_vars_to_local(nir
);
424 nir_remove_dead_variables(nir
, nir_var_function_temp
);
425 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
427 .ballot_bit_size
= 64,
428 .lower_to_scalar
= 1,
429 .lower_subgroup_masks
= 1,
431 .lower_shuffle_to_32bit
= 1,
432 .lower_vote_eq_to_ballot
= 1,
435 nir_lower_load_const_to_scalar(nir
);
437 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
438 radv_optimize_nir(nir
, false, true);
440 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
441 * to remove any copies introduced by nir_opt_find_array_copies().
443 nir_lower_var_copies(nir
);
445 /* Indirect lowering must be called after the radv_optimize_nir() loop
446 * has been called at least once. Otherwise indirect lowering can
447 * bloat the instruction count of the loop and cause it to be
448 * considered too large for unrolling.
450 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
451 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
457 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
459 return glsl_count_attribute_slots(type
, false);
462 static nir_variable
*
463 find_layer_in_var(nir_shader
*nir
)
465 nir_foreach_variable(var
, &nir
->inputs
) {
466 if (var
->data
.location
== VARYING_SLOT_LAYER
) {
472 nir_variable_create(nir
, nir_var_shader_in
, glsl_int_type(), "layer id");
473 var
->data
.location
= VARYING_SLOT_LAYER
;
474 var
->data
.interpolation
= INTERP_MODE_FLAT
;
478 /* We use layered rendering to implement multiview, which means we need to map
479 * view_index to gl_Layer. The attachment lowering also uses needs to know the
480 * layer so that it can sample from the correct layer. The code generates a
481 * load from the layer_id sysval, but since we don't have a way to get at this
482 * information from the fragment shader, we also need to lower this to the
483 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
484 * slot, before lowering io, so that nir_assign_var_locations() will give the
485 * LAYER varying the correct driver_location.
489 lower_view_index(nir_shader
*nir
)
491 bool progress
= false;
492 nir_function_impl
*entry
= nir_shader_get_entrypoint(nir
);
494 nir_builder_init(&b
, entry
);
496 nir_variable
*layer
= NULL
;
497 nir_foreach_block(block
, entry
) {
498 nir_foreach_instr_safe(instr
, block
) {
499 if (instr
->type
!= nir_instr_type_intrinsic
)
502 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
503 if (load
->intrinsic
!= nir_intrinsic_load_view_index
&&
504 load
->intrinsic
!= nir_intrinsic_load_layer_id
)
508 layer
= find_layer_in_var(nir
);
510 b
.cursor
= nir_before_instr(instr
);
511 nir_ssa_def
*def
= nir_load_var(&b
, layer
);
512 nir_ssa_def_rewrite_uses(&load
->dest
.ssa
,
513 nir_src_for_ssa(def
));
515 nir_instr_remove(instr
);
524 radv_lower_fs_io(nir_shader
*nir
)
526 NIR_PASS_V(nir
, lower_view_index
);
527 nir_assign_io_var_locations(&nir
->inputs
, &nir
->num_inputs
,
528 MESA_SHADER_FRAGMENT
);
530 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
532 /* This pass needs actual constants */
533 nir_opt_constant_folding(nir
);
535 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
540 radv_alloc_shader_memory(struct radv_device
*device
,
541 struct radv_shader_variant
*shader
)
543 mtx_lock(&device
->shader_slab_mutex
);
544 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
546 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
547 if (s
->bo_offset
- offset
>= shader
->code_size
) {
548 shader
->bo
= slab
->bo
;
549 shader
->bo_offset
= offset
;
550 list_addtail(&shader
->slab_list
, &s
->slab_list
);
551 mtx_unlock(&device
->shader_slab_mutex
);
552 return slab
->ptr
+ offset
;
554 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
556 if (slab
->size
- offset
>= shader
->code_size
) {
557 shader
->bo
= slab
->bo
;
558 shader
->bo_offset
= offset
;
559 list_addtail(&shader
->slab_list
, &slab
->shaders
);
560 mtx_unlock(&device
->shader_slab_mutex
);
561 return slab
->ptr
+ offset
;
565 mtx_unlock(&device
->shader_slab_mutex
);
566 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
568 slab
->size
= 256 * 1024;
569 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
571 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
572 (device
->physical_device
->rad_info
.cpdma_prefetch_writes_memory
?
573 0 : RADEON_FLAG_READ_ONLY
),
574 RADV_BO_PRIORITY_SHADER
);
575 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
576 list_inithead(&slab
->shaders
);
578 mtx_lock(&device
->shader_slab_mutex
);
579 list_add(&slab
->slabs
, &device
->shader_slabs
);
581 shader
->bo
= slab
->bo
;
582 shader
->bo_offset
= 0;
583 list_add(&shader
->slab_list
, &slab
->shaders
);
584 mtx_unlock(&device
->shader_slab_mutex
);
589 radv_destroy_shader_slabs(struct radv_device
*device
)
591 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
592 device
->ws
->buffer_destroy(slab
->bo
);
595 mtx_destroy(&device
->shader_slab_mutex
);
598 /* For the UMR disassembler. */
599 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
600 #define DEBUGGER_NUM_MARKERS 5
603 radv_get_shader_binary_size(size_t code_size
)
605 return code_size
+ DEBUGGER_NUM_MARKERS
* 4;
608 static void radv_postprocess_config(const struct radv_physical_device
*pdevice
,
609 const struct ac_shader_config
*config_in
,
610 const struct radv_shader_variant_info
*info
,
611 gl_shader_stage stage
,
612 struct ac_shader_config
*config_out
)
614 bool scratch_enabled
= config_in
->scratch_bytes_per_wave
> 0;
615 unsigned vgpr_comp_cnt
= 0;
616 unsigned num_input_vgprs
= info
->num_input_vgprs
;
618 if (stage
== MESA_SHADER_FRAGMENT
) {
620 if (G_0286CC_PERSP_SAMPLE_ENA(config_in
->spi_ps_input_addr
))
621 num_input_vgprs
+= 2;
622 if (G_0286CC_PERSP_CENTER_ENA(config_in
->spi_ps_input_addr
))
623 num_input_vgprs
+= 2;
624 if (G_0286CC_PERSP_CENTROID_ENA(config_in
->spi_ps_input_addr
))
625 num_input_vgprs
+= 2;
626 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in
->spi_ps_input_addr
))
627 num_input_vgprs
+= 3;
628 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in
->spi_ps_input_addr
))
629 num_input_vgprs
+= 2;
630 if (G_0286CC_LINEAR_CENTER_ENA(config_in
->spi_ps_input_addr
))
631 num_input_vgprs
+= 2;
632 if (G_0286CC_LINEAR_CENTROID_ENA(config_in
->spi_ps_input_addr
))
633 num_input_vgprs
+= 2;
634 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in
->spi_ps_input_addr
))
635 num_input_vgprs
+= 1;
636 if (G_0286CC_POS_X_FLOAT_ENA(config_in
->spi_ps_input_addr
))
637 num_input_vgprs
+= 1;
638 if (G_0286CC_POS_Y_FLOAT_ENA(config_in
->spi_ps_input_addr
))
639 num_input_vgprs
+= 1;
640 if (G_0286CC_POS_Z_FLOAT_ENA(config_in
->spi_ps_input_addr
))
641 num_input_vgprs
+= 1;
642 if (G_0286CC_POS_W_FLOAT_ENA(config_in
->spi_ps_input_addr
))
643 num_input_vgprs
+= 1;
644 if (G_0286CC_FRONT_FACE_ENA(config_in
->spi_ps_input_addr
))
645 num_input_vgprs
+= 1;
646 if (G_0286CC_ANCILLARY_ENA(config_in
->spi_ps_input_addr
))
647 num_input_vgprs
+= 1;
648 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in
->spi_ps_input_addr
))
649 num_input_vgprs
+= 1;
650 if (G_0286CC_POS_FIXED_PT_ENA(config_in
->spi_ps_input_addr
))
651 num_input_vgprs
+= 1;
654 unsigned num_vgprs
= MAX2(config_in
->num_vgprs
, num_input_vgprs
);
655 /* +3 for scratch wave offset and VCC */
656 unsigned num_sgprs
= MAX2(config_in
->num_sgprs
, info
->num_input_sgprs
+ 3);
658 *config_out
= *config_in
;
659 config_out
->num_vgprs
= num_vgprs
;
660 config_out
->num_sgprs
= num_sgprs
;
662 /* Enable 64-bit and 16-bit denormals, because there is no performance
665 * If denormals are enabled, all floating-point output modifiers are
668 * Don't enable denormals for 32-bit floats, because:
669 * - Floating-point output modifiers would be ignored by the hw.
670 * - Some opcodes don't support denormals, such as v_mad_f32. We would
671 * have to stop using those.
672 * - GFX6 & GFX7 would be very slow.
674 config_out
->float_mode
|= V_00B028_FP_64_DENORMS
;
676 config_out
->rsrc2
= S_00B12C_USER_SGPR(info
->num_user_sgprs
) |
677 S_00B12C_SCRATCH_EN(scratch_enabled
) |
678 S_00B12C_SO_BASE0_EN(!!info
->info
.so
.strides
[0]) |
679 S_00B12C_SO_BASE1_EN(!!info
->info
.so
.strides
[1]) |
680 S_00B12C_SO_BASE2_EN(!!info
->info
.so
.strides
[2]) |
681 S_00B12C_SO_BASE3_EN(!!info
->info
.so
.strides
[3]) |
682 S_00B12C_SO_EN(!!info
->info
.so
.num_outputs
);
684 config_out
->rsrc1
= S_00B848_VGPRS((num_vgprs
- 1) /
685 (info
->info
.wave_size
== 32 ? 8 : 4)) |
686 S_00B848_DX10_CLAMP(1) |
687 S_00B848_FLOAT_MODE(config_out
->float_mode
);
689 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
690 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(info
->num_user_sgprs
>> 5);
692 config_out
->rsrc1
|= S_00B228_SGPRS((num_sgprs
- 1) / 8);
693 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(info
->num_user_sgprs
>> 5);
697 case MESA_SHADER_TESS_EVAL
:
699 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
700 config_out
->rsrc2
|= S_00B22C_OC_LDS_EN(1);
701 } else if (info
->tes
.as_es
) {
702 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
703 vgpr_comp_cnt
= info
->info
.uses_prim_id
? 3 : 2;
705 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
707 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->info
.uses_prim_id
;
708 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
710 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
711 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
714 case MESA_SHADER_TESS_CTRL
:
715 if (pdevice
->rad_info
.chip_class
>= GFX9
) {
716 /* We need at least 2 components for LS.
717 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
718 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
720 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
721 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 3 : 1;
723 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 2 : 1;
726 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
728 config_out
->rsrc1
|= S_00B428_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
729 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
731 case MESA_SHADER_VERTEX
:
733 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
734 } else if (info
->vs
.as_ls
) {
735 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
736 /* We need at least 2 components for LS.
737 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
738 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
740 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 2 : 1;
741 } else if (info
->vs
.as_es
) {
742 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
743 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
744 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 1 : 0;
746 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
747 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
748 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
750 if (info
->info
.vs
.needs_instance_id
&& pdevice
->rad_info
.chip_class
>= GFX10
) {
752 } else if (info
->vs
.export_prim_id
) {
754 } else if (info
->info
.vs
.needs_instance_id
) {
760 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
763 case MESA_SHADER_FRAGMENT
:
764 config_out
->rsrc1
|= S_00B028_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
766 case MESA_SHADER_GEOMETRY
:
767 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
768 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
770 case MESA_SHADER_COMPUTE
:
771 config_out
->rsrc1
|= S_00B848_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
772 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
774 S_00B84C_TGID_X_EN(info
->info
.cs
.uses_block_id
[0]) |
775 S_00B84C_TGID_Y_EN(info
->info
.cs
.uses_block_id
[1]) |
776 S_00B84C_TGID_Z_EN(info
->info
.cs
.uses_block_id
[2]) |
777 S_00B84C_TIDIG_COMP_CNT(info
->info
.cs
.uses_thread_id
[2] ? 2 :
778 info
->info
.cs
.uses_thread_id
[1] ? 1 : 0) |
779 S_00B84C_TG_SIZE_EN(info
->info
.cs
.uses_local_invocation_idx
) |
780 S_00B84C_LDS_SIZE(config_in
->lds_size
);
783 unreachable("unsupported shader type");
787 if (pdevice
->rad_info
.chip_class
>= GFX10
&& info
->is_ngg
&&
788 (stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_GEOMETRY
)) {
789 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
790 gl_shader_stage es_stage
= stage
;
791 if (stage
== MESA_SHADER_GEOMETRY
)
792 es_stage
= info
->gs
.es_type
;
794 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
795 if (es_stage
== MESA_SHADER_VERTEX
) {
796 es_vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 3 : 0;
797 } else if (es_stage
== MESA_SHADER_TESS_EVAL
) {
798 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->info
.uses_prim_id
;
799 es_vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
801 unreachable("Unexpected ES shader stage");
803 bool tes_triangles
= stage
== MESA_SHADER_TESS_EVAL
&&
804 info
->tes
.primitive_mode
>= 4; /* GL_TRIANGLES */
805 if (info
->info
.uses_invocation_id
|| stage
== MESA_SHADER_VERTEX
) {
806 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
807 } else if (info
->info
.uses_prim_id
) {
808 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
809 } else if (info
->gs
.vertices_in
>= 3 || tes_triangles
) {
810 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
812 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
815 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
) |
816 S_00B228_WGP_MODE(1);
817 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
818 S_00B22C_LDS_SIZE(config_in
->lds_size
) |
819 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
);
820 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
821 stage
== MESA_SHADER_GEOMETRY
) {
822 unsigned es_type
= info
->gs
.es_type
;
823 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
825 if (es_type
== MESA_SHADER_VERTEX
) {
826 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
827 if (info
->info
.vs
.needs_instance_id
) {
828 es_vgpr_comp_cnt
= pdevice
->rad_info
.chip_class
>= GFX10
? 3 : 1;
830 es_vgpr_comp_cnt
= 0;
832 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
833 es_vgpr_comp_cnt
= info
->info
.uses_prim_id
? 3 : 2;
835 unreachable("invalid shader ES type");
838 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
839 * VGPR[0:4] are always loaded.
841 if (info
->info
.uses_invocation_id
) {
842 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
843 } else if (info
->info
.uses_prim_id
) {
844 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
845 } else if (info
->gs
.vertices_in
>= 3) {
846 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
848 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
851 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
852 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
853 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
854 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
855 stage
== MESA_SHADER_TESS_CTRL
) {
856 config_out
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
858 config_out
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
862 struct radv_shader_variant
*
863 radv_shader_variant_create(struct radv_device
*device
,
864 const struct radv_shader_binary
*binary
,
865 bool keep_shader_info
)
867 struct ac_shader_config config
= {0};
868 struct ac_rtld_binary rtld_binary
= {0};
869 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
873 variant
->ref_count
= 1;
875 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
876 struct ac_rtld_symbol lds_symbols
[1];
877 unsigned num_lds_symbols
= 0;
878 const char *elf_data
= (const char *)((struct radv_shader_binary_rtld
*)binary
)->data
;
879 size_t elf_size
= ((struct radv_shader_binary_rtld
*)binary
)->elf_size
;
880 unsigned esgs_ring_size
= 0;
882 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
883 binary
->stage
== MESA_SHADER_GEOMETRY
&& !binary
->is_gs_copy_shader
) {
884 /* TODO: Do not hardcode this value */
885 esgs_ring_size
= 32 * 1024;
888 if (binary
->variant_info
.is_ngg
) {
889 /* GS stores Primitive IDs into LDS at the address
890 * corresponding to the ES thread of the provoking
891 * vertex. All ES threads load and export PrimitiveID
894 if (binary
->stage
== MESA_SHADER_VERTEX
&&
895 binary
->variant_info
.vs
.export_prim_id
) {
896 /* TODO: Do not harcode this value */
897 esgs_ring_size
= 256 /* max_out_verts */ * 4;
901 if (esgs_ring_size
) {
902 /* We add this symbol even on LLVM <= 8 to ensure that
903 * shader->config.lds_size is set correctly below.
905 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
906 sym
->name
= "esgs_ring";
907 sym
->size
= esgs_ring_size
;
908 sym
->align
= 64 * 1024;
910 /* Make sure to have LDS space for NGG scratch. */
911 /* TODO: Compute this correctly somehow? */
912 if (binary
->variant_info
.is_ngg
)
916 struct ac_rtld_open_info open_info
= {
917 .info
= &device
->physical_device
->rad_info
,
918 .shader_type
= binary
->stage
,
919 .wave_size
= binary
->variant_info
.info
.wave_size
,
921 .elf_ptrs
= &elf_data
,
922 .elf_sizes
= &elf_size
,
923 .num_shared_lds_symbols
= num_lds_symbols
,
924 .shared_lds_symbols
= lds_symbols
,
927 if (!ac_rtld_open(&rtld_binary
, open_info
)) {
932 if (!ac_rtld_read_config(&rtld_binary
, &config
)) {
933 ac_rtld_close(&rtld_binary
);
938 if (rtld_binary
.lds_size
> 0) {
939 unsigned alloc_granularity
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
940 config
.lds_size
= align(rtld_binary
.lds_size
, alloc_granularity
) / alloc_granularity
;
943 variant
->code_size
= rtld_binary
.rx_size
;
944 variant
->exec_size
= rtld_binary
.exec_size
;
946 assert(binary
->type
== RADV_BINARY_TYPE_LEGACY
);
947 config
= ((struct radv_shader_binary_legacy
*)binary
)->config
;
948 variant
->code_size
= radv_get_shader_binary_size(((struct radv_shader_binary_legacy
*)binary
)->code_size
);
949 variant
->exec_size
= variant
->code_size
;
952 variant
->info
= binary
->variant_info
;
953 radv_postprocess_config(device
->physical_device
, &config
, &binary
->variant_info
,
954 binary
->stage
, &variant
->config
);
956 void *dest_ptr
= radv_alloc_shader_memory(device
, variant
);
958 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
959 struct radv_shader_binary_rtld
* bin
= (struct radv_shader_binary_rtld
*)binary
;
960 struct ac_rtld_upload_info info
= {
961 .binary
= &rtld_binary
,
962 .rx_va
= radv_buffer_get_va(variant
->bo
) + variant
->bo_offset
,
966 if (!ac_rtld_upload(&info
)) {
967 radv_shader_variant_destroy(device
, variant
);
968 ac_rtld_close(&rtld_binary
);
972 if (keep_shader_info
||
973 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
)) {
974 const char *disasm_data
;
976 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm_data
, &disasm_size
)) {
977 radv_shader_variant_destroy(device
, variant
);
978 ac_rtld_close(&rtld_binary
);
982 variant
->llvm_ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->elf_size
)) : NULL
;
983 variant
->disasm_string
= malloc(disasm_size
+ 1);
984 memcpy(variant
->disasm_string
, disasm_data
, disasm_size
);
985 variant
->disasm_string
[disasm_size
] = 0;
988 ac_rtld_close(&rtld_binary
);
990 struct radv_shader_binary_legacy
* bin
= (struct radv_shader_binary_legacy
*)binary
;
991 memcpy(dest_ptr
, bin
->data
, bin
->code_size
);
993 /* Add end-of-code markers for the UMR disassembler. */
994 uint32_t *ptr32
= (uint32_t *)dest_ptr
+ bin
->code_size
/ 4;
995 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
996 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
998 variant
->llvm_ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->code_size
)) : NULL
;
999 variant
->disasm_string
= bin
->disasm_size
? strdup((const char*)(bin
->data
+ bin
->code_size
+ bin
->llvm_ir_size
)) : NULL
;
1005 radv_dump_nir_shaders(struct nir_shader
* const *shaders
,
1011 FILE *f
= open_memstream(&data
, &size
);
1013 for (int i
= 0; i
< shader_count
; ++i
)
1014 nir_print_shader(shaders
[i
], f
);
1018 ret
= malloc(size
+ 1);
1020 memcpy(ret
, data
, size
);
1027 static struct radv_shader_variant
*
1028 shader_variant_compile(struct radv_device
*device
,
1029 struct radv_shader_module
*module
,
1030 struct nir_shader
* const *shaders
,
1032 gl_shader_stage stage
,
1033 struct radv_nir_compiler_options
*options
,
1034 bool gs_copy_shader
,
1035 bool keep_shader_info
,
1036 struct radv_shader_binary
**binary_out
)
1038 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
1039 enum ac_target_machine_options tm_options
= 0;
1040 struct ac_llvm_compiler ac_llvm
;
1041 struct radv_shader_binary
*binary
= NULL
;
1042 struct radv_shader_variant_info variant_info
= {0};
1043 bool thread_compiler
;
1045 options
->family
= chip_family
;
1046 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
1047 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
1048 options
->dump_preoptir
= options
->dump_shader
&&
1049 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
1050 options
->record_llvm_ir
= keep_shader_info
;
1051 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
1052 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
1053 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
1054 options
->has_ls_vgpr_init_bug
= device
->physical_device
->rad_info
.has_ls_vgpr_init_bug
;
1056 if ((stage
== MESA_SHADER_GEOMETRY
&& !options
->key
.vs_common_out
.as_ngg
) ||
1058 options
->wave_size
= 64;
1059 else if (stage
== MESA_SHADER_COMPUTE
)
1060 options
->wave_size
= device
->physical_device
->cs_wave_size
;
1061 else if (stage
== MESA_SHADER_FRAGMENT
)
1062 options
->wave_size
= device
->physical_device
->ps_wave_size
;
1064 options
->wave_size
= device
->physical_device
->ge_wave_size
;
1066 if (options
->supports_spill
)
1067 tm_options
|= AC_TM_SUPPORTS_SPILL
;
1068 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
1069 tm_options
|= AC_TM_SISCHED
;
1070 if (options
->check_ir
)
1071 tm_options
|= AC_TM_CHECK_IR
;
1072 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
1073 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
1075 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
1076 ac_init_llvm_once();
1077 radv_init_llvm_compiler(&ac_llvm
,
1079 chip_family
, tm_options
,
1080 options
->wave_size
);
1081 if (gs_copy_shader
) {
1082 assert(shader_count
== 1);
1083 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
1084 &variant_info
, options
);
1086 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant_info
,
1087 shaders
, shader_count
, options
);
1089 binary
->variant_info
= variant_info
;
1091 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
1093 struct radv_shader_variant
*variant
= radv_shader_variant_create(device
, binary
,
1100 if (options
->dump_shader
) {
1101 fprintf(stderr
, "disasm:\n%s\n", variant
->disasm_string
);
1105 if (keep_shader_info
) {
1106 variant
->nir_string
= radv_dump_nir_shaders(shaders
, shader_count
);
1107 if (!gs_copy_shader
&& !module
->nir
) {
1108 variant
->spirv
= (uint32_t *)module
->data
;
1109 variant
->spirv_size
= module
->size
;
1114 *binary_out
= binary
;
1121 struct radv_shader_variant
*
1122 radv_shader_variant_compile(struct radv_device
*device
,
1123 struct radv_shader_module
*module
,
1124 struct nir_shader
*const *shaders
,
1126 struct radv_pipeline_layout
*layout
,
1127 const struct radv_shader_variant_key
*key
,
1128 bool keep_shader_info
,
1129 struct radv_shader_binary
**binary_out
)
1131 struct radv_nir_compiler_options options
= {0};
1133 options
.layout
= layout
;
1137 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
1138 options
.supports_spill
= true;
1139 options
.robust_buffer_access
= device
->robust_buffer_access
;
1141 return shader_variant_compile(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
1142 &options
, false, keep_shader_info
, binary_out
);
1145 struct radv_shader_variant
*
1146 radv_create_gs_copy_shader(struct radv_device
*device
,
1147 struct nir_shader
*shader
,
1148 struct radv_shader_binary
**binary_out
,
1149 bool keep_shader_info
,
1152 struct radv_nir_compiler_options options
= {0};
1154 options
.key
.has_multiview_view_index
= multiview
;
1156 return shader_variant_compile(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
1157 &options
, true, keep_shader_info
, binary_out
);
1161 radv_shader_variant_destroy(struct radv_device
*device
,
1162 struct radv_shader_variant
*variant
)
1164 if (!p_atomic_dec_zero(&variant
->ref_count
))
1167 mtx_lock(&device
->shader_slab_mutex
);
1168 list_del(&variant
->slab_list
);
1169 mtx_unlock(&device
->shader_slab_mutex
);
1171 free(variant
->nir_string
);
1172 free(variant
->disasm_string
);
1173 free(variant
->llvm_ir_string
);
1178 radv_get_shader_name(struct radv_shader_variant_info
*info
,
1179 gl_shader_stage stage
)
1182 case MESA_SHADER_VERTEX
:
1184 return "Vertex Shader as LS";
1185 else if (info
->vs
.as_es
)
1186 return "Vertex Shader as ES";
1187 else if (info
->is_ngg
)
1188 return "Vertex Shader as ESGS";
1190 return "Vertex Shader as VS";
1191 case MESA_SHADER_TESS_CTRL
:
1192 return "Tessellation Control Shader";
1193 case MESA_SHADER_TESS_EVAL
:
1194 if (info
->tes
.as_es
)
1195 return "Tessellation Evaluation Shader as ES";
1196 else if (info
->is_ngg
)
1197 return "Tessellation Evaluation Shader as ESGS";
1199 return "Tessellation Evaluation Shader as VS";
1200 case MESA_SHADER_GEOMETRY
:
1201 return "Geometry Shader";
1202 case MESA_SHADER_FRAGMENT
:
1203 return "Pixel Shader";
1204 case MESA_SHADER_COMPUTE
:
1205 return "Compute Shader";
1207 return "Unknown shader";
1212 radv_get_max_workgroup_size(enum chip_class chip_class
,
1213 gl_shader_stage stage
,
1214 const unsigned *sizes
)
1217 case MESA_SHADER_TESS_CTRL
:
1218 return chip_class
>= GFX7
? 128 : 64;
1219 case MESA_SHADER_GEOMETRY
:
1220 return chip_class
>= GFX9
? 128 : 64;
1221 case MESA_SHADER_COMPUTE
:
1227 unsigned max_workgroup_size
= sizes
[0] * sizes
[1] * sizes
[2];
1228 return max_workgroup_size
;
1232 radv_get_max_waves(struct radv_device
*device
,
1233 struct radv_shader_variant
*variant
,
1234 gl_shader_stage stage
)
1236 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
1237 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
1238 uint8_t wave_size
= variant
->info
.info
.wave_size
;
1239 struct ac_shader_config
*conf
= &variant
->config
;
1240 unsigned max_simd_waves
;
1241 unsigned lds_per_wave
= 0;
1243 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
1245 if (stage
== MESA_SHADER_FRAGMENT
) {
1246 lds_per_wave
= conf
->lds_size
* lds_increment
+
1247 align(variant
->info
.info
.ps
.num_interp
* 48,
1249 } else if (stage
== MESA_SHADER_COMPUTE
) {
1250 unsigned max_workgroup_size
=
1251 radv_get_max_workgroup_size(chip_class
, stage
, variant
->info
.cs
.block_size
);
1252 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
1253 DIV_ROUND_UP(max_workgroup_size
, wave_size
);
1256 if (conf
->num_sgprs
)
1258 MIN2(max_simd_waves
,
1259 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
1261 if (conf
->num_vgprs
)
1263 MIN2(max_simd_waves
,
1264 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
1266 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1270 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
1272 return max_simd_waves
;
1276 generate_shader_stats(struct radv_device
*device
,
1277 struct radv_shader_variant
*variant
,
1278 gl_shader_stage stage
,
1279 struct _mesa_string_buffer
*buf
)
1281 struct ac_shader_config
*conf
= &variant
->config
;
1282 unsigned max_simd_waves
= radv_get_max_waves(device
, variant
, stage
);
1284 if (stage
== MESA_SHADER_FRAGMENT
) {
1285 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
1286 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1287 "SPI_PS_INPUT_ENA = 0x%04x\n",
1288 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
1291 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
1294 "Spilled SGPRs: %d\n"
1295 "Spilled VGPRs: %d\n"
1296 "PrivMem VGPRS: %d\n"
1297 "Code Size: %d bytes\n"
1299 "Scratch: %d bytes per wave\n"
1301 "********************\n\n\n",
1302 conf
->num_sgprs
, conf
->num_vgprs
,
1303 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
1304 variant
->info
.private_mem_vgprs
, variant
->exec_size
,
1305 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
1310 radv_shader_dump_stats(struct radv_device
*device
,
1311 struct radv_shader_variant
*variant
,
1312 gl_shader_stage stage
,
1315 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
1317 generate_shader_stats(device
, variant
, stage
, buf
);
1319 fprintf(file
, "\n%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1320 fprintf(file
, "%s", buf
->buf
);
1322 _mesa_string_buffer_destroy(buf
);
1326 radv_GetShaderInfoAMD(VkDevice _device
,
1327 VkPipeline _pipeline
,
1328 VkShaderStageFlagBits shaderStage
,
1329 VkShaderInfoTypeAMD infoType
,
1333 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1334 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
1335 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
1336 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
1337 struct _mesa_string_buffer
*buf
;
1338 VkResult result
= VK_SUCCESS
;
1340 /* Spec doesn't indicate what to do if the stage is invalid, so just
1341 * return no info for this. */
1343 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1346 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
1348 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
1350 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1351 struct ac_shader_config
*conf
= &variant
->config
;
1353 VkShaderStatisticsInfoAMD statistics
= {};
1354 statistics
.shaderStageMask
= shaderStage
;
1355 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
1356 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
1357 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
1359 if (stage
== MESA_SHADER_COMPUTE
) {
1360 unsigned *local_size
= variant
->info
.cs
.block_size
;
1361 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
1363 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
1364 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
1366 statistics
.computeWorkGroupSize
[0] = local_size
[0];
1367 statistics
.computeWorkGroupSize
[1] = local_size
[1];
1368 statistics
.computeWorkGroupSize
[2] = local_size
[2];
1370 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
1373 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
1374 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
1375 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
1376 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
1377 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
1379 size_t size
= *pInfoSize
;
1380 *pInfoSize
= sizeof(statistics
);
1382 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
1384 if (size
< *pInfoSize
)
1385 result
= VK_INCOMPLETE
;
1389 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
1390 buf
= _mesa_string_buffer_create(NULL
, 1024);
1392 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1393 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
1394 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
1395 generate_shader_stats(device
, variant
, stage
, buf
);
1397 /* Need to include the null terminator. */
1398 size_t length
= buf
->length
+ 1;
1401 *pInfoSize
= length
;
1403 size_t size
= *pInfoSize
;
1404 *pInfoSize
= length
;
1406 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
1409 result
= VK_INCOMPLETE
;
1412 _mesa_string_buffer_destroy(buf
);
1415 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1416 result
= VK_ERROR_FEATURE_NOT_PRESENT
;