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radv: Override the uniform buffer offset alignment for World War Z.
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 struct radv_spirv_debug_data {
303 struct radv_device *device;
304 const struct radv_shader_module *module;
305 };
306
307 static void radv_spirv_nir_debug(void *private_data,
308 enum nir_spirv_debug_level level,
309 size_t spirv_offset,
310 const char *message)
311 {
312 struct radv_spirv_debug_data *debug_data = private_data;
313 struct radv_instance *instance = debug_data->device->instance;
314
315 static const VkDebugReportFlagsEXT vk_flags[] = {
316 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
317 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
318 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
319 };
320 char buffer[256];
321
322 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s",
323 (unsigned long)spirv_offset, message);
324
325 vk_debug_report(&instance->debug_report_callbacks,
326 vk_flags[level],
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
328 (uint64_t)(uintptr_t)debug_data->module,
329 0, 0, "radv", buffer);
330 }
331
332 nir_shader *
333 radv_shader_compile_to_nir(struct radv_device *device,
334 struct radv_shader_module *module,
335 const char *entrypoint_name,
336 gl_shader_stage stage,
337 const VkSpecializationInfo *spec_info,
338 const VkPipelineCreateFlags flags,
339 const struct radv_pipeline_layout *layout,
340 unsigned subgroup_size, unsigned ballot_bit_size)
341 {
342 nir_shader *nir;
343 const nir_shader_compiler_options *nir_options =
344 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
345
346 if (module->nir) {
347 /* Some things such as our meta clear/blit code will give us a NIR
348 * shader directly. In that case, we just ignore the SPIR-V entirely
349 * and just use the NIR shader */
350 nir = module->nir;
351 nir->options = nir_options;
352 nir_validate_shader(nir, "in internal shader");
353
354 assert(exec_list_length(&nir->functions) == 1);
355 } else {
356 uint32_t *spirv = (uint32_t *) module->data;
357 assert(module->size % 4 == 0);
358
359 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
360 radv_print_spirv(module->data, module->size, stderr);
361
362 uint32_t num_spec_entries = 0;
363 struct nir_spirv_specialization *spec_entries = NULL;
364 if (spec_info && spec_info->mapEntryCount > 0) {
365 num_spec_entries = spec_info->mapEntryCount;
366 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
367 for (uint32_t i = 0; i < num_spec_entries; i++) {
368 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
369 const void *data = spec_info->pData + entry.offset;
370 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
371
372 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
373 switch (entry.size) {
374 case 8:
375 spec_entries[i].value.u64 = *(const uint64_t *)data;
376 break;
377 case 4:
378 spec_entries[i].value.u32 = *(const uint32_t *)data;
379 break;
380 case 2:
381 spec_entries[i].value.u16 = *(const uint16_t *)data;
382 break;
383 case 1:
384 spec_entries[i].value.u8 = *(const uint8_t *)data;
385 break;
386 default:
387 assert(!"Invalid spec constant size");
388 break;
389 }
390 }
391 }
392
393 struct radv_spirv_debug_data spirv_debug_data = {
394 .device = device,
395 .module = module,
396 };
397 const struct spirv_to_nir_options spirv_options = {
398 .lower_ubo_ssbo_access_to_offsets = true,
399 .caps = {
400 .amd_fragment_mask = true,
401 .amd_gcn_shader = true,
402 .amd_image_gather_bias_lod = true,
403 .amd_image_read_write_lod = true,
404 .amd_shader_ballot = true,
405 .amd_shader_explicit_vertex_parameter = true,
406 .amd_trinary_minmax = true,
407 .demote_to_helper_invocation = true,
408 .derivative_group = true,
409 .descriptor_array_dynamic_indexing = true,
410 .descriptor_array_non_uniform_indexing = true,
411 .descriptor_indexing = true,
412 .device_group = true,
413 .draw_parameters = true,
414 .float_controls = true,
415 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
416 .float32_atomic_add = true,
417 .float64 = true,
418 .geometry_streams = true,
419 .image_ms_array = true,
420 .image_read_without_format = true,
421 .image_write_without_format = true,
422 .int8 = true,
423 .int16 = true,
424 .int64 = true,
425 .int64_atomics = true,
426 .min_lod = true,
427 .multiview = true,
428 .physical_storage_buffer_address = true,
429 .post_depth_coverage = true,
430 .runtime_descriptor_array = true,
431 .shader_clock = true,
432 .shader_viewport_index_layer = true,
433 .stencil_export = true,
434 .storage_8bit = true,
435 .storage_16bit = true,
436 .storage_image_ms = true,
437 .subgroup_arithmetic = true,
438 .subgroup_ballot = true,
439 .subgroup_basic = true,
440 .subgroup_quad = true,
441 .subgroup_shuffle = true,
442 .subgroup_vote = true,
443 .tessellation = true,
444 .transform_feedback = true,
445 .variable_pointers = true,
446 .vk_memory_model = true,
447 .vk_memory_model_device_scope = true,
448 },
449 .ubo_addr_format = nir_address_format_32bit_index_offset,
450 .ssbo_addr_format = nir_address_format_32bit_index_offset,
451 .phys_ssbo_addr_format = nir_address_format_64bit_global,
452 .push_const_addr_format = nir_address_format_logical,
453 .shared_addr_format = nir_address_format_32bit_offset,
454 .frag_coord_is_sysval = true,
455 .debug = {
456 .func = radv_spirv_nir_debug,
457 .private_data = &spirv_debug_data,
458 },
459 };
460 nir = spirv_to_nir(spirv, module->size / 4,
461 spec_entries, num_spec_entries,
462 stage, entrypoint_name,
463 &spirv_options, nir_options);
464 assert(nir->info.stage == stage);
465 nir_validate_shader(nir, "after spirv_to_nir");
466
467 free(spec_entries);
468
469 /* We have to lower away local constant initializers right before we
470 * inline functions. That way they get properly initialized at the top
471 * of the function and not at the top of its caller.
472 */
473 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
474 NIR_PASS_V(nir, nir_lower_returns);
475 NIR_PASS_V(nir, nir_inline_functions);
476 NIR_PASS_V(nir, nir_copy_prop);
477 NIR_PASS_V(nir, nir_opt_deref);
478
479 /* Pick off the single entrypoint that we want */
480 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
481 if (func->is_entrypoint)
482 func->name = ralloc_strdup(func, "main");
483 else
484 exec_node_remove(&func->node);
485 }
486 assert(exec_list_length(&nir->functions) == 1);
487
488 /* Make sure we lower constant initializers on output variables so that
489 * nir_remove_dead_variables below sees the corresponding stores
490 */
491 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
492
493 /* Now that we've deleted all but the main function, we can go ahead and
494 * lower the rest of the constant initializers.
495 */
496 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
497
498 /* Split member structs. We do this before lower_io_to_temporaries so that
499 * it doesn't lower system values to temporaries by accident.
500 */
501 NIR_PASS_V(nir, nir_split_var_copies);
502 NIR_PASS_V(nir, nir_split_per_member_structs);
503
504 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
505 !radv_use_llvm_for_stage(device, nir->info.stage))
506 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
507 if (nir->info.stage == MESA_SHADER_FRAGMENT)
508 NIR_PASS_V(nir, nir_lower_input_attachments, true);
509
510 NIR_PASS_V(nir, nir_remove_dead_variables,
511 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
512 NULL);
513
514 NIR_PASS_V(nir, nir_propagate_invariant);
515
516 NIR_PASS_V(nir, nir_lower_system_values);
517 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
518
519 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
520 NIR_PASS_V(nir, nir_lower_discard_to_demote);
521
522 nir_lower_doubles_options lower_doubles =
523 nir->options->lower_doubles_options;
524
525 if (device->physical_device->rad_info.chip_class == GFX6) {
526 /* GFX6 doesn't support v_floor_f64 and the precision
527 * of v_fract_f64 which is used to implement 64-bit
528 * floor is less than what Vulkan requires.
529 */
530 lower_doubles |= nir_lower_dfloor;
531 }
532
533 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
534 }
535
536 /* Vulkan uses the separate-shader linking model */
537 nir->info.separate_shader = true;
538
539 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
540
541 if (nir->info.stage == MESA_SHADER_GEOMETRY)
542 nir_lower_gs_intrinsics(nir, true);
543
544 static const nir_lower_tex_options tex_options = {
545 .lower_txp = ~0,
546 .lower_tg4_offsets = true,
547 };
548
549 nir_lower_tex(nir, &tex_options);
550
551 nir_lower_vars_to_ssa(nir);
552
553 if (nir->info.stage == MESA_SHADER_VERTEX ||
554 nir->info.stage == MESA_SHADER_GEOMETRY ||
555 nir->info.stage == MESA_SHADER_FRAGMENT) {
556 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
557 nir_shader_get_entrypoint(nir), true, true);
558 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
559 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
560 nir_shader_get_entrypoint(nir), true, false);
561 }
562
563 nir_split_var_copies(nir);
564
565 nir_lower_global_vars_to_local(nir);
566 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
567 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
568 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
569 .subgroup_size = subgroup_size,
570 .ballot_bit_size = ballot_bit_size,
571 .lower_to_scalar = 1,
572 .lower_subgroup_masks = 1,
573 .lower_shuffle = 1,
574 .lower_shuffle_to_32bit = 1,
575 .lower_vote_eq_to_ballot = 1,
576 .lower_quad_broadcast_dynamic = 1,
577 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
578 .lower_shuffle_to_swizzle_amd = 1,
579 });
580
581 nir_lower_load_const_to_scalar(nir);
582
583 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
584 radv_optimize_nir(nir, false, true);
585
586 /* call radv_nir_lower_ycbcr_textures() late as there might still be
587 * tex with undef texture/sampler before first optimization */
588 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
589
590 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
591 * to remove any copies introduced by nir_opt_find_array_copies().
592 */
593 nir_lower_var_copies(nir);
594
595 /* Lower deref operations for compute shared memory. */
596 if (nir->info.stage == MESA_SHADER_COMPUTE) {
597 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
598 nir_var_mem_shared, shared_var_info);
599 NIR_PASS_V(nir, nir_lower_explicit_io,
600 nir_var_mem_shared, nir_address_format_32bit_offset);
601 }
602
603 /* Lower large variables that are always constant with load_constant
604 * intrinsics, which get turned into PC-relative loads from a data
605 * section next to the shader.
606 */
607 NIR_PASS_V(nir, nir_opt_large_constants,
608 glsl_get_natural_size_align_bytes, 16);
609
610 /* Indirect lowering must be called after the radv_optimize_nir() loop
611 * has been called at least once. Otherwise indirect lowering can
612 * bloat the instruction count of the loop and cause it to be
613 * considered too large for unrolling.
614 */
615 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
616 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
617
618 return nir;
619 }
620
621 static int
622 type_size_vec4(const struct glsl_type *type, bool bindless)
623 {
624 return glsl_count_attribute_slots(type, false);
625 }
626
627 static nir_variable *
628 find_layer_in_var(nir_shader *nir)
629 {
630 nir_variable *var =
631 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
632 if (var != NULL)
633 return var;
634
635 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
636 var->data.location = VARYING_SLOT_LAYER;
637 var->data.interpolation = INTERP_MODE_FLAT;
638 return var;
639 }
640
641 /* We use layered rendering to implement multiview, which means we need to map
642 * view_index to gl_Layer. The attachment lowering also uses needs to know the
643 * layer so that it can sample from the correct layer. The code generates a
644 * load from the layer_id sysval, but since we don't have a way to get at this
645 * information from the fragment shader, we also need to lower this to the
646 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
647 * slot, before lowering io, so that nir_assign_var_locations() will give the
648 * LAYER varying the correct driver_location.
649 */
650
651 static bool
652 lower_view_index(nir_shader *nir)
653 {
654 bool progress = false;
655 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
656 nir_builder b;
657 nir_builder_init(&b, entry);
658
659 nir_variable *layer = NULL;
660 nir_foreach_block(block, entry) {
661 nir_foreach_instr_safe(instr, block) {
662 if (instr->type != nir_instr_type_intrinsic)
663 continue;
664
665 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
666 if (load->intrinsic != nir_intrinsic_load_view_index &&
667 load->intrinsic != nir_intrinsic_load_layer_id)
668 continue;
669
670 if (!layer)
671 layer = find_layer_in_var(nir);
672
673 b.cursor = nir_before_instr(instr);
674 nir_ssa_def *def = nir_load_var(&b, layer);
675 nir_ssa_def_rewrite_uses(&load->dest.ssa,
676 nir_src_for_ssa(def));
677
678 nir_instr_remove(instr);
679 progress = true;
680 }
681 }
682
683 return progress;
684 }
685
686 void
687 radv_lower_fs_io(nir_shader *nir)
688 {
689 NIR_PASS_V(nir, lower_view_index);
690 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
691 MESA_SHADER_FRAGMENT);
692
693 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
694
695 /* This pass needs actual constants */
696 nir_opt_constant_folding(nir);
697
698 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
699 }
700
701
702 static void *
703 radv_alloc_shader_memory(struct radv_device *device,
704 struct radv_shader_variant *shader)
705 {
706 mtx_lock(&device->shader_slab_mutex);
707 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
708 uint64_t offset = 0;
709 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
710 if (s->bo_offset - offset >= shader->code_size) {
711 shader->bo = slab->bo;
712 shader->bo_offset = offset;
713 list_addtail(&shader->slab_list, &s->slab_list);
714 mtx_unlock(&device->shader_slab_mutex);
715 return slab->ptr + offset;
716 }
717 offset = align_u64(s->bo_offset + s->code_size, 256);
718 }
719 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
720 shader->bo = slab->bo;
721 shader->bo_offset = offset;
722 list_addtail(&shader->slab_list, &slab->shaders);
723 mtx_unlock(&device->shader_slab_mutex);
724 return slab->ptr + offset;
725 }
726 }
727
728 mtx_unlock(&device->shader_slab_mutex);
729 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
730
731 slab->size = MAX2(256 * 1024, shader->code_size);
732 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
733 RADEON_DOMAIN_VRAM,
734 RADEON_FLAG_NO_INTERPROCESS_SHARING |
735 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
736 0 : RADEON_FLAG_READ_ONLY),
737 RADV_BO_PRIORITY_SHADER);
738 if (!slab->bo) {
739 free(slab);
740 return NULL;
741 }
742
743 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
744 if (!slab->ptr) {
745 device->ws->buffer_destroy(slab->bo);
746 free(slab);
747 return NULL;
748 }
749
750 list_inithead(&slab->shaders);
751
752 mtx_lock(&device->shader_slab_mutex);
753 list_add(&slab->slabs, &device->shader_slabs);
754
755 shader->bo = slab->bo;
756 shader->bo_offset = 0;
757 list_add(&shader->slab_list, &slab->shaders);
758 mtx_unlock(&device->shader_slab_mutex);
759 return slab->ptr;
760 }
761
762 void
763 radv_destroy_shader_slabs(struct radv_device *device)
764 {
765 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
766 device->ws->buffer_destroy(slab->bo);
767 free(slab);
768 }
769 mtx_destroy(&device->shader_slab_mutex);
770 }
771
772 /* For the UMR disassembler. */
773 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
774 #define DEBUGGER_NUM_MARKERS 5
775
776 static unsigned
777 radv_get_shader_binary_size(size_t code_size)
778 {
779 return code_size + DEBUGGER_NUM_MARKERS * 4;
780 }
781
782 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
783 const struct ac_shader_config *config_in,
784 const struct radv_shader_info *info,
785 gl_shader_stage stage,
786 struct ac_shader_config *config_out)
787 {
788 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
789 unsigned vgpr_comp_cnt = 0;
790 unsigned num_input_vgprs = info->num_input_vgprs;
791
792 if (stage == MESA_SHADER_FRAGMENT) {
793 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
794 }
795
796 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
797 /* +3 for scratch wave offset and VCC */
798 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
799 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
800 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
801 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
802 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
803 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
804
805 *config_out = *config_in;
806 config_out->num_vgprs = num_vgprs;
807 config_out->num_sgprs = num_sgprs;
808 config_out->num_shared_vgprs = num_shared_vgprs;
809
810 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
811 S_00B12C_SCRATCH_EN(scratch_enabled);
812
813 if (!pdevice->use_ngg_streamout) {
814 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
815 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
816 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
817 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
818 S_00B12C_SO_EN(!!info->so.num_outputs);
819 }
820
821 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
822 (info->wave_size == 32 ? 8 : 4)) |
823 S_00B848_DX10_CLAMP(1) |
824 S_00B848_FLOAT_MODE(config_out->float_mode);
825
826 if (pdevice->rad_info.chip_class >= GFX10) {
827 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
828 } else {
829 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
830 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
831 }
832
833 switch (stage) {
834 case MESA_SHADER_TESS_EVAL:
835 if (info->is_ngg) {
836 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
837 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
838 } else if (info->tes.as_es) {
839 assert(pdevice->rad_info.chip_class <= GFX8);
840 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
841
842 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
843 } else {
844 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
845 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
846
847 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
848 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
849 }
850 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
851 break;
852 case MESA_SHADER_TESS_CTRL:
853 if (pdevice->rad_info.chip_class >= GFX9) {
854 /* We need at least 2 components for LS.
855 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
856 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
857 */
858 if (pdevice->rad_info.chip_class >= GFX10) {
859 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
860 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
861 } else {
862 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
863 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
864 }
865 } else {
866 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
867 }
868 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
869 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
870 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
871 break;
872 case MESA_SHADER_VERTEX:
873 if (info->is_ngg) {
874 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
875 } else if (info->vs.as_ls) {
876 assert(pdevice->rad_info.chip_class <= GFX8);
877 /* We need at least 2 components for LS.
878 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
879 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
880 */
881 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
882 } else if (info->vs.as_es) {
883 assert(pdevice->rad_info.chip_class <= GFX8);
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
885 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
886 } else {
887 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
888 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
889 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
890 */
891 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
892 vgpr_comp_cnt = 3;
893 } else if (info->vs.export_prim_id) {
894 vgpr_comp_cnt = 2;
895 } else if (info->vs.needs_instance_id) {
896 vgpr_comp_cnt = 1;
897 } else {
898 vgpr_comp_cnt = 0;
899 }
900
901 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
902 }
903 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
904 break;
905 case MESA_SHADER_FRAGMENT:
906 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
907 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
908 break;
909 case MESA_SHADER_GEOMETRY:
910 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
911 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
912 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
913 break;
914 case MESA_SHADER_COMPUTE:
915 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
916 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
917 config_out->rsrc2 |=
918 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
919 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
920 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
921 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
922 info->cs.uses_thread_id[1] ? 1 : 0) |
923 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
924 S_00B84C_LDS_SIZE(config_in->lds_size);
925 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
926
927 break;
928 default:
929 unreachable("unsupported shader type");
930 break;
931 }
932
933 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
934 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
935 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
936 gl_shader_stage es_stage = stage;
937 if (stage == MESA_SHADER_GEOMETRY)
938 es_stage = info->gs.es_type;
939
940 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
941 if (es_stage == MESA_SHADER_VERTEX) {
942 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
943 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
944 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
945 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
946 } else
947 unreachable("Unexpected ES shader stage");
948
949 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
950 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
951 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
952 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
953 } else if (info->uses_prim_id) {
954 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
955 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
956 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
957 } else {
958 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
959 }
960
961 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
962 S_00B228_WGP_MODE(1);
963 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
964 S_00B22C_LDS_SIZE(config_in->lds_size) |
965 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
966 } else if (pdevice->rad_info.chip_class >= GFX9 &&
967 stage == MESA_SHADER_GEOMETRY) {
968 unsigned es_type = info->gs.es_type;
969 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
970
971 if (es_type == MESA_SHADER_VERTEX) {
972 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
973 if (info->vs.needs_instance_id) {
974 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
975 } else {
976 es_vgpr_comp_cnt = 0;
977 }
978 } else if (es_type == MESA_SHADER_TESS_EVAL) {
979 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
980 } else {
981 unreachable("invalid shader ES type");
982 }
983
984 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
985 * VGPR[0:4] are always loaded.
986 */
987 if (info->uses_invocation_id) {
988 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
989 } else if (info->uses_prim_id) {
990 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
991 } else if (info->gs.vertices_in >= 3) {
992 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
993 } else {
994 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
995 }
996
997 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
998 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
999 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
1000 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1001 stage == MESA_SHADER_TESS_CTRL) {
1002 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
1003 } else {
1004 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
1005 }
1006 }
1007
1008 struct radv_shader_variant *
1009 radv_shader_variant_create(struct radv_device *device,
1010 const struct radv_shader_binary *binary,
1011 bool keep_shader_info)
1012 {
1013 struct ac_shader_config config = {0};
1014 struct ac_rtld_binary rtld_binary = {0};
1015 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
1016 if (!variant)
1017 return NULL;
1018
1019 variant->ref_count = 1;
1020
1021 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1022 struct ac_rtld_symbol lds_symbols[2];
1023 unsigned num_lds_symbols = 0;
1024 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
1025 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
1026
1027 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1028 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1029 !binary->is_gs_copy_shader) {
1030 /* We add this symbol even on LLVM <= 8 to ensure that
1031 * shader->config.lds_size is set correctly below.
1032 */
1033 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1034 sym->name = "esgs_ring";
1035 sym->size = binary->info.ngg_info.esgs_ring_size;
1036 sym->align = 64 * 1024;
1037 }
1038
1039 if (binary->info.is_ngg &&
1040 binary->stage == MESA_SHADER_GEOMETRY) {
1041 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1042 sym->name = "ngg_emit";
1043 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1044 sym->align = 4;
1045 }
1046
1047 struct ac_rtld_open_info open_info = {
1048 .info = &device->physical_device->rad_info,
1049 .shader_type = binary->stage,
1050 .wave_size = binary->info.wave_size,
1051 .num_parts = 1,
1052 .elf_ptrs = &elf_data,
1053 .elf_sizes = &elf_size,
1054 .num_shared_lds_symbols = num_lds_symbols,
1055 .shared_lds_symbols = lds_symbols,
1056 };
1057
1058 if (!ac_rtld_open(&rtld_binary, open_info)) {
1059 free(variant);
1060 return NULL;
1061 }
1062
1063 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1064 &rtld_binary, &config)) {
1065 ac_rtld_close(&rtld_binary);
1066 free(variant);
1067 return NULL;
1068 }
1069
1070 if (rtld_binary.lds_size > 0) {
1071 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1072 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1073 }
1074
1075 variant->code_size = rtld_binary.rx_size;
1076 variant->exec_size = rtld_binary.exec_size;
1077 } else {
1078 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1079 config = ((struct radv_shader_binary_legacy *)binary)->config;
1080 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1081 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1082 }
1083
1084 variant->info = binary->info;
1085 radv_postprocess_config(device->physical_device, &config, &binary->info,
1086 binary->stage, &variant->config);
1087
1088 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1089 if (!dest_ptr) {
1090 if (binary->type == RADV_BINARY_TYPE_RTLD)
1091 ac_rtld_close(&rtld_binary);
1092 free(variant);
1093 return NULL;
1094 }
1095
1096 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1097 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1098 struct ac_rtld_upload_info info = {
1099 .binary = &rtld_binary,
1100 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1101 .rx_ptr = dest_ptr,
1102 };
1103
1104 if (!ac_rtld_upload(&info)) {
1105 radv_shader_variant_destroy(device, variant);
1106 ac_rtld_close(&rtld_binary);
1107 return NULL;
1108 }
1109
1110 if (keep_shader_info ||
1111 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1112 const char *disasm_data;
1113 size_t disasm_size;
1114 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1115 radv_shader_variant_destroy(device, variant);
1116 ac_rtld_close(&rtld_binary);
1117 return NULL;
1118 }
1119
1120 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1121 variant->disasm_string = malloc(disasm_size + 1);
1122 memcpy(variant->disasm_string, disasm_data, disasm_size);
1123 variant->disasm_string[disasm_size] = 0;
1124 }
1125
1126 ac_rtld_close(&rtld_binary);
1127 } else {
1128 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1129 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1130
1131 /* Add end-of-code markers for the UMR disassembler. */
1132 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1133 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1134 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1135
1136 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1137 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1138
1139 if (bin->stats_size) {
1140 variant->statistics = calloc(bin->stats_size, 1);
1141 memcpy(variant->statistics, bin->data, bin->stats_size);
1142 }
1143 }
1144 return variant;
1145 }
1146
1147 static char *
1148 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1149 int shader_count)
1150 {
1151 char *data = NULL;
1152 char *ret = NULL;
1153 size_t size = 0;
1154 FILE *f = open_memstream(&data, &size);
1155 if (f) {
1156 for (int i = 0; i < shader_count; ++i)
1157 nir_print_shader(shaders[i], f);
1158 fclose(f);
1159 }
1160
1161 ret = malloc(size + 1);
1162 if (ret) {
1163 memcpy(ret, data, size);
1164 ret[size] = 0;
1165 }
1166 free(data);
1167 return ret;
1168 }
1169
1170 static struct radv_shader_variant *
1171 shader_variant_compile(struct radv_device *device,
1172 struct radv_shader_module *module,
1173 struct nir_shader * const *shaders,
1174 int shader_count,
1175 gl_shader_stage stage,
1176 struct radv_shader_info *info,
1177 struct radv_nir_compiler_options *options,
1178 bool gs_copy_shader,
1179 bool keep_shader_info,
1180 bool keep_statistic_info,
1181 struct radv_shader_binary **binary_out)
1182 {
1183 enum radeon_family chip_family = device->physical_device->rad_info.family;
1184 struct radv_shader_binary *binary = NULL;
1185
1186 options->family = chip_family;
1187 options->chip_class = device->physical_device->rad_info.chip_class;
1188 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1189 options->dump_preoptir = options->dump_shader &&
1190 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1191 options->record_ir = keep_shader_info;
1192 options->record_stats = keep_statistic_info;
1193 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1194 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1195 options->address32_hi = device->physical_device->rad_info.address32_hi;
1196 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1197 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1198 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1199
1200 struct radv_shader_args args = {};
1201 args.options = options;
1202 args.shader_info = info;
1203 args.is_gs_copy_shader = gs_copy_shader;
1204 radv_declare_shader_args(&args,
1205 gs_copy_shader ? MESA_SHADER_VERTEX
1206 : shaders[shader_count - 1]->info.stage,
1207 shader_count >= 2,
1208 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1209 : MESA_SHADER_VERTEX);
1210
1211 if (radv_use_llvm_for_stage(device, stage) ||
1212 options->dump_shader || options->record_ir)
1213 ac_init_llvm_once();
1214
1215 if (radv_use_llvm_for_stage(device, stage)) {
1216 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1217 } else {
1218 aco_compile_shader(shader_count, shaders, &binary, &args);
1219 }
1220
1221 binary->info = *info;
1222
1223 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1224 keep_shader_info);
1225 if (!variant) {
1226 free(binary);
1227 return NULL;
1228 }
1229
1230 if (options->dump_shader) {
1231 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1232 for (int i = 1; i < shader_count; ++i)
1233 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1234
1235 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1236 }
1237
1238
1239 if (keep_shader_info) {
1240 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1241 if (!gs_copy_shader && !module->nir) {
1242 variant->spirv = malloc(module->size);
1243 if (!variant->spirv) {
1244 free(variant);
1245 free(binary);
1246 return NULL;
1247 }
1248
1249 memcpy(variant->spirv, module->data, module->size);
1250 variant->spirv_size = module->size;
1251 }
1252 }
1253
1254 if (binary_out)
1255 *binary_out = binary;
1256 else
1257 free(binary);
1258
1259 return variant;
1260 }
1261
1262 struct radv_shader_variant *
1263 radv_shader_variant_compile(struct radv_device *device,
1264 struct radv_shader_module *module,
1265 struct nir_shader *const *shaders,
1266 int shader_count,
1267 struct radv_pipeline_layout *layout,
1268 const struct radv_shader_variant_key *key,
1269 struct radv_shader_info *info,
1270 bool keep_shader_info, bool keep_statistic_info,
1271 struct radv_shader_binary **binary_out)
1272 {
1273 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1274 struct radv_nir_compiler_options options = {0};
1275
1276 options.layout = layout;
1277 if (key)
1278 options.key = *key;
1279
1280 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1281 options.robust_buffer_access = device->robust_buffer_access;
1282
1283 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1284 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1285 }
1286
1287 struct radv_shader_variant *
1288 radv_create_gs_copy_shader(struct radv_device *device,
1289 struct nir_shader *shader,
1290 struct radv_shader_info *info,
1291 struct radv_shader_binary **binary_out,
1292 bool keep_shader_info, bool keep_statistic_info,
1293 bool multiview)
1294 {
1295 struct radv_nir_compiler_options options = {0};
1296 gl_shader_stage stage = MESA_SHADER_VERTEX;
1297
1298 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1299 options.key.has_multiview_view_index = multiview;
1300
1301 return shader_variant_compile(device, NULL, &shader, 1, stage,
1302 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1303 }
1304
1305 void
1306 radv_shader_variant_destroy(struct radv_device *device,
1307 struct radv_shader_variant *variant)
1308 {
1309 if (!p_atomic_dec_zero(&variant->ref_count))
1310 return;
1311
1312 mtx_lock(&device->shader_slab_mutex);
1313 list_del(&variant->slab_list);
1314 mtx_unlock(&device->shader_slab_mutex);
1315
1316 free(variant->spirv);
1317 free(variant->nir_string);
1318 free(variant->disasm_string);
1319 free(variant->ir_string);
1320 free(variant->statistics);
1321 free(variant);
1322 }
1323
1324 const char *
1325 radv_get_shader_name(struct radv_shader_info *info,
1326 gl_shader_stage stage)
1327 {
1328 switch (stage) {
1329 case MESA_SHADER_VERTEX:
1330 if (info->vs.as_ls)
1331 return "Vertex Shader as LS";
1332 else if (info->vs.as_es)
1333 return "Vertex Shader as ES";
1334 else if (info->is_ngg)
1335 return "Vertex Shader as ESGS";
1336 else
1337 return "Vertex Shader as VS";
1338 case MESA_SHADER_TESS_CTRL:
1339 return "Tessellation Control Shader";
1340 case MESA_SHADER_TESS_EVAL:
1341 if (info->tes.as_es)
1342 return "Tessellation Evaluation Shader as ES";
1343 else if (info->is_ngg)
1344 return "Tessellation Evaluation Shader as ESGS";
1345 else
1346 return "Tessellation Evaluation Shader as VS";
1347 case MESA_SHADER_GEOMETRY:
1348 return "Geometry Shader";
1349 case MESA_SHADER_FRAGMENT:
1350 return "Pixel Shader";
1351 case MESA_SHADER_COMPUTE:
1352 return "Compute Shader";
1353 default:
1354 return "Unknown shader";
1355 };
1356 }
1357
1358 unsigned
1359 radv_get_max_workgroup_size(enum chip_class chip_class,
1360 gl_shader_stage stage,
1361 const unsigned *sizes)
1362 {
1363 switch (stage) {
1364 case MESA_SHADER_TESS_CTRL:
1365 return chip_class >= GFX7 ? 128 : 64;
1366 case MESA_SHADER_GEOMETRY:
1367 return chip_class >= GFX9 ? 128 : 64;
1368 case MESA_SHADER_COMPUTE:
1369 break;
1370 default:
1371 return 0;
1372 }
1373
1374 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1375 return max_workgroup_size;
1376 }
1377
1378 unsigned
1379 radv_get_max_waves(struct radv_device *device,
1380 struct radv_shader_variant *variant,
1381 gl_shader_stage stage)
1382 {
1383 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1384 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1385 uint8_t wave_size = variant->info.wave_size;
1386 struct ac_shader_config *conf = &variant->config;
1387 unsigned max_simd_waves;
1388 unsigned lds_per_wave = 0;
1389
1390 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1391
1392 if (stage == MESA_SHADER_FRAGMENT) {
1393 lds_per_wave = conf->lds_size * lds_increment +
1394 align(variant->info.ps.num_interp * 48,
1395 lds_increment);
1396 } else if (stage == MESA_SHADER_COMPUTE) {
1397 unsigned max_workgroup_size =
1398 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1399 lds_per_wave = (conf->lds_size * lds_increment) /
1400 DIV_ROUND_UP(max_workgroup_size, wave_size);
1401 }
1402
1403 if (conf->num_sgprs) {
1404 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1405 max_simd_waves =
1406 MIN2(max_simd_waves,
1407 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1408 sgprs);
1409 }
1410
1411 if (conf->num_vgprs) {
1412 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1413 max_simd_waves =
1414 MIN2(max_simd_waves,
1415 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1416 }
1417
1418 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1419 if (lds_per_wave)
1420 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1421
1422 return max_simd_waves;
1423 }
1424
1425 static void
1426 generate_shader_stats(struct radv_device *device,
1427 struct radv_shader_variant *variant,
1428 gl_shader_stage stage,
1429 struct _mesa_string_buffer *buf)
1430 {
1431 struct ac_shader_config *conf = &variant->config;
1432 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1433
1434 if (stage == MESA_SHADER_FRAGMENT) {
1435 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1436 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1437 "SPI_PS_INPUT_ENA = 0x%04x\n",
1438 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1439 }
1440
1441 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1442 "SGPRS: %d\n"
1443 "VGPRS: %d\n"
1444 "Spilled SGPRs: %d\n"
1445 "Spilled VGPRs: %d\n"
1446 "PrivMem VGPRS: %d\n"
1447 "Code Size: %d bytes\n"
1448 "LDS: %d blocks\n"
1449 "Scratch: %d bytes per wave\n"
1450 "Max Waves: %d\n",
1451 conf->num_sgprs, conf->num_vgprs,
1452 conf->spilled_sgprs, conf->spilled_vgprs,
1453 variant->info.private_mem_vgprs, variant->exec_size,
1454 conf->lds_size, conf->scratch_bytes_per_wave,
1455 max_simd_waves);
1456
1457 if (variant->statistics) {
1458 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1459 for (unsigned i = 0; i < variant->statistics->count; i++) {
1460 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1461 uint32_t value = variant->statistics->values[i];
1462 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1463 }
1464 }
1465
1466 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1467 }
1468
1469 void
1470 radv_shader_dump_stats(struct radv_device *device,
1471 struct radv_shader_variant *variant,
1472 gl_shader_stage stage,
1473 FILE *file)
1474 {
1475 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1476
1477 generate_shader_stats(device, variant, stage, buf);
1478
1479 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1480 fprintf(file, "%s", buf->buf);
1481
1482 _mesa_string_buffer_destroy(buf);
1483 }
1484
1485 VkResult
1486 radv_GetShaderInfoAMD(VkDevice _device,
1487 VkPipeline _pipeline,
1488 VkShaderStageFlagBits shaderStage,
1489 VkShaderInfoTypeAMD infoType,
1490 size_t* pInfoSize,
1491 void* pInfo)
1492 {
1493 RADV_FROM_HANDLE(radv_device, device, _device);
1494 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1495 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1496 struct radv_shader_variant *variant = pipeline->shaders[stage];
1497 struct _mesa_string_buffer *buf;
1498 VkResult result = VK_SUCCESS;
1499
1500 /* Spec doesn't indicate what to do if the stage is invalid, so just
1501 * return no info for this. */
1502 if (!variant)
1503 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1504
1505 switch (infoType) {
1506 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1507 if (!pInfo) {
1508 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1509 } else {
1510 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1511 struct ac_shader_config *conf = &variant->config;
1512
1513 VkShaderStatisticsInfoAMD statistics = {};
1514 statistics.shaderStageMask = shaderStage;
1515 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1516 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1517 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1518
1519 if (stage == MESA_SHADER_COMPUTE) {
1520 unsigned *local_size = variant->info.cs.block_size;
1521 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1522
1523 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1524 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1525
1526 statistics.computeWorkGroupSize[0] = local_size[0];
1527 statistics.computeWorkGroupSize[1] = local_size[1];
1528 statistics.computeWorkGroupSize[2] = local_size[2];
1529 } else {
1530 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1531 }
1532
1533 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1534 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1535 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1536 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1537 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1538
1539 size_t size = *pInfoSize;
1540 *pInfoSize = sizeof(statistics);
1541
1542 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1543
1544 if (size < *pInfoSize)
1545 result = VK_INCOMPLETE;
1546 }
1547
1548 break;
1549 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1550 buf = _mesa_string_buffer_create(NULL, 1024);
1551
1552 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1553 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1554 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1555 generate_shader_stats(device, variant, stage, buf);
1556
1557 /* Need to include the null terminator. */
1558 size_t length = buf->length + 1;
1559
1560 if (!pInfo) {
1561 *pInfoSize = length;
1562 } else {
1563 size_t size = *pInfoSize;
1564 *pInfoSize = length;
1565
1566 memcpy(pInfo, buf->buf, MIN2(size, length));
1567
1568 if (size < length)
1569 result = VK_INCOMPLETE;
1570 }
1571
1572 _mesa_string_buffer_destroy(buf);
1573 break;
1574 default:
1575 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1576 result = VK_ERROR_FEATURE_NOT_PRESENT;
1577 break;
1578 }
1579
1580 return result;
1581 }