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radv/aco,aco: implement GS on GFX9+
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 unsigned shader_io_get_unique_index(gl_varying_slot slot)
156 {
157 /* handle patch indices separate */
158 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
159 return 0;
160 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
161 return 1;
162 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
163 return 2 + (slot - VARYING_SLOT_PATCH0);
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 if (slot == VARYING_SLOT_CLIP_DIST1)
171 return 3;
172 /* 3 is reserved for clip dist as well */
173 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
174 return 4 + (slot - VARYING_SLOT_VAR0);
175 unreachable("illegal slot in get unique index\n");
176 }
177
178 VkResult radv_CreateShaderModule(
179 VkDevice _device,
180 const VkShaderModuleCreateInfo* pCreateInfo,
181 const VkAllocationCallbacks* pAllocator,
182 VkShaderModule* pShaderModule)
183 {
184 RADV_FROM_HANDLE(radv_device, device, _device);
185 struct radv_shader_module *module;
186
187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
188 assert(pCreateInfo->flags == 0);
189
190 module = vk_alloc2(&device->alloc, pAllocator,
191 sizeof(*module) + pCreateInfo->codeSize, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (module == NULL)
194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 module->nir = NULL;
197 module->size = pCreateInfo->codeSize;
198 memcpy(module->data, pCreateInfo->pCode, module->size);
199
200 _mesa_sha1_compute(module->data, module->size, module->sha1);
201
202 *pShaderModule = radv_shader_module_to_handle(module);
203
204 return VK_SUCCESS;
205 }
206
207 void radv_DestroyShaderModule(
208 VkDevice _device,
209 VkShaderModule _module,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 RADV_FROM_HANDLE(radv_device, device, _device);
213 RADV_FROM_HANDLE(radv_shader_module, module, _module);
214
215 if (!module)
216 return;
217
218 vk_free2(&device->alloc, pAllocator, module);
219 }
220
221 void
222 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
223 bool allow_copies)
224 {
225 bool progress;
226 unsigned lower_flrp =
227 (shader->options->lower_flrp16 ? 16 : 0) |
228 (shader->options->lower_flrp32 ? 32 : 0) |
229 (shader->options->lower_flrp64 ? 64 : 0);
230
231 do {
232 progress = false;
233
234 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
235 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
236
237 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
238 NIR_PASS_V(shader, nir_lower_pack);
239
240 if (allow_copies) {
241 /* Only run this pass in the first call to
242 * radv_optimize_nir. Later calls assume that we've
243 * lowered away any copy_deref instructions and we
244 * don't want to introduce any more.
245 */
246 NIR_PASS(progress, shader, nir_opt_find_array_copies);
247 }
248
249 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
250 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
251 NIR_PASS(progress, shader, nir_remove_dead_variables,
252 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
253
254 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
255 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
256
257 NIR_PASS(progress, shader, nir_copy_prop);
258 NIR_PASS(progress, shader, nir_opt_remove_phis);
259 NIR_PASS(progress, shader, nir_opt_dce);
260 if (nir_opt_trivial_continues(shader)) {
261 progress = true;
262 NIR_PASS(progress, shader, nir_copy_prop);
263 NIR_PASS(progress, shader, nir_opt_remove_phis);
264 NIR_PASS(progress, shader, nir_opt_dce);
265 }
266 NIR_PASS(progress, shader, nir_opt_if, true);
267 NIR_PASS(progress, shader, nir_opt_dead_cf);
268 NIR_PASS(progress, shader, nir_opt_cse);
269 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
270 NIR_PASS(progress, shader, nir_opt_constant_folding);
271 NIR_PASS(progress, shader, nir_opt_algebraic);
272
273 if (lower_flrp != 0) {
274 bool lower_flrp_progress = false;
275 NIR_PASS(lower_flrp_progress,
276 shader,
277 nir_lower_flrp,
278 lower_flrp,
279 false /* always_precise */,
280 shader->options->lower_ffma);
281 if (lower_flrp_progress) {
282 NIR_PASS(progress, shader,
283 nir_opt_constant_folding);
284 progress = true;
285 }
286
287 /* Nothing should rematerialize any flrps, so we only
288 * need to do this lowering once.
289 */
290 lower_flrp = 0;
291 }
292
293 NIR_PASS(progress, shader, nir_opt_undef);
294 if (shader->options->max_unroll_iterations) {
295 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
296 }
297 } while (progress && !optimize_conservatively);
298
299 NIR_PASS(progress, shader, nir_opt_conditional_discard);
300 NIR_PASS(progress, shader, nir_opt_shrink_load);
301 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
302 }
303
304 static void
305 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
306 {
307 assert(glsl_type_is_vector_or_scalar(type));
308
309 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
310 unsigned length = glsl_get_vector_elements(type);
311 *size = comp_size * length,
312 *align = comp_size;
313 }
314
315 nir_shader *
316 radv_shader_compile_to_nir(struct radv_device *device,
317 struct radv_shader_module *module,
318 const char *entrypoint_name,
319 gl_shader_stage stage,
320 const VkSpecializationInfo *spec_info,
321 const VkPipelineCreateFlags flags,
322 const struct radv_pipeline_layout *layout,
323 bool use_aco)
324 {
325 nir_shader *nir;
326 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
327 &nir_options_llvm;
328 if (module->nir) {
329 /* Some things such as our meta clear/blit code will give us a NIR
330 * shader directly. In that case, we just ignore the SPIR-V entirely
331 * and just use the NIR shader */
332 nir = module->nir;
333 nir->options = nir_options;
334 nir_validate_shader(nir, "in internal shader");
335
336 assert(exec_list_length(&nir->functions) == 1);
337 } else {
338 uint32_t *spirv = (uint32_t *) module->data;
339 assert(module->size % 4 == 0);
340
341 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
342 radv_print_spirv(module->data, module->size, stderr);
343
344 uint32_t num_spec_entries = 0;
345 struct nir_spirv_specialization *spec_entries = NULL;
346 if (spec_info && spec_info->mapEntryCount > 0) {
347 num_spec_entries = spec_info->mapEntryCount;
348 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
349 for (uint32_t i = 0; i < num_spec_entries; i++) {
350 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
351 const void *data = spec_info->pData + entry.offset;
352 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
353
354 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
355 if (spec_info->dataSize == 8)
356 spec_entries[i].data64 = *(const uint64_t *)data;
357 else
358 spec_entries[i].data32 = *(const uint32_t *)data;
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_fragment_mask = true,
365 .amd_gcn_shader = true,
366 .amd_image_read_write_lod = true,
367 .amd_shader_ballot = device->physical_device->use_shader_ballot,
368 .amd_trinary_minmax = true,
369 .demote_to_helper_invocation = device->physical_device->use_aco,
370 .derivative_group = true,
371 .descriptor_array_dynamic_indexing = true,
372 .descriptor_array_non_uniform_indexing = true,
373 .descriptor_indexing = true,
374 .device_group = true,
375 .draw_parameters = true,
376 .float_controls = true,
377 .float16 = !device->physical_device->use_aco,
378 .float64 = true,
379 .geometry_streams = true,
380 .image_ms_array = true,
381 .image_read_without_format = true,
382 .image_write_without_format = true,
383 .int8 = !device->physical_device->use_aco,
384 .int16 = !device->physical_device->use_aco,
385 .int64 = true,
386 .int64_atomics = true,
387 .multiview = true,
388 .physical_storage_buffer_address = true,
389 .post_depth_coverage = true,
390 .runtime_descriptor_array = true,
391 .shader_clock = true,
392 .shader_viewport_index_layer = true,
393 .stencil_export = true,
394 .storage_8bit = !device->physical_device->use_aco,
395 .storage_16bit = !device->physical_device->use_aco,
396 .storage_image_ms = true,
397 .subgroup_arithmetic = true,
398 .subgroup_ballot = true,
399 .subgroup_basic = true,
400 .subgroup_quad = true,
401 .subgroup_shuffle = true,
402 .subgroup_vote = true,
403 .tessellation = true,
404 .transform_feedback = true,
405 .variable_pointers = true,
406 },
407 .ubo_addr_format = nir_address_format_32bit_index_offset,
408 .ssbo_addr_format = nir_address_format_32bit_index_offset,
409 .phys_ssbo_addr_format = nir_address_format_64bit_global,
410 .push_const_addr_format = nir_address_format_logical,
411 .shared_addr_format = nir_address_format_32bit_offset,
412 .frag_coord_is_sysval = true,
413 };
414 nir = spirv_to_nir(spirv, module->size / 4,
415 spec_entries, num_spec_entries,
416 stage, entrypoint_name,
417 &spirv_options, nir_options);
418 assert(nir->info.stage == stage);
419 nir_validate_shader(nir, "after spirv_to_nir");
420
421 free(spec_entries);
422
423 /* We have to lower away local constant initializers right before we
424 * inline functions. That way they get properly initialized at the top
425 * of the function and not at the top of its caller.
426 */
427 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
428 NIR_PASS_V(nir, nir_lower_returns);
429 NIR_PASS_V(nir, nir_inline_functions);
430 NIR_PASS_V(nir, nir_opt_deref);
431
432 /* Pick off the single entrypoint that we want */
433 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
434 if (func->is_entrypoint)
435 func->name = ralloc_strdup(func, "main");
436 else
437 exec_node_remove(&func->node);
438 }
439 assert(exec_list_length(&nir->functions) == 1);
440
441 /* Make sure we lower constant initializers on output variables so that
442 * nir_remove_dead_variables below sees the corresponding stores
443 */
444 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
445
446 /* Now that we've deleted all but the main function, we can go ahead and
447 * lower the rest of the constant initializers.
448 */
449 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
450
451 /* Split member structs. We do this before lower_io_to_temporaries so that
452 * it doesn't lower system values to temporaries by accident.
453 */
454 NIR_PASS_V(nir, nir_split_var_copies);
455 NIR_PASS_V(nir, nir_split_per_member_structs);
456
457 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
458 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
459 if (nir->info.stage == MESA_SHADER_FRAGMENT)
460 NIR_PASS_V(nir, nir_lower_input_attachments, true);
461
462 NIR_PASS_V(nir, nir_remove_dead_variables,
463 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
464
465 NIR_PASS_V(nir, nir_propagate_invariant);
466
467 NIR_PASS_V(nir, nir_lower_system_values);
468 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
469 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
470 }
471
472 /* Vulkan uses the separate-shader linking model */
473 nir->info.separate_shader = true;
474
475 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
476
477 if (nir->info.stage == MESA_SHADER_GEOMETRY && use_aco)
478 nir_lower_gs_intrinsics(nir, true);
479
480 static const nir_lower_tex_options tex_options = {
481 .lower_txp = ~0,
482 .lower_tg4_offsets = true,
483 };
484
485 nir_lower_tex(nir, &tex_options);
486
487 nir_lower_vars_to_ssa(nir);
488
489 if (nir->info.stage == MESA_SHADER_VERTEX ||
490 nir->info.stage == MESA_SHADER_GEOMETRY ||
491 nir->info.stage == MESA_SHADER_FRAGMENT) {
492 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
493 nir_shader_get_entrypoint(nir), true, true);
494 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
495 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
496 nir_shader_get_entrypoint(nir), true, false);
497 }
498
499 nir_split_var_copies(nir);
500
501 nir_lower_global_vars_to_local(nir);
502 nir_remove_dead_variables(nir, nir_var_function_temp);
503 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
504 .subgroup_size = 64,
505 .ballot_bit_size = 64,
506 .lower_to_scalar = 1,
507 .lower_subgroup_masks = 1,
508 .lower_shuffle = 1,
509 .lower_shuffle_to_32bit = 1,
510 .lower_vote_eq_to_ballot = 1,
511 });
512
513 nir_lower_load_const_to_scalar(nir);
514
515 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
516 radv_optimize_nir(nir, false, true);
517
518 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
519 * to remove any copies introduced by nir_opt_find_array_copies().
520 */
521 nir_lower_var_copies(nir);
522
523 /* Lower deref operations for compute shared memory. */
524 if (nir->info.stage == MESA_SHADER_COMPUTE) {
525 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
526 nir_var_mem_shared, shared_var_info);
527 NIR_PASS_V(nir, nir_lower_explicit_io,
528 nir_var_mem_shared, nir_address_format_32bit_offset);
529 }
530
531 /* Lower large variables that are always constant with load_constant
532 * intrinsics, which get turned into PC-relative loads from a data
533 * section next to the shader.
534 */
535 NIR_PASS_V(nir, nir_opt_large_constants,
536 glsl_get_natural_size_align_bytes, 16);
537
538 /* Indirect lowering must be called after the radv_optimize_nir() loop
539 * has been called at least once. Otherwise indirect lowering can
540 * bloat the instruction count of the loop and cause it to be
541 * considered too large for unrolling.
542 */
543 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
544 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
545
546 return nir;
547 }
548
549 static int
550 type_size_vec4(const struct glsl_type *type, bool bindless)
551 {
552 return glsl_count_attribute_slots(type, false);
553 }
554
555 static nir_variable *
556 find_layer_in_var(nir_shader *nir)
557 {
558 nir_foreach_variable(var, &nir->inputs) {
559 if (var->data.location == VARYING_SLOT_LAYER) {
560 return var;
561 }
562 }
563
564 nir_variable *var =
565 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
566 var->data.location = VARYING_SLOT_LAYER;
567 var->data.interpolation = INTERP_MODE_FLAT;
568 return var;
569 }
570
571 /* We use layered rendering to implement multiview, which means we need to map
572 * view_index to gl_Layer. The attachment lowering also uses needs to know the
573 * layer so that it can sample from the correct layer. The code generates a
574 * load from the layer_id sysval, but since we don't have a way to get at this
575 * information from the fragment shader, we also need to lower this to the
576 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
577 * slot, before lowering io, so that nir_assign_var_locations() will give the
578 * LAYER varying the correct driver_location.
579 */
580
581 static bool
582 lower_view_index(nir_shader *nir)
583 {
584 bool progress = false;
585 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
586 nir_builder b;
587 nir_builder_init(&b, entry);
588
589 nir_variable *layer = NULL;
590 nir_foreach_block(block, entry) {
591 nir_foreach_instr_safe(instr, block) {
592 if (instr->type != nir_instr_type_intrinsic)
593 continue;
594
595 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
596 if (load->intrinsic != nir_intrinsic_load_view_index &&
597 load->intrinsic != nir_intrinsic_load_layer_id)
598 continue;
599
600 if (!layer)
601 layer = find_layer_in_var(nir);
602
603 b.cursor = nir_before_instr(instr);
604 nir_ssa_def *def = nir_load_var(&b, layer);
605 nir_ssa_def_rewrite_uses(&load->dest.ssa,
606 nir_src_for_ssa(def));
607
608 nir_instr_remove(instr);
609 progress = true;
610 }
611 }
612
613 return progress;
614 }
615
616 void
617 radv_lower_fs_io(nir_shader *nir)
618 {
619 NIR_PASS_V(nir, lower_view_index);
620 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
621 MESA_SHADER_FRAGMENT);
622
623 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
624
625 /* This pass needs actual constants */
626 nir_opt_constant_folding(nir);
627
628 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
629 }
630
631
632 void *
633 radv_alloc_shader_memory(struct radv_device *device,
634 struct radv_shader_variant *shader)
635 {
636 mtx_lock(&device->shader_slab_mutex);
637 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
638 uint64_t offset = 0;
639 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
640 if (s->bo_offset - offset >= shader->code_size) {
641 shader->bo = slab->bo;
642 shader->bo_offset = offset;
643 list_addtail(&shader->slab_list, &s->slab_list);
644 mtx_unlock(&device->shader_slab_mutex);
645 return slab->ptr + offset;
646 }
647 offset = align_u64(s->bo_offset + s->code_size, 256);
648 }
649 if (slab->size - offset >= shader->code_size) {
650 shader->bo = slab->bo;
651 shader->bo_offset = offset;
652 list_addtail(&shader->slab_list, &slab->shaders);
653 mtx_unlock(&device->shader_slab_mutex);
654 return slab->ptr + offset;
655 }
656 }
657
658 mtx_unlock(&device->shader_slab_mutex);
659 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
660
661 slab->size = 256 * 1024;
662 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
663 RADEON_DOMAIN_VRAM,
664 RADEON_FLAG_NO_INTERPROCESS_SHARING |
665 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
666 0 : RADEON_FLAG_READ_ONLY),
667 RADV_BO_PRIORITY_SHADER);
668 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
669 list_inithead(&slab->shaders);
670
671 mtx_lock(&device->shader_slab_mutex);
672 list_add(&slab->slabs, &device->shader_slabs);
673
674 shader->bo = slab->bo;
675 shader->bo_offset = 0;
676 list_add(&shader->slab_list, &slab->shaders);
677 mtx_unlock(&device->shader_slab_mutex);
678 return slab->ptr;
679 }
680
681 void
682 radv_destroy_shader_slabs(struct radv_device *device)
683 {
684 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
685 device->ws->buffer_destroy(slab->bo);
686 free(slab);
687 }
688 mtx_destroy(&device->shader_slab_mutex);
689 }
690
691 /* For the UMR disassembler. */
692 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
693 #define DEBUGGER_NUM_MARKERS 5
694
695 static unsigned
696 radv_get_shader_binary_size(size_t code_size)
697 {
698 return code_size + DEBUGGER_NUM_MARKERS * 4;
699 }
700
701 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
702 const struct ac_shader_config *config_in,
703 const struct radv_shader_info *info,
704 gl_shader_stage stage,
705 struct ac_shader_config *config_out)
706 {
707 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
708 unsigned vgpr_comp_cnt = 0;
709 unsigned num_input_vgprs = info->num_input_vgprs;
710
711 if (stage == MESA_SHADER_FRAGMENT) {
712 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
713 }
714
715 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
716 /* +3 for scratch wave offset and VCC */
717 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
718 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
719 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
720 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
721 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
722 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
723
724 *config_out = *config_in;
725 config_out->num_vgprs = num_vgprs;
726 config_out->num_sgprs = num_sgprs;
727 config_out->num_shared_vgprs = num_shared_vgprs;
728
729 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
730 S_00B12C_SCRATCH_EN(scratch_enabled);
731
732 if (!pdevice->use_ngg_streamout) {
733 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
734 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
735 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
736 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
737 S_00B12C_SO_EN(!!info->so.num_outputs);
738 }
739
740 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
741 (info->wave_size == 32 ? 8 : 4)) |
742 S_00B848_DX10_CLAMP(1) |
743 S_00B848_FLOAT_MODE(config_out->float_mode);
744
745 if (pdevice->rad_info.chip_class >= GFX10) {
746 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
747 } else {
748 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
749 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
750 }
751
752 switch (stage) {
753 case MESA_SHADER_TESS_EVAL:
754 if (info->is_ngg) {
755 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
756 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
757 } else if (info->tes.as_es) {
758 assert(pdevice->rad_info.chip_class <= GFX8);
759 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
760
761 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
762 } else {
763 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
764 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
765
766 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
767 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
768 }
769 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
770 break;
771 case MESA_SHADER_TESS_CTRL:
772 if (pdevice->rad_info.chip_class >= GFX9) {
773 /* We need at least 2 components for LS.
774 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
775 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
776 */
777 if (pdevice->rad_info.chip_class >= GFX10) {
778 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
779 } else {
780 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
781 }
782 } else {
783 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
784 }
785 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
786 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
787 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
788 break;
789 case MESA_SHADER_VERTEX:
790 if (info->is_ngg) {
791 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
792 } else if (info->vs.as_ls) {
793 assert(pdevice->rad_info.chip_class <= GFX8);
794 /* We need at least 2 components for LS.
795 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
796 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
797 */
798 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
799 } else if (info->vs.as_es) {
800 assert(pdevice->rad_info.chip_class <= GFX8);
801 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
802 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
803 } else {
804 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
805 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
806 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
807 */
808 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
809 vgpr_comp_cnt = 3;
810 } else if (info->vs.export_prim_id) {
811 vgpr_comp_cnt = 2;
812 } else if (info->vs.needs_instance_id) {
813 vgpr_comp_cnt = 1;
814 } else {
815 vgpr_comp_cnt = 0;
816 }
817
818 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
819 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
820 }
821 break;
822 case MESA_SHADER_FRAGMENT:
823 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
824 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
825 break;
826 case MESA_SHADER_GEOMETRY:
827 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
828 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
829 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
830 break;
831 case MESA_SHADER_COMPUTE:
832 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
833 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
834 config_out->rsrc2 |=
835 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
836 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
837 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
838 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
839 info->cs.uses_thread_id[1] ? 1 : 0) |
840 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
841 S_00B84C_LDS_SIZE(config_in->lds_size);
842 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
843
844 break;
845 default:
846 unreachable("unsupported shader type");
847 break;
848 }
849
850 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
851 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
852 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
853 gl_shader_stage es_stage = stage;
854 if (stage == MESA_SHADER_GEOMETRY)
855 es_stage = info->gs.es_type;
856
857 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
858 if (es_stage == MESA_SHADER_VERTEX) {
859 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
860 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
861 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
862 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
863 } else
864 unreachable("Unexpected ES shader stage");
865
866 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
867 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
868 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
869 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
870 } else if (info->uses_prim_id) {
871 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
872 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
873 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
874 } else {
875 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
876 }
877
878 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
879 S_00B228_WGP_MODE(1);
880 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
881 S_00B22C_LDS_SIZE(config_in->lds_size) |
882 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
883 } else if (pdevice->rad_info.chip_class >= GFX9 &&
884 stage == MESA_SHADER_GEOMETRY) {
885 unsigned es_type = info->gs.es_type;
886 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
887
888 if (es_type == MESA_SHADER_VERTEX) {
889 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
890 if (info->vs.needs_instance_id) {
891 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
892 } else {
893 es_vgpr_comp_cnt = 0;
894 }
895 } else if (es_type == MESA_SHADER_TESS_EVAL) {
896 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
897 } else {
898 unreachable("invalid shader ES type");
899 }
900
901 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
902 * VGPR[0:4] are always loaded.
903 */
904 if (info->uses_invocation_id) {
905 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
906 } else if (info->uses_prim_id) {
907 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
908 } else if (info->gs.vertices_in >= 3) {
909 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
910 } else {
911 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
912 }
913
914 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
915 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
916 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
917 } else if (pdevice->rad_info.chip_class >= GFX9 &&
918 stage == MESA_SHADER_TESS_CTRL) {
919 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
920 } else {
921 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
922 }
923 }
924
925 struct radv_shader_variant *
926 radv_shader_variant_create(struct radv_device *device,
927 const struct radv_shader_binary *binary,
928 bool keep_shader_info)
929 {
930 struct ac_shader_config config = {0};
931 struct ac_rtld_binary rtld_binary = {0};
932 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
933 if (!variant)
934 return NULL;
935
936 variant->ref_count = 1;
937
938 if (binary->type == RADV_BINARY_TYPE_RTLD) {
939 struct ac_rtld_symbol lds_symbols[2];
940 unsigned num_lds_symbols = 0;
941 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
942 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
943
944 if (device->physical_device->rad_info.chip_class >= GFX9 &&
945 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
946 !binary->is_gs_copy_shader) {
947 /* We add this symbol even on LLVM <= 8 to ensure that
948 * shader->config.lds_size is set correctly below.
949 */
950 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
951 sym->name = "esgs_ring";
952 sym->size = binary->info.ngg_info.esgs_ring_size;
953 sym->align = 64 * 1024;
954 }
955
956 if (binary->info.is_ngg &&
957 binary->stage == MESA_SHADER_GEOMETRY) {
958 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
959 sym->name = "ngg_emit";
960 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
961 sym->align = 4;
962 }
963
964 struct ac_rtld_open_info open_info = {
965 .info = &device->physical_device->rad_info,
966 .shader_type = binary->stage,
967 .wave_size = binary->info.wave_size,
968 .num_parts = 1,
969 .elf_ptrs = &elf_data,
970 .elf_sizes = &elf_size,
971 .num_shared_lds_symbols = num_lds_symbols,
972 .shared_lds_symbols = lds_symbols,
973 };
974
975 if (!ac_rtld_open(&rtld_binary, open_info)) {
976 free(variant);
977 return NULL;
978 }
979
980 if (!ac_rtld_read_config(&rtld_binary, &config)) {
981 ac_rtld_close(&rtld_binary);
982 free(variant);
983 return NULL;
984 }
985
986 /* Enable 64-bit and 16-bit denormals, because there is no performance
987 * cost.
988 *
989 * If denormals are enabled, all floating-point output modifiers are
990 * ignored.
991 *
992 * Don't enable denormals for 32-bit floats, because:
993 * - Floating-point output modifiers would be ignored by the hw.
994 * - Some opcodes don't support denormals, such as v_mad_f32. We would
995 * have to stop using those.
996 * - GFX6 & GFX7 would be very slow.
997 */
998 config.float_mode |= V_00B028_FP_64_DENORMS;
999
1000 if (rtld_binary.lds_size > 0) {
1001 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1002 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1003 }
1004
1005 variant->code_size = rtld_binary.rx_size;
1006 variant->exec_size = rtld_binary.exec_size;
1007 } else {
1008 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1009 config = ((struct radv_shader_binary_legacy *)binary)->config;
1010 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1011 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1012 }
1013
1014 variant->info = binary->info;
1015 radv_postprocess_config(device->physical_device, &config, &binary->info,
1016 binary->stage, &variant->config);
1017
1018 if (radv_device_use_secure_compile(device->instance)) {
1019 if (binary->type == RADV_BINARY_TYPE_RTLD)
1020 ac_rtld_close(&rtld_binary);
1021
1022 return variant;
1023 }
1024
1025 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1026
1027 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1028 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1029 struct ac_rtld_upload_info info = {
1030 .binary = &rtld_binary,
1031 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1032 .rx_ptr = dest_ptr,
1033 };
1034
1035 if (!ac_rtld_upload(&info)) {
1036 radv_shader_variant_destroy(device, variant);
1037 ac_rtld_close(&rtld_binary);
1038 return NULL;
1039 }
1040
1041 if (keep_shader_info ||
1042 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1043 const char *disasm_data;
1044 size_t disasm_size;
1045 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1046 radv_shader_variant_destroy(device, variant);
1047 ac_rtld_close(&rtld_binary);
1048 return NULL;
1049 }
1050
1051 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1052 variant->disasm_string = malloc(disasm_size + 1);
1053 memcpy(variant->disasm_string, disasm_data, disasm_size);
1054 variant->disasm_string[disasm_size] = 0;
1055 }
1056
1057 ac_rtld_close(&rtld_binary);
1058 } else {
1059 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1060 memcpy(dest_ptr, bin->data, bin->code_size);
1061
1062 /* Add end-of-code markers for the UMR disassembler. */
1063 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1064 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1065 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1066
1067 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1068 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1069 }
1070 return variant;
1071 }
1072
1073 static char *
1074 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1075 int shader_count)
1076 {
1077 char *data = NULL;
1078 char *ret = NULL;
1079 size_t size = 0;
1080 FILE *f = open_memstream(&data, &size);
1081 if (f) {
1082 for (int i = 0; i < shader_count; ++i)
1083 nir_print_shader(shaders[i], f);
1084 fclose(f);
1085 }
1086
1087 ret = malloc(size + 1);
1088 if (ret) {
1089 memcpy(ret, data, size);
1090 ret[size] = 0;
1091 }
1092 free(data);
1093 return ret;
1094 }
1095
1096 static struct radv_shader_variant *
1097 shader_variant_compile(struct radv_device *device,
1098 struct radv_shader_module *module,
1099 struct nir_shader * const *shaders,
1100 int shader_count,
1101 gl_shader_stage stage,
1102 struct radv_shader_info *info,
1103 struct radv_nir_compiler_options *options,
1104 bool gs_copy_shader,
1105 bool keep_shader_info,
1106 bool use_aco,
1107 struct radv_shader_binary **binary_out)
1108 {
1109 enum radeon_family chip_family = device->physical_device->rad_info.family;
1110 struct radv_shader_binary *binary = NULL;
1111
1112 options->family = chip_family;
1113 options->chip_class = device->physical_device->rad_info.chip_class;
1114 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1115 options->dump_preoptir = options->dump_shader &&
1116 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1117 options->record_ir = keep_shader_info;
1118 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1119 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1120 options->address32_hi = device->physical_device->rad_info.address32_hi;
1121 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1122 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1123
1124 struct radv_shader_args args = {};
1125 args.options = options;
1126 args.shader_info = info;
1127 args.is_gs_copy_shader = gs_copy_shader;
1128 radv_declare_shader_args(&args,
1129 gs_copy_shader ? MESA_SHADER_VERTEX
1130 : shaders[shader_count - 1]->info.stage,
1131 shader_count >= 2,
1132 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1133 : MESA_SHADER_VERTEX);
1134
1135 if (!use_aco || options->dump_shader || options->record_ir)
1136 ac_init_llvm_once();
1137
1138 if (use_aco) {
1139 aco_compile_shader(shader_count, shaders, &binary, &args);
1140 binary->info = *info;
1141 } else {
1142 enum ac_target_machine_options tm_options = 0;
1143 struct ac_llvm_compiler ac_llvm;
1144 bool thread_compiler;
1145
1146 tm_options |= AC_TM_SUPPORTS_SPILL;
1147 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1148 tm_options |= AC_TM_SISCHED;
1149 if (options->check_ir)
1150 tm_options |= AC_TM_CHECK_IR;
1151 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1152 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1153
1154 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1155 radv_init_llvm_compiler(&ac_llvm,
1156 thread_compiler,
1157 chip_family, tm_options,
1158 info->wave_size);
1159
1160 if (gs_copy_shader) {
1161 assert(shader_count == 1);
1162 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1163 &args);
1164 } else {
1165 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1166 shaders, shader_count);
1167 }
1168
1169 binary->info = *info;
1170 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1171 }
1172
1173 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1174 keep_shader_info);
1175 if (!variant) {
1176 free(binary);
1177 return NULL;
1178 }
1179 variant->aco_used = use_aco;
1180
1181 if (options->dump_shader) {
1182 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1183 }
1184
1185
1186 if (keep_shader_info) {
1187 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1188 if (!gs_copy_shader && !module->nir) {
1189 variant->spirv = malloc(module->size);
1190 if (!variant->spirv) {
1191 free(variant);
1192 free(binary);
1193 return NULL;
1194 }
1195
1196 memcpy(variant->spirv, module->data, module->size);
1197 variant->spirv_size = module->size;
1198 }
1199 }
1200
1201 if (binary_out)
1202 *binary_out = binary;
1203 else
1204 free(binary);
1205
1206 return variant;
1207 }
1208
1209 struct radv_shader_variant *
1210 radv_shader_variant_compile(struct radv_device *device,
1211 struct radv_shader_module *module,
1212 struct nir_shader *const *shaders,
1213 int shader_count,
1214 struct radv_pipeline_layout *layout,
1215 const struct radv_shader_variant_key *key,
1216 struct radv_shader_info *info,
1217 bool keep_shader_info,
1218 bool use_aco,
1219 struct radv_shader_binary **binary_out)
1220 {
1221 struct radv_nir_compiler_options options = {0};
1222
1223 options.layout = layout;
1224 if (key)
1225 options.key = *key;
1226
1227 options.explicit_scratch_args = use_aco;
1228 options.robust_buffer_access = device->robust_buffer_access;
1229
1230 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1231 &options, false, keep_shader_info, use_aco, binary_out);
1232 }
1233
1234 struct radv_shader_variant *
1235 radv_create_gs_copy_shader(struct radv_device *device,
1236 struct nir_shader *shader,
1237 struct radv_shader_info *info,
1238 struct radv_shader_binary **binary_out,
1239 bool keep_shader_info,
1240 bool multiview)
1241 {
1242 struct radv_nir_compiler_options options = {0};
1243
1244 options.key.has_multiview_view_index = multiview;
1245
1246 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1247 info, &options, true, keep_shader_info, false, binary_out);
1248 }
1249
1250 void
1251 radv_shader_variant_destroy(struct radv_device *device,
1252 struct radv_shader_variant *variant)
1253 {
1254 if (!p_atomic_dec_zero(&variant->ref_count))
1255 return;
1256
1257 mtx_lock(&device->shader_slab_mutex);
1258 list_del(&variant->slab_list);
1259 mtx_unlock(&device->shader_slab_mutex);
1260
1261 free(variant->spirv);
1262 free(variant->nir_string);
1263 free(variant->disasm_string);
1264 free(variant->ir_string);
1265 free(variant);
1266 }
1267
1268 const char *
1269 radv_get_shader_name(struct radv_shader_info *info,
1270 gl_shader_stage stage)
1271 {
1272 switch (stage) {
1273 case MESA_SHADER_VERTEX:
1274 if (info->vs.as_ls)
1275 return "Vertex Shader as LS";
1276 else if (info->vs.as_es)
1277 return "Vertex Shader as ES";
1278 else if (info->is_ngg)
1279 return "Vertex Shader as ESGS";
1280 else
1281 return "Vertex Shader as VS";
1282 case MESA_SHADER_TESS_CTRL:
1283 return "Tessellation Control Shader";
1284 case MESA_SHADER_TESS_EVAL:
1285 if (info->tes.as_es)
1286 return "Tessellation Evaluation Shader as ES";
1287 else if (info->is_ngg)
1288 return "Tessellation Evaluation Shader as ESGS";
1289 else
1290 return "Tessellation Evaluation Shader as VS";
1291 case MESA_SHADER_GEOMETRY:
1292 return "Geometry Shader";
1293 case MESA_SHADER_FRAGMENT:
1294 return "Pixel Shader";
1295 case MESA_SHADER_COMPUTE:
1296 return "Compute Shader";
1297 default:
1298 return "Unknown shader";
1299 };
1300 }
1301
1302 unsigned
1303 radv_get_max_workgroup_size(enum chip_class chip_class,
1304 gl_shader_stage stage,
1305 const unsigned *sizes)
1306 {
1307 switch (stage) {
1308 case MESA_SHADER_TESS_CTRL:
1309 return chip_class >= GFX7 ? 128 : 64;
1310 case MESA_SHADER_GEOMETRY:
1311 return chip_class >= GFX9 ? 128 : 64;
1312 case MESA_SHADER_COMPUTE:
1313 break;
1314 default:
1315 return 0;
1316 }
1317
1318 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1319 return max_workgroup_size;
1320 }
1321
1322 unsigned
1323 radv_get_max_waves(struct radv_device *device,
1324 struct radv_shader_variant *variant,
1325 gl_shader_stage stage)
1326 {
1327 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1328 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1329 uint8_t wave_size = variant->info.wave_size;
1330 struct ac_shader_config *conf = &variant->config;
1331 unsigned max_simd_waves;
1332 unsigned lds_per_wave = 0;
1333
1334 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1335
1336 if (stage == MESA_SHADER_FRAGMENT) {
1337 lds_per_wave = conf->lds_size * lds_increment +
1338 align(variant->info.ps.num_interp * 48,
1339 lds_increment);
1340 } else if (stage == MESA_SHADER_COMPUTE) {
1341 unsigned max_workgroup_size =
1342 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1343 lds_per_wave = (conf->lds_size * lds_increment) /
1344 DIV_ROUND_UP(max_workgroup_size, wave_size);
1345 }
1346
1347 if (conf->num_sgprs) {
1348 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1349 max_simd_waves =
1350 MIN2(max_simd_waves,
1351 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1352 sgprs);
1353 }
1354
1355 if (conf->num_vgprs) {
1356 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1357 max_simd_waves =
1358 MIN2(max_simd_waves,
1359 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1360 }
1361
1362 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1363 * that PS can use.
1364 */
1365 if (lds_per_wave)
1366 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1367
1368 return max_simd_waves;
1369 }
1370
1371 static void
1372 generate_shader_stats(struct radv_device *device,
1373 struct radv_shader_variant *variant,
1374 gl_shader_stage stage,
1375 struct _mesa_string_buffer *buf)
1376 {
1377 struct ac_shader_config *conf = &variant->config;
1378 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1379
1380 if (stage == MESA_SHADER_FRAGMENT) {
1381 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1382 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1383 "SPI_PS_INPUT_ENA = 0x%04x\n",
1384 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1385 }
1386
1387 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1388 "SGPRS: %d\n"
1389 "VGPRS: %d\n"
1390 "Spilled SGPRs: %d\n"
1391 "Spilled VGPRs: %d\n"
1392 "PrivMem VGPRS: %d\n"
1393 "Code Size: %d bytes\n"
1394 "LDS: %d blocks\n"
1395 "Scratch: %d bytes per wave\n"
1396 "Max Waves: %d\n"
1397 "********************\n\n\n",
1398 conf->num_sgprs, conf->num_vgprs,
1399 conf->spilled_sgprs, conf->spilled_vgprs,
1400 variant->info.private_mem_vgprs, variant->exec_size,
1401 conf->lds_size, conf->scratch_bytes_per_wave,
1402 max_simd_waves);
1403 }
1404
1405 void
1406 radv_shader_dump_stats(struct radv_device *device,
1407 struct radv_shader_variant *variant,
1408 gl_shader_stage stage,
1409 FILE *file)
1410 {
1411 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1412
1413 generate_shader_stats(device, variant, stage, buf);
1414
1415 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1416 fprintf(file, "%s", buf->buf);
1417
1418 _mesa_string_buffer_destroy(buf);
1419 }
1420
1421 VkResult
1422 radv_GetShaderInfoAMD(VkDevice _device,
1423 VkPipeline _pipeline,
1424 VkShaderStageFlagBits shaderStage,
1425 VkShaderInfoTypeAMD infoType,
1426 size_t* pInfoSize,
1427 void* pInfo)
1428 {
1429 RADV_FROM_HANDLE(radv_device, device, _device);
1430 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1431 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1432 struct radv_shader_variant *variant = pipeline->shaders[stage];
1433 struct _mesa_string_buffer *buf;
1434 VkResult result = VK_SUCCESS;
1435
1436 /* Spec doesn't indicate what to do if the stage is invalid, so just
1437 * return no info for this. */
1438 if (!variant)
1439 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1440
1441 switch (infoType) {
1442 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1443 if (!pInfo) {
1444 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1445 } else {
1446 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1447 struct ac_shader_config *conf = &variant->config;
1448
1449 VkShaderStatisticsInfoAMD statistics = {};
1450 statistics.shaderStageMask = shaderStage;
1451 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1452 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1453 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1454
1455 if (stage == MESA_SHADER_COMPUTE) {
1456 unsigned *local_size = variant->info.cs.block_size;
1457 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1458
1459 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1460 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1461
1462 statistics.computeWorkGroupSize[0] = local_size[0];
1463 statistics.computeWorkGroupSize[1] = local_size[1];
1464 statistics.computeWorkGroupSize[2] = local_size[2];
1465 } else {
1466 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1467 }
1468
1469 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1470 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1471 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1472 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1473 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1474
1475 size_t size = *pInfoSize;
1476 *pInfoSize = sizeof(statistics);
1477
1478 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1479
1480 if (size < *pInfoSize)
1481 result = VK_INCOMPLETE;
1482 }
1483
1484 break;
1485 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1486 buf = _mesa_string_buffer_create(NULL, 1024);
1487
1488 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1489 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1490 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1491 generate_shader_stats(device, variant, stage, buf);
1492
1493 /* Need to include the null terminator. */
1494 size_t length = buf->length + 1;
1495
1496 if (!pInfo) {
1497 *pInfoSize = length;
1498 } else {
1499 size_t size = *pInfoSize;
1500 *pInfoSize = length;
1501
1502 memcpy(pInfo, buf->buf, MIN2(size, length));
1503
1504 if (size < length)
1505 result = VK_INCOMPLETE;
1506 }
1507
1508 _mesa_string_buffer_destroy(buf);
1509 break;
1510 default:
1511 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1512 result = VK_ERROR_FEATURE_NOT_PRESENT;
1513 break;
1514 }
1515
1516 return result;
1517 }