src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 static const struct nir_shader_compiler_options nir_options = {
  50         .vertex_id_zero_based = true,
  51         .lower_scmp = true,
  52         .lower_flrp32 = true,
  53         .lower_fsat = true,
  54         .lower_fdiv = true,
  55         .lower_sub = true,
  56         .lower_pack_snorm_2x16 = true,
  57         .lower_pack_snorm_4x8 = true,
  58         .lower_pack_unorm_2x16 = true,
  59         .lower_pack_unorm_4x8 = true,
  60         .lower_unpack_snorm_2x16 = true,
  61         .lower_unpack_snorm_4x8 = true,
  62         .lower_unpack_unorm_2x16 = true,
  63         .lower_unpack_unorm_4x8 = true,
  64         .lower_extract_byte = true,
  65         .lower_extract_word = true,
  66         .lower_ffma = true,
  67         .max_unroll_iterations = 32
  68 };
  69
  70 VkResult radv_CreateShaderModule(
  71         VkDevice                                    _device,
  72         const VkShaderModuleCreateInfo*             pCreateInfo,
  73         const VkAllocationCallbacks*                pAllocator,
  74         VkShaderModule*                             pShaderModule)
  75 {
  76         RADV_FROM_HANDLE(radv_device, device, _device);
  77         struct radv_shader_module *module;
  78
  79         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  80         assert(pCreateInfo->flags == 0);
  81
  82         module = vk_alloc2(&device->alloc, pAllocator,
  83                              sizeof(*module) + pCreateInfo->codeSize, 8,
  84                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  85         if (module == NULL)
  86                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  87
  88         module->nir = NULL;
  89         module->size = pCreateInfo->codeSize;
  90         memcpy(module->data, pCreateInfo->pCode, module->size);
  91
  92         _mesa_sha1_compute(module->data, module->size, module->sha1);
  93
  94         *pShaderModule = radv_shader_module_to_handle(module);
  95
  96         return VK_SUCCESS;
  97 }
  98
  99 void radv_DestroyShaderModule(
 100         VkDevice                                    _device,
 101         VkShaderModule                              _module,
 102         const VkAllocationCallbacks*                pAllocator)
 103 {
 104         RADV_FROM_HANDLE(radv_device, device, _device);
 105         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 106
 107         if (!module)
 108                 return;
 109
 110         vk_free2(&device->alloc, pAllocator, module);
 111 }
 112
 113 void
 114 radv_optimize_nir(struct nir_shader *shader)
 115 {
 116         bool progress;
 117
 118         do {
 119                 progress = false;
 120
 121                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 122                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 123                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 124                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 125
 126                 NIR_PASS(progress, shader, nir_copy_prop);
 127                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 128                 NIR_PASS(progress, shader, nir_opt_dce);
 129                 if (nir_opt_trivial_continues(shader)) {
 130                         progress = true;
 131                         NIR_PASS(progress, shader, nir_copy_prop);
 132                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 133                         NIR_PASS(progress, shader, nir_opt_dce);
 134                 }
 135                 NIR_PASS(progress, shader, nir_opt_if);
 136                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 137                 NIR_PASS(progress, shader, nir_opt_cse);
 138                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 139                 NIR_PASS(progress, shader, nir_opt_algebraic);
 140                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 141                 NIR_PASS(progress, shader, nir_opt_undef);
 142                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 143                 if (shader->options->max_unroll_iterations) {
 144                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 145                 }
 146         } while (progress);
 147 }
 148
 149 nir_shader *
 150 radv_shader_compile_to_nir(struct radv_device *device,
 151                            struct radv_shader_module *module,
 152                            const char *entrypoint_name,
 153                            gl_shader_stage stage,
 154                            const VkSpecializationInfo *spec_info)
 155 {
 156         if (strcmp(entrypoint_name, "main") != 0) {
 157                 radv_finishme("Multiple shaders per module not really supported");
 158         }
 159
 160         nir_shader *nir;
 161         nir_function *entry_point;
 162         if (module->nir) {
 163                 /* Some things such as our meta clear/blit code will give us a NIR
 164                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 165                  * and just use the NIR shader */
 166                 nir = module->nir;
 167                 nir->options = &nir_options;
 168                 nir_validate_shader(nir);
 169
 170                 assert(exec_list_length(&nir->functions) == 1);
 171                 struct exec_node *node = exec_list_get_head(&nir->functions);
 172                 entry_point = exec_node_data(nir_function, node, node);
 173         } else {
 174                 uint32_t *spirv = (uint32_t *) module->data;
 175                 assert(module->size % 4 == 0);
 176
 177                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 178                         radv_print_spirv(spirv, module->size, stderr);
 179
 180                 uint32_t num_spec_entries = 0;
 181                 struct nir_spirv_specialization *spec_entries = NULL;
 182                 if (spec_info && spec_info->mapEntryCount > 0) {
 183                         num_spec_entries = spec_info->mapEntryCount;
 184                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 185                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 186                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 187                                 const void *data = spec_info->pData + entry.offset;
 188                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 189
 190                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 191                                 if (spec_info->dataSize == 8)
 192                                         spec_entries[i].data64 = *(const uint64_t *)data;
 193                                 else
 194                                         spec_entries[i].data32 = *(const uint32_t *)data;
 195                         }
 196                 }
 197                 const struct nir_spirv_supported_extensions supported_ext = {
 198                         .draw_parameters = true,
 199                         .float64 = true,
 200                         .image_read_without_format = true,
 201                         .image_write_without_format = true,
 202                         .tessellation = true,
 203                         .int64 = true,
 204                         .multiview = true,
 205                         .variable_pointers = true,
 206                 };
 207                 entry_point = spirv_to_nir(spirv, module->size / 4,
 208                                            spec_entries, num_spec_entries,
 209                                            stage, entrypoint_name, &supported_ext, &nir_options);
 210                 nir = entry_point->shader;
 211                 assert(nir->info.stage == stage);
 212                 nir_validate_shader(nir);
 213
 214                 free(spec_entries);
 215
 216                 /* We have to lower away local constant initializers right before we
 217                  * inline functions.  That way they get properly initialized at the top
 218                  * of the function and not at the top of its caller.
 219                  */
 220                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 221                 NIR_PASS_V(nir, nir_lower_returns);
 222                 NIR_PASS_V(nir, nir_inline_functions);
 223
 224                 /* Pick off the single entrypoint that we want */
 225                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 226                         if (func != entry_point)
 227                                 exec_node_remove(&func->node);
 228                 }
 229                 assert(exec_list_length(&nir->functions) == 1);
 230                 entry_point->name = ralloc_strdup(entry_point, "main");
 231
 232                 NIR_PASS_V(nir, nir_remove_dead_variables,
 233                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 234
 235                 /* Now that we've deleted all but the main function, we can go ahead and
 236                  * lower the rest of the constant initializers.
 237                  */
 238                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 239                 NIR_PASS_V(nir, nir_lower_system_values);
 240                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 241         }
 242
 243         /* Vulkan uses the separate-shader linking model */
 244         nir->info.separate_shader = true;
 245
 246         nir_shader_gather_info(nir, entry_point->impl);
 247
 248         /* While it would be nice not to have this flag, we are constrained
 249          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 250          * on GFX9.
 251          */
 252         bool llvm_has_working_vgpr_indexing =
 253                 device->physical_device->rad_info.chip_class <= VI;
 254
 255         /* TODO: Indirect indexing of GS inputs is unimplemented.
 256          *
 257          * TCS and TES load inputs directly from LDS or offchip memory, so
 258          * indirect indexing is trivial.
 259          */
 260         nir_variable_mode indirect_mask = 0;
 261         if (nir->info.stage == MESA_SHADER_GEOMETRY ||
 262             (nir->info.stage != MESA_SHADER_TESS_CTRL &&
 263              nir->info.stage != MESA_SHADER_TESS_EVAL &&
 264              !llvm_has_working_vgpr_indexing)) {
 265                 indirect_mask |= nir_var_shader_in;
 266         }
 267         if (!llvm_has_working_vgpr_indexing &&
 268             (nir->info.stage == MESA_SHADER_VERTEX ||
 269              nir->info.stage == MESA_SHADER_TESS_EVAL ||
 270              nir->info.stage == MESA_SHADER_FRAGMENT))
 271                 indirect_mask |= nir_var_shader_out;
 272
 273         /* TODO: We shouldn't need to do this, however LLVM isn't currently
 274          * smart enough to handle indirects without causing excess spilling
 275          * causing the gpu to hang.
 276          *
 277          * See the following thread for more details of the problem:
 278          * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
 279          */
 280         indirect_mask |= nir_var_local;
 281
 282         nir_lower_indirect_derefs(nir, indirect_mask);
 283
 284         static const nir_lower_tex_options tex_options = {
 285           .lower_txp = ~0,
 286         };
 287
 288         nir_lower_tex(nir, &tex_options);
 289
 290         nir_lower_vars_to_ssa(nir);
 291         nir_lower_var_copies(nir);
 292         nir_lower_global_vars_to_local(nir);
 293         nir_remove_dead_variables(nir, nir_var_local);
 294         radv_optimize_nir(nir);
 295
 296         if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
 297                 nir_print_shader(nir, stderr);
 298
 299         return nir;
 300 }
 301
 302 void *
 303 radv_alloc_shader_memory(struct radv_device *device,
 304                          struct radv_shader_variant *shader)
 305 {
 306         mtx_lock(&device->shader_slab_mutex);
 307         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 308                 uint64_t offset = 0;
 309                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 310                         if (s->bo_offset - offset >= shader->code_size) {
 311                                 shader->bo = slab->bo;
 312                                 shader->bo_offset = offset;
 313                                 list_addtail(&shader->slab_list, &s->slab_list);
 314                                 mtx_unlock(&device->shader_slab_mutex);
 315                                 return slab->ptr + offset;
 316                         }
 317                         offset = align_u64(s->bo_offset + s->code_size, 256);
 318                 }
 319                 if (slab->size - offset >= shader->code_size) {
 320                         shader->bo = slab->bo;
 321                         shader->bo_offset = offset;
 322                         list_addtail(&shader->slab_list, &slab->shaders);
 323                         mtx_unlock(&device->shader_slab_mutex);
 324                         return slab->ptr + offset;
 325                 }
 326         }
 327
 328         mtx_unlock(&device->shader_slab_mutex);
 329         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 330
 331         slab->size = 256 * 1024;
 332         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 333                                              RADEON_DOMAIN_VRAM, 0);
 334         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 335         list_inithead(&slab->shaders);
 336
 337         mtx_lock(&device->shader_slab_mutex);
 338         list_add(&slab->slabs, &device->shader_slabs);
 339
 340         shader->bo = slab->bo;
 341         shader->bo_offset = 0;
 342         list_add(&shader->slab_list, &slab->shaders);
 343         mtx_unlock(&device->shader_slab_mutex);
 344         return slab->ptr;
 345 }
 346
 347 void
 348 radv_destroy_shader_slabs(struct radv_device *device)
 349 {
 350         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 351                 device->ws->buffer_destroy(slab->bo);
 352                 free(slab);
 353         }
 354         mtx_destroy(&device->shader_slab_mutex);
 355 }
 356
 357 static void
 358 radv_fill_shader_variant(struct radv_device *device,
 359                          struct radv_shader_variant *variant,
 360                          struct ac_shader_binary *binary,
 361                          gl_shader_stage stage)
 362 {
 363         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 364         unsigned vgpr_comp_cnt = 0;
 365
 366         if (scratch_enabled && !device->llvm_supports_spill)
 367                 radv_finishme("shader scratch support only available with LLVM 4.0");
 368
 369         variant->code_size = binary->code_size;
 370         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 371                         S_00B12C_SCRATCH_EN(scratch_enabled);
 372
 373         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 374                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 375                 S_00B848_DX10_CLAMP(1) |
 376                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 377
 378         switch (stage) {
 379         case MESA_SHADER_TESS_EVAL:
 380                 vgpr_comp_cnt = 3;
 381                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 382                 break;
 383         case MESA_SHADER_TESS_CTRL:
 384                 if (device->physical_device->rad_info.chip_class >= GFX9)
 385                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 386                 else
 387                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 388                 break;
 389         case MESA_SHADER_VERTEX:
 390         case MESA_SHADER_GEOMETRY:
 391                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 392                 break;
 393         case MESA_SHADER_FRAGMENT:
 394                 break;
 395         case MESA_SHADER_COMPUTE:
 396                 variant->rsrc2 |=
 397                         S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 398                         S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 399                         S_00B84C_TG_SIZE_EN(1) |
 400                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 401                 break;
 402         default:
 403                 unreachable("unsupported shader type");
 404                 break;
 405         }
 406
 407         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 408             stage == MESA_SHADER_GEOMETRY) {
 409                 /* TODO: Figure out how many we actually need. */
 410                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(3);
 411                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
 412                                   S_00B22C_OC_LDS_EN(1);
 413         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 414             stage == MESA_SHADER_TESS_CTRL)
 415                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 416         else
 417                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 418
 419         void *ptr = radv_alloc_shader_memory(device, variant);
 420         memcpy(ptr, binary->code, binary->code_size);
 421 }
 422
 423 static struct radv_shader_variant *
 424 shader_variant_create(struct radv_device *device,
 425                       struct radv_shader_module *module,
 426                       struct nir_shader * const *shaders,
 427                       int shader_count,
 428                       gl_shader_stage stage,
 429                       struct ac_nir_compiler_options *options,
 430                       bool gs_copy_shader,
 431                       void **code_out,
 432                       unsigned *code_size_out)
 433 {
 434         enum radeon_family chip_family = device->physical_device->rad_info.family;
 435         bool dump_shaders = device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS;
 436         enum ac_target_machine_options tm_options = 0;
 437         struct radv_shader_variant *variant;
 438         struct ac_shader_binary binary;
 439         LLVMTargetMachineRef tm;
 440
 441         variant = calloc(1, sizeof(struct radv_shader_variant));
 442         if (!variant)
 443                 return NULL;
 444
 445         options->family = chip_family;
 446         options->chip_class = device->physical_device->rad_info.chip_class;
 447
 448         if (options->supports_spill)
 449                 tm_options |= AC_TM_SUPPORTS_SPILL;
 450         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 451                 tm_options |= AC_TM_SISCHED;
 452         tm = ac_create_target_machine(chip_family, tm_options);
 453
 454         if (gs_copy_shader) {
 455                 assert(shader_count == 1);
 456                 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
 457                                          &variant->info, options, dump_shaders);
 458         } else {
 459                 ac_compile_nir_shader(tm, &binary, &variant->config,
 460                                       &variant->info, shaders, shader_count, options,
 461                                       dump_shaders);
 462         }
 463
 464         LLVMDisposeTargetMachine(tm);
 465
 466         radv_fill_shader_variant(device, variant, &binary, stage);
 467
 468         if (code_out) {
 469                 *code_out = binary.code;
 470                 *code_size_out = binary.code_size;
 471         } else
 472                 free(binary.code);
 473         free(binary.config);
 474         free(binary.rodata);
 475         free(binary.global_symbol_offsets);
 476         free(binary.relocs);
 477         variant->ref_count = 1;
 478
 479         if (device->trace_bo) {
 480                 variant->disasm_string = binary.disasm_string;
 481                 if (!gs_copy_shader && !module->nir) {
 482                         variant->nir = *shaders;
 483                         variant->spirv = (uint32_t *)module->data;
 484                         variant->spirv_size = module->size;
 485                 }
 486         } else {
 487                 free(binary.disasm_string);
 488         }
 489
 490         return variant;
 491 }
 492
 493 struct radv_shader_variant *
 494 radv_shader_variant_create(struct radv_device *device,
 495                            struct radv_shader_module *module,
 496                            struct nir_shader *const *shaders,
 497                            int shader_count,
 498                            struct radv_pipeline_layout *layout,
 499                            const struct ac_shader_variant_key *key,
 500                            void **code_out,
 501                            unsigned *code_size_out)
 502 {
 503         struct ac_nir_compiler_options options = {0};
 504
 505         options.layout = layout;
 506         if (key)
 507                 options.key = *key;
 508
 509         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 510         options.supports_spill = device->llvm_supports_spill;
 511
 512         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 513                                      &options, false, code_out, code_size_out);
 514 }
 515
 516 struct radv_shader_variant *
 517 radv_create_gs_copy_shader(struct radv_device *device,
 518                            struct nir_shader *shader,
 519                            void **code_out,
 520                            unsigned *code_size_out,
 521                            bool multiview)
 522 {
 523         struct ac_nir_compiler_options options = {0};
 524
 525         options.key.has_multiview_view_index = multiview;
 526
 527         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 528                                      &options, true, code_out, code_size_out);
 529 }
 530
 531 void
 532 radv_shader_variant_destroy(struct radv_device *device,
 533                             struct radv_shader_variant *variant)
 534 {
 535         if (!p_atomic_dec_zero(&variant->ref_count))
 536                 return;
 537
 538         mtx_lock(&device->shader_slab_mutex);
 539         list_del(&variant->slab_list);
 540         mtx_unlock(&device->shader_slab_mutex);
 541
 542         ralloc_free(variant->nir);
 543         free(variant->disasm_string);
 544         free(variant);
 545 }
 546
 547 uint32_t
 548 radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class,
 549                                  bool has_gs, bool has_tess)
 550 {
 551         switch (stage) {
 552         case MESA_SHADER_FRAGMENT:
 553                 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
 554         case MESA_SHADER_VERTEX:
 555                 if (chip_class >= GFX9) {
 556                         return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
 557                                has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
 558                                R_00B130_SPI_SHADER_USER_DATA_VS_0;
 559                 }
 560                 if (has_tess)
 561                         return R_00B530_SPI_SHADER_USER_DATA_LS_0;
 562                 else
 563                         return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
 564         case MESA_SHADER_GEOMETRY:
 565                 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
 566                                             R_00B230_SPI_SHADER_USER_DATA_GS_0;
 567         case MESA_SHADER_COMPUTE:
 568                 return R_00B900_COMPUTE_USER_DATA_0;
 569         case MESA_SHADER_TESS_CTRL:
 570                 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
 571                                             R_00B430_SPI_SHADER_USER_DATA_HS_0;
 572         case MESA_SHADER_TESS_EVAL:
 573                 if (chip_class >= GFX9) {
 574                         return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
 575                                R_00B130_SPI_SHADER_USER_DATA_VS_0;
 576                 }
 577                 if (has_gs)
 578                         return R_00B330_SPI_SHADER_USER_DATA_ES_0;
 579                 else
 580                         return R_00B130_SPI_SHADER_USER_DATA_VS_0;
 581         default:
 582                 unreachable("unknown shader");
 583         }
 584 }
 585
 586 const char *
 587 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 588 {
 589         switch (stage) {
 590         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 591         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 592         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 593         case MESA_SHADER_COMPUTE: return "Compute Shader";
 594         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 595         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 596         default:
 597                 return "Unknown shader";
 598         };
 599 }
 600
 601 void
 602 radv_shader_dump_stats(struct radv_device *device,
 603                        struct radv_shader_variant *variant,
 604                        gl_shader_stage stage,
 605                        FILE *file)
 606 {
 607         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 608         struct ac_shader_config *conf;
 609         unsigned max_simd_waves;
 610         unsigned lds_per_wave = 0;
 611
 612         switch (device->physical_device->rad_info.family) {
 613         /* These always have 8 waves: */
 614         case CHIP_POLARIS10:
 615         case CHIP_POLARIS11:
 616         case CHIP_POLARIS12:
 617                 max_simd_waves = 8;
 618                 break;
 619         default:
 620                 max_simd_waves = 10;
 621         }
 622
 623         conf = &variant->config;
 624
 625         if (stage == MESA_SHADER_FRAGMENT) {
 626                 lds_per_wave = conf->lds_size * lds_increment +
 627                                align(variant->info.fs.num_interp * 48,
 628                                      lds_increment);
 629         }
 630
 631         if (conf->num_sgprs) {
 632                 if (device->physical_device->rad_info.chip_class >= VI)
 633                         max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
 634                 else
 635                         max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
 636         }
 637
 638         if (conf->num_vgprs)
 639                 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 640
 641         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 642          * that PS can use.
 643          */
 644         if (lds_per_wave)
 645                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 646
 647         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 648
 649         if (stage == MESA_SHADER_FRAGMENT) {
 650                 fprintf(file, "*** SHADER CONFIG ***\n"
 651                         "SPI_PS_INPUT_ADDR = 0x%04x\n"
 652                         "SPI_PS_INPUT_ENA  = 0x%04x\n",
 653                         conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 654         }
 655
 656         fprintf(file, "*** SHADER STATS ***\n"
 657                 "SGPRS: %d\n"
 658                 "VGPRS: %d\n"
 659                 "Spilled SGPRs: %d\n"
 660                 "Spilled VGPRs: %d\n"
 661                 "Code Size: %d bytes\n"
 662                 "LDS: %d blocks\n"
 663                 "Scratch: %d bytes per wave\n"
 664                 "Max Waves: %d\n"
 665                 "********************\n\n\n",
 666                 conf->num_sgprs, conf->num_vgprs,
 667                 conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
 668                 conf->lds_size, conf->scratch_bytes_per_wave,
 669                 max_simd_waves);
 670 }