2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
62 .lower_bitfield_insert_to_bitfield_select
= true,
63 .lower_bitfield_extract
= true,
65 .lower_pack_snorm_2x16
= true,
66 .lower_pack_snorm_4x8
= true,
67 .lower_pack_unorm_2x16
= true,
68 .lower_pack_unorm_4x8
= true,
69 .lower_unpack_snorm_2x16
= true,
70 .lower_unpack_snorm_4x8
= true,
71 .lower_unpack_unorm_2x16
= true,
72 .lower_unpack_unorm_4x8
= true,
73 .lower_extract_byte
= true,
74 .lower_extract_word
= true,
77 .lower_mul_2x32_64
= true,
79 .max_unroll_iterations
= 32
82 VkResult
radv_CreateShaderModule(
84 const VkShaderModuleCreateInfo
* pCreateInfo
,
85 const VkAllocationCallbacks
* pAllocator
,
86 VkShaderModule
* pShaderModule
)
88 RADV_FROM_HANDLE(radv_device
, device
, _device
);
89 struct radv_shader_module
*module
;
91 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
92 assert(pCreateInfo
->flags
== 0);
94 module
= vk_alloc2(&device
->alloc
, pAllocator
,
95 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
96 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
98 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
101 module
->size
= pCreateInfo
->codeSize
;
102 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
104 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
106 *pShaderModule
= radv_shader_module_to_handle(module
);
111 void radv_DestroyShaderModule(
113 VkShaderModule _module
,
114 const VkAllocationCallbacks
* pAllocator
)
116 RADV_FROM_HANDLE(radv_device
, device
, _device
);
117 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
122 vk_free2(&device
->alloc
, pAllocator
, module
);
126 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
130 unsigned lower_flrp
=
131 (shader
->options
->lower_flrp16
? 16 : 0) |
132 (shader
->options
->lower_flrp32
? 32 : 0) |
133 (shader
->options
->lower_flrp64
? 64 : 0);
138 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
139 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
141 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
142 NIR_PASS_V(shader
, nir_lower_pack
);
145 /* Only run this pass in the first call to
146 * radv_optimize_nir. Later calls assume that we've
147 * lowered away any copy_deref instructions and we
148 * don't want to introduce any more.
150 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
153 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
154 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
156 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
);
157 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
159 NIR_PASS(progress
, shader
, nir_copy_prop
);
160 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
161 NIR_PASS(progress
, shader
, nir_opt_dce
);
162 if (nir_opt_trivial_continues(shader
)) {
164 NIR_PASS(progress
, shader
, nir_copy_prop
);
165 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
166 NIR_PASS(progress
, shader
, nir_opt_dce
);
168 NIR_PASS(progress
, shader
, nir_opt_if
, true);
169 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
170 NIR_PASS(progress
, shader
, nir_opt_cse
);
171 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
172 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
173 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
175 if (lower_flrp
!= 0) {
176 bool lower_flrp_progress
= false;
177 NIR_PASS(lower_flrp_progress
,
181 false /* always_precise */,
182 shader
->options
->lower_ffma
);
183 if (lower_flrp_progress
) {
184 NIR_PASS(progress
, shader
,
185 nir_opt_constant_folding
);
189 /* Nothing should rematerialize any flrps, so we only
190 * need to do this lowering once.
195 NIR_PASS(progress
, shader
, nir_opt_undef
);
196 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
197 if (shader
->options
->max_unroll_iterations
) {
198 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
200 } while (progress
&& !optimize_conservatively
);
202 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
203 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
207 radv_shader_compile_to_nir(struct radv_device
*device
,
208 struct radv_shader_module
*module
,
209 const char *entrypoint_name
,
210 gl_shader_stage stage
,
211 const VkSpecializationInfo
*spec_info
,
212 const VkPipelineCreateFlags flags
,
213 const struct radv_pipeline_layout
*layout
)
217 /* Some things such as our meta clear/blit code will give us a NIR
218 * shader directly. In that case, we just ignore the SPIR-V entirely
219 * and just use the NIR shader */
221 nir
->options
= &nir_options
;
222 nir_validate_shader(nir
, "in internal shader");
224 assert(exec_list_length(&nir
->functions
) == 1);
226 uint32_t *spirv
= (uint32_t *) module
->data
;
227 assert(module
->size
% 4 == 0);
229 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
230 radv_print_spirv(spirv
, module
->size
, stderr
);
232 uint32_t num_spec_entries
= 0;
233 struct nir_spirv_specialization
*spec_entries
= NULL
;
234 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
235 num_spec_entries
= spec_info
->mapEntryCount
;
236 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
237 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
238 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
239 const void *data
= spec_info
->pData
+ entry
.offset
;
240 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
242 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
243 if (spec_info
->dataSize
== 8)
244 spec_entries
[i
].data64
= *(const uint64_t *)data
;
246 spec_entries
[i
].data32
= *(const uint32_t *)data
;
249 const struct spirv_to_nir_options spirv_options
= {
250 .lower_ubo_ssbo_access_to_offsets
= true,
252 .amd_gcn_shader
= true,
253 .amd_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
,
254 .amd_trinary_minmax
= true,
255 .derivative_group
= true,
256 .descriptor_array_dynamic_indexing
= true,
257 .descriptor_array_non_uniform_indexing
= true,
258 .descriptor_indexing
= true,
259 .device_group
= true,
260 .draw_parameters
= true,
263 .geometry_streams
= true,
264 .image_read_without_format
= true,
265 .image_write_without_format
= true,
269 .int64_atomics
= true,
271 .physical_storage_buffer_address
= true,
272 .runtime_descriptor_array
= true,
273 .shader_viewport_index_layer
= true,
274 .stencil_export
= true,
275 .storage_8bit
= true,
276 .storage_16bit
= true,
277 .storage_image_ms
= true,
278 .subgroup_arithmetic
= true,
279 .subgroup_ballot
= true,
280 .subgroup_basic
= true,
281 .subgroup_quad
= true,
282 .subgroup_shuffle
= true,
283 .subgroup_vote
= true,
284 .tessellation
= true,
285 .transform_feedback
= true,
286 .variable_pointers
= true,
288 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
289 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
290 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
291 .push_const_addr_format
= nir_address_format_logical
,
292 .shared_addr_format
= nir_address_format_32bit_offset
,
294 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
295 spec_entries
, num_spec_entries
,
296 stage
, entrypoint_name
,
297 &spirv_options
, &nir_options
);
298 assert(nir
->info
.stage
== stage
);
299 nir_validate_shader(nir
, "after spirv_to_nir");
303 /* We have to lower away local constant initializers right before we
304 * inline functions. That way they get properly initialized at the top
305 * of the function and not at the top of its caller.
307 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
308 NIR_PASS_V(nir
, nir_lower_returns
);
309 NIR_PASS_V(nir
, nir_inline_functions
);
310 NIR_PASS_V(nir
, nir_opt_deref
);
312 /* Pick off the single entrypoint that we want */
313 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
314 if (func
->is_entrypoint
)
315 func
->name
= ralloc_strdup(func
, "main");
317 exec_node_remove(&func
->node
);
319 assert(exec_list_length(&nir
->functions
) == 1);
321 /* Make sure we lower constant initializers on output variables so that
322 * nir_remove_dead_variables below sees the corresponding stores
324 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
326 /* Now that we've deleted all but the main function, we can go ahead and
327 * lower the rest of the constant initializers.
329 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
331 /* Split member structs. We do this before lower_io_to_temporaries so that
332 * it doesn't lower system values to temporaries by accident.
334 NIR_PASS_V(nir
, nir_split_var_copies
);
335 NIR_PASS_V(nir
, nir_split_per_member_structs
);
337 NIR_PASS_V(nir
, nir_remove_dead_variables
,
338 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
340 NIR_PASS_V(nir
, nir_lower_system_values
);
341 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
342 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
345 /* Vulkan uses the separate-shader linking model */
346 nir
->info
.separate_shader
= true;
348 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
350 static const nir_lower_tex_options tex_options
= {
352 .lower_tg4_offsets
= true,
355 nir_lower_tex(nir
, &tex_options
);
357 nir_lower_vars_to_ssa(nir
);
359 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
360 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
361 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
362 nir_shader_get_entrypoint(nir
), true, true);
363 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
364 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
365 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
366 nir_shader_get_entrypoint(nir
), true, false);
369 nir_split_var_copies(nir
);
371 nir_lower_global_vars_to_local(nir
);
372 nir_remove_dead_variables(nir
, nir_var_function_temp
);
373 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
375 .ballot_bit_size
= 64,
376 .lower_to_scalar
= 1,
377 .lower_subgroup_masks
= 1,
379 .lower_shuffle_to_32bit
= 1,
380 .lower_vote_eq_to_ballot
= 1,
383 nir_lower_load_const_to_scalar(nir
);
385 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
386 radv_optimize_nir(nir
, false, true);
388 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
389 * to remove any copies introduced by nir_opt_find_array_copies().
391 nir_lower_var_copies(nir
);
393 /* Indirect lowering must be called after the radv_optimize_nir() loop
394 * has been called at least once. Otherwise indirect lowering can
395 * bloat the instruction count of the loop and cause it to be
396 * considered too large for unrolling.
398 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
399 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
405 radv_alloc_shader_memory(struct radv_device
*device
,
406 struct radv_shader_variant
*shader
)
408 mtx_lock(&device
->shader_slab_mutex
);
409 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
411 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
412 if (s
->bo_offset
- offset
>= shader
->code_size
) {
413 shader
->bo
= slab
->bo
;
414 shader
->bo_offset
= offset
;
415 list_addtail(&shader
->slab_list
, &s
->slab_list
);
416 mtx_unlock(&device
->shader_slab_mutex
);
417 return slab
->ptr
+ offset
;
419 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
421 if (slab
->size
- offset
>= shader
->code_size
) {
422 shader
->bo
= slab
->bo
;
423 shader
->bo_offset
= offset
;
424 list_addtail(&shader
->slab_list
, &slab
->shaders
);
425 mtx_unlock(&device
->shader_slab_mutex
);
426 return slab
->ptr
+ offset
;
430 mtx_unlock(&device
->shader_slab_mutex
);
431 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
433 slab
->size
= 256 * 1024;
434 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
436 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
437 (device
->physical_device
->cpdma_prefetch_writes_memory
?
438 0 : RADEON_FLAG_READ_ONLY
),
439 RADV_BO_PRIORITY_SHADER
);
440 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
441 list_inithead(&slab
->shaders
);
443 mtx_lock(&device
->shader_slab_mutex
);
444 list_add(&slab
->slabs
, &device
->shader_slabs
);
446 shader
->bo
= slab
->bo
;
447 shader
->bo_offset
= 0;
448 list_add(&shader
->slab_list
, &slab
->shaders
);
449 mtx_unlock(&device
->shader_slab_mutex
);
454 radv_destroy_shader_slabs(struct radv_device
*device
)
456 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
457 device
->ws
->buffer_destroy(slab
->bo
);
460 mtx_destroy(&device
->shader_slab_mutex
);
463 /* For the UMR disassembler. */
464 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
465 #define DEBUGGER_NUM_MARKERS 5
468 radv_get_shader_binary_size(size_t code_size
)
470 return code_size
+ DEBUGGER_NUM_MARKERS
* 4;
473 static void radv_postprocess_config(const struct radv_physical_device
*pdevice
,
474 const struct ac_shader_config
*config_in
,
475 const struct radv_shader_variant_info
*info
,
476 gl_shader_stage stage
,
477 struct ac_shader_config
*config_out
)
479 bool scratch_enabled
= config_in
->scratch_bytes_per_wave
> 0;
480 unsigned vgpr_comp_cnt
= 0;
482 *config_out
= *config_in
;
484 config_out
->rsrc2
= S_00B12C_USER_SGPR(info
->num_user_sgprs
) |
485 S_00B12C_USER_SGPR_MSB_GFX9(info
->num_user_sgprs
>> 5) |
486 S_00B12C_SCRATCH_EN(scratch_enabled
) |
487 S_00B12C_SO_BASE0_EN(!!info
->info
.so
.strides
[0]) |
488 S_00B12C_SO_BASE1_EN(!!info
->info
.so
.strides
[1]) |
489 S_00B12C_SO_BASE2_EN(!!info
->info
.so
.strides
[2]) |
490 S_00B12C_SO_BASE3_EN(!!info
->info
.so
.strides
[3]) |
491 S_00B12C_SO_EN(!!info
->info
.so
.num_outputs
);
493 config_out
->rsrc1
= S_00B848_VGPRS((config_in
->num_vgprs
- 1) / 4) |
494 S_00B848_SGPRS((config_in
->num_sgprs
- 1) / 8) |
495 S_00B848_DX10_CLAMP(1) |
496 S_00B848_FLOAT_MODE(config_in
->float_mode
);
499 case MESA_SHADER_TESS_EVAL
:
500 if (info
->tes
.as_es
) {
501 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
502 vgpr_comp_cnt
= info
->info
.uses_prim_id
? 3 : 2;
504 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->info
.uses_prim_id
;
505 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
507 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
509 case MESA_SHADER_TESS_CTRL
:
510 if (pdevice
->rad_info
.chip_class
>= GFX9
) {
511 /* We need at least 2 components for LS.
512 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
513 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
515 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 2 : 1;
517 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
520 case MESA_SHADER_VERTEX
:
521 if (info
->vs
.as_ls
) {
522 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
523 /* We need at least 2 components for LS.
524 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
525 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
527 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 2 : 1;
528 } else if (info
->vs
.as_es
) {
529 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
530 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
531 vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 1 : 0;
533 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
534 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
535 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
537 if (info
->vs
.export_prim_id
) {
539 } else if (info
->info
.vs
.needs_instance_id
) {
546 case MESA_SHADER_FRAGMENT
:
547 case MESA_SHADER_GEOMETRY
:
549 case MESA_SHADER_COMPUTE
:
551 S_00B84C_TGID_X_EN(info
->info
.cs
.uses_block_id
[0]) |
552 S_00B84C_TGID_Y_EN(info
->info
.cs
.uses_block_id
[1]) |
553 S_00B84C_TGID_Z_EN(info
->info
.cs
.uses_block_id
[2]) |
554 S_00B84C_TIDIG_COMP_CNT(info
->info
.cs
.uses_thread_id
[2] ? 2 :
555 info
->info
.cs
.uses_thread_id
[1] ? 1 : 0) |
556 S_00B84C_TG_SIZE_EN(info
->info
.cs
.uses_local_invocation_idx
) |
557 S_00B84C_LDS_SIZE(config_in
->lds_size
);
560 unreachable("unsupported shader type");
564 if (pdevice
->rad_info
.chip_class
>= GFX9
&&
565 stage
== MESA_SHADER_GEOMETRY
) {
566 unsigned es_type
= info
->gs
.es_type
;
567 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
569 if (es_type
== MESA_SHADER_VERTEX
) {
570 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
571 es_vgpr_comp_cnt
= info
->info
.vs
.needs_instance_id
? 1 : 0;
572 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
573 es_vgpr_comp_cnt
= info
->info
.uses_prim_id
? 3 : 2;
575 unreachable("invalid shader ES type");
578 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
579 * VGPR[0:4] are always loaded.
581 if (info
->info
.uses_invocation_id
) {
582 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
583 } else if (info
->info
.uses_prim_id
) {
584 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
585 } else if (info
->gs
.vertices_in
>= 3) {
586 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
588 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
591 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
592 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
593 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
594 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
595 stage
== MESA_SHADER_TESS_CTRL
) {
596 config_out
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
598 config_out
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
602 static void radv_init_llvm_target()
604 LLVMInitializeAMDGPUTargetInfo();
605 LLVMInitializeAMDGPUTarget();
606 LLVMInitializeAMDGPUTargetMC();
607 LLVMInitializeAMDGPUAsmPrinter();
609 /* For inline assembly. */
610 LLVMInitializeAMDGPUAsmParser();
612 /* Workaround for bug in llvm 4.0 that causes image intrinsics
614 * https://reviews.llvm.org/D26348
616 * Workaround for bug in llvm that causes the GPU to hang in presence
617 * of nested loops because there is an exec mask issue. The proper
618 * solution is to fix LLVM but this might require a bunch of work.
619 * https://bugs.llvm.org/show_bug.cgi?id=37744
621 * "mesa" is the prefix for error messages.
623 if (HAVE_LLVM
>= 0x0800) {
624 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
625 LLVMParseCommandLineOptions(2, argv
, NULL
);
628 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
629 "-amdgpu-skip-threshold=1" };
630 LLVMParseCommandLineOptions(3, argv
, NULL
);
634 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
636 static void radv_init_llvm_once(void)
638 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
641 struct radv_shader_variant
*
642 radv_shader_variant_create(struct radv_device
*device
,
643 const struct radv_shader_binary
*binary
)
645 struct ac_shader_config config
= {0};
646 struct ac_rtld_binary rtld_binary
= {0};
647 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
651 variant
->ref_count
= 1;
653 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
654 struct ac_rtld_symbol lds_symbols
[1];
655 unsigned num_lds_symbols
= 0;
656 const char *elf_data
= (const char *)((struct radv_shader_binary_rtld
*)binary
)->data
;
657 size_t elf_size
= ((struct radv_shader_binary_rtld
*)binary
)->elf_size
;
659 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
660 binary
->stage
== MESA_SHADER_GEOMETRY
&& !binary
->is_gs_copy_shader
) {
661 /* We add this symbol even on LLVM <= 8 to ensure that
662 * shader->config.lds_size is set correctly below.
664 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
665 sym
->name
= "esgs_ring";
666 sym
->size
= 32 * 1024;
667 sym
->align
= 64 * 1024;
669 struct ac_rtld_open_info open_info
= {
670 .info
= &device
->physical_device
->rad_info
,
671 .shader_type
= binary
->stage
,
673 .elf_ptrs
= &elf_data
,
674 .elf_sizes
= &elf_size
,
675 .num_shared_lds_symbols
= num_lds_symbols
,
676 .shared_lds_symbols
= lds_symbols
,
679 if (!ac_rtld_open(&rtld_binary
, open_info
)) {
684 if (!ac_rtld_read_config(&rtld_binary
, &config
)) {
685 ac_rtld_close(&rtld_binary
);
690 if (rtld_binary
.lds_size
> 0) {
691 unsigned alloc_granularity
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
692 config
.lds_size
= align(rtld_binary
.lds_size
, alloc_granularity
) / alloc_granularity
;
695 variant
->code_size
= rtld_binary
.rx_size
;
697 assert(binary
->type
== RADV_BINARY_TYPE_LEGACY
);
698 config
= ((struct radv_shader_binary_legacy
*)binary
)->config
;
699 variant
->code_size
= radv_get_shader_binary_size(((struct radv_shader_binary_legacy
*)binary
)->code_size
);
702 variant
->info
= binary
->variant_info
;
703 radv_postprocess_config(device
->physical_device
, &config
, &binary
->variant_info
,
704 binary
->stage
, &variant
->config
);
706 void *dest_ptr
= radv_alloc_shader_memory(device
, variant
);
708 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
709 struct radv_shader_binary_rtld
* bin
= (struct radv_shader_binary_rtld
*)binary
;
710 struct ac_rtld_upload_info info
= {
711 .binary
= &rtld_binary
,
712 .rx_va
= radv_buffer_get_va(variant
->bo
) + variant
->bo_offset
,
716 if (!ac_rtld_upload(&info
)) {
717 radv_shader_variant_destroy(device
, variant
);
718 ac_rtld_close(&rtld_binary
);
722 const char *disasm_data
;
724 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm_data
, &disasm_size
)) {
725 radv_shader_variant_destroy(device
, variant
);
726 ac_rtld_close(&rtld_binary
);
730 variant
->llvm_ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->elf_size
)) : NULL
;
731 variant
->disasm_string
= malloc(disasm_size
+ 1);
732 memcpy(variant
->disasm_string
, disasm_data
, disasm_size
);
733 variant
->disasm_string
[disasm_size
] = 0;
735 ac_rtld_close(&rtld_binary
);
737 struct radv_shader_binary_legacy
* bin
= (struct radv_shader_binary_legacy
*)binary
;
738 memcpy(dest_ptr
, bin
->data
, bin
->code_size
);
740 /* Add end-of-code markers for the UMR disassembler. */
741 uint32_t *ptr32
= (uint32_t *)dest_ptr
+ bin
->code_size
/ 4;
742 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
743 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
745 variant
->llvm_ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->code_size
)) : NULL
;
746 variant
->disasm_string
= bin
->disasm_size
? strdup((const char*)(bin
->data
+ bin
->code_size
+ bin
->llvm_ir_size
)) : NULL
;
751 static struct radv_shader_variant
*
752 shader_variant_compile(struct radv_device
*device
,
753 struct radv_shader_module
*module
,
754 struct nir_shader
* const *shaders
,
756 gl_shader_stage stage
,
757 struct radv_nir_compiler_options
*options
,
759 struct radv_shader_binary
**binary_out
)
761 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
762 enum ac_target_machine_options tm_options
= 0;
763 struct ac_llvm_compiler ac_llvm
;
764 struct radv_shader_binary
*binary
= NULL
;
765 struct radv_shader_variant_info variant_info
= {0};
766 bool thread_compiler
;
768 options
->family
= chip_family
;
769 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
770 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
771 options
->dump_preoptir
= options
->dump_shader
&&
772 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
773 options
->record_llvm_ir
= device
->keep_shader_info
;
774 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
775 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
776 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
778 if (options
->supports_spill
)
779 tm_options
|= AC_TM_SUPPORTS_SPILL
;
780 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
781 tm_options
|= AC_TM_SISCHED
;
782 if (options
->check_ir
)
783 tm_options
|= AC_TM_CHECK_IR
;
784 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
785 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
787 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
788 radv_init_llvm_once();
789 radv_init_llvm_compiler(&ac_llvm
,
791 chip_family
, tm_options
);
792 if (gs_copy_shader
) {
793 assert(shader_count
== 1);
794 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
795 &variant_info
, options
);
797 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant_info
,
798 shaders
, shader_count
, options
);
800 binary
->variant_info
= variant_info
;
802 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
804 struct radv_shader_variant
*variant
= radv_shader_variant_create(device
, binary
);
810 if (device
->keep_shader_info
) {
811 if (!gs_copy_shader
&& !module
->nir
) {
812 variant
->nir
= *shaders
;
813 variant
->spirv
= (uint32_t *)module
->data
;
814 variant
->spirv_size
= module
->size
;
819 *binary_out
= binary
;
826 struct radv_shader_variant
*
827 radv_shader_variant_compile(struct radv_device
*device
,
828 struct radv_shader_module
*module
,
829 struct nir_shader
*const *shaders
,
831 struct radv_pipeline_layout
*layout
,
832 const struct radv_shader_variant_key
*key
,
833 struct radv_shader_binary
**binary_out
)
835 struct radv_nir_compiler_options options
= {0};
837 options
.layout
= layout
;
841 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
842 options
.supports_spill
= true;
844 return shader_variant_compile(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
845 &options
, false, binary_out
);
848 struct radv_shader_variant
*
849 radv_create_gs_copy_shader(struct radv_device
*device
,
850 struct nir_shader
*shader
,
851 struct radv_shader_binary
**binary_out
,
854 struct radv_nir_compiler_options options
= {0};
856 options
.key
.has_multiview_view_index
= multiview
;
858 return shader_variant_compile(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
859 &options
, true, binary_out
);
863 radv_shader_variant_destroy(struct radv_device
*device
,
864 struct radv_shader_variant
*variant
)
866 if (!p_atomic_dec_zero(&variant
->ref_count
))
869 mtx_lock(&device
->shader_slab_mutex
);
870 list_del(&variant
->slab_list
);
871 mtx_unlock(&device
->shader_slab_mutex
);
873 ralloc_free(variant
->nir
);
874 free(variant
->disasm_string
);
875 free(variant
->llvm_ir_string
);
880 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
883 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
884 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
885 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
886 case MESA_SHADER_COMPUTE
: return "Compute Shader";
887 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
888 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
890 return "Unknown shader";
895 generate_shader_stats(struct radv_device
*device
,
896 struct radv_shader_variant
*variant
,
897 gl_shader_stage stage
,
898 struct _mesa_string_buffer
*buf
)
900 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
901 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
902 struct ac_shader_config
*conf
;
903 unsigned max_simd_waves
;
904 unsigned lds_per_wave
= 0;
906 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
908 conf
= &variant
->config
;
910 if (stage
== MESA_SHADER_FRAGMENT
) {
911 lds_per_wave
= conf
->lds_size
* lds_increment
+
912 align(variant
->info
.fs
.num_interp
* 48,
914 } else if (stage
== MESA_SHADER_COMPUTE
) {
915 unsigned max_workgroup_size
=
916 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
917 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
918 DIV_ROUND_UP(max_workgroup_size
, 64);
924 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
929 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
931 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
935 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
937 if (stage
== MESA_SHADER_FRAGMENT
) {
938 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
939 "SPI_PS_INPUT_ADDR = 0x%04x\n"
940 "SPI_PS_INPUT_ENA = 0x%04x\n",
941 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
944 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
947 "Spilled SGPRs: %d\n"
948 "Spilled VGPRs: %d\n"
949 "PrivMem VGPRS: %d\n"
950 "Code Size: %d bytes\n"
952 "Scratch: %d bytes per wave\n"
954 "********************\n\n\n",
955 conf
->num_sgprs
, conf
->num_vgprs
,
956 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
957 variant
->info
.private_mem_vgprs
, variant
->code_size
,
958 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
963 radv_shader_dump_stats(struct radv_device
*device
,
964 struct radv_shader_variant
*variant
,
965 gl_shader_stage stage
,
968 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
970 generate_shader_stats(device
, variant
, stage
, buf
);
972 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
973 fprintf(file
, "%s", buf
->buf
);
975 _mesa_string_buffer_destroy(buf
);
979 radv_GetShaderInfoAMD(VkDevice _device
,
980 VkPipeline _pipeline
,
981 VkShaderStageFlagBits shaderStage
,
982 VkShaderInfoTypeAMD infoType
,
986 RADV_FROM_HANDLE(radv_device
, device
, _device
);
987 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
988 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
989 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
990 struct _mesa_string_buffer
*buf
;
991 VkResult result
= VK_SUCCESS
;
993 /* Spec doesn't indicate what to do if the stage is invalid, so just
994 * return no info for this. */
996 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
999 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
1001 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
1003 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1004 struct ac_shader_config
*conf
= &variant
->config
;
1006 VkShaderStatisticsInfoAMD statistics
= {};
1007 statistics
.shaderStageMask
= shaderStage
;
1008 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
1009 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
1010 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
1012 if (stage
== MESA_SHADER_COMPUTE
) {
1013 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
1014 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
1016 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
1017 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
1019 statistics
.computeWorkGroupSize
[0] = local_size
[0];
1020 statistics
.computeWorkGroupSize
[1] = local_size
[1];
1021 statistics
.computeWorkGroupSize
[2] = local_size
[2];
1023 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
1026 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
1027 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
1028 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
1029 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
1030 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
1032 size_t size
= *pInfoSize
;
1033 *pInfoSize
= sizeof(statistics
);
1035 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
1037 if (size
< *pInfoSize
)
1038 result
= VK_INCOMPLETE
;
1042 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
1043 buf
= _mesa_string_buffer_create(NULL
, 1024);
1045 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
1046 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
1047 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
1048 generate_shader_stats(device
, variant
, stage
, buf
);
1050 /* Need to include the null terminator. */
1051 size_t length
= buf
->length
+ 1;
1054 *pInfoSize
= length
;
1056 size_t size
= *pInfoSize
;
1057 *pInfoSize
= length
;
1059 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
1062 result
= VK_INCOMPLETE
;
1065 _mesa_string_buffer_destroy(buf
);
1068 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1069 result
= VK_ERROR_FEATURE_NOT_PRESENT
;