src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 #include "util/string_buffer.h"
  50
  51 static const struct nir_shader_compiler_options nir_options = {
  52         .vertex_id_zero_based = true,
  53         .lower_scmp = true,
  54         .lower_flrp32 = true,
  55         .lower_fsat = true,
  56         .lower_fdiv = true,
  57         .lower_sub = true,
  58         .lower_pack_snorm_2x16 = true,
  59         .lower_pack_snorm_4x8 = true,
  60         .lower_pack_unorm_2x16 = true,
  61         .lower_pack_unorm_4x8 = true,
  62         .lower_unpack_snorm_2x16 = true,
  63         .lower_unpack_snorm_4x8 = true,
  64         .lower_unpack_unorm_2x16 = true,
  65         .lower_unpack_unorm_4x8 = true,
  66         .lower_extract_byte = true,
  67         .lower_extract_word = true,
  68         .lower_ffma = true,
  69         .max_unroll_iterations = 32
  70 };
  71
  72 VkResult radv_CreateShaderModule(
  73         VkDevice                                    _device,
  74         const VkShaderModuleCreateInfo*             pCreateInfo,
  75         const VkAllocationCallbacks*                pAllocator,
  76         VkShaderModule*                             pShaderModule)
  77 {
  78         RADV_FROM_HANDLE(radv_device, device, _device);
  79         struct radv_shader_module *module;
  80
  81         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  82         assert(pCreateInfo->flags == 0);
  83
  84         module = vk_alloc2(&device->alloc, pAllocator,
  85                              sizeof(*module) + pCreateInfo->codeSize, 8,
  86                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  87         if (module == NULL)
  88                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  89
  90         module->nir = NULL;
  91         module->size = pCreateInfo->codeSize;
  92         memcpy(module->data, pCreateInfo->pCode, module->size);
  93
  94         _mesa_sha1_compute(module->data, module->size, module->sha1);
  95
  96         *pShaderModule = radv_shader_module_to_handle(module);
  97
  98         return VK_SUCCESS;
  99 }
 100
 101 void radv_DestroyShaderModule(
 102         VkDevice                                    _device,
 103         VkShaderModule                              _module,
 104         const VkAllocationCallbacks*                pAllocator)
 105 {
 106         RADV_FROM_HANDLE(radv_device, device, _device);
 107         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 108
 109         if (!module)
 110                 return;
 111
 112         vk_free2(&device->alloc, pAllocator, module);
 113 }
 114
 115 void
 116 radv_optimize_nir(struct nir_shader *shader)
 117 {
 118         bool progress;
 119
 120         do {
 121                 progress = false;
 122
 123                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 124                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 125                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 126                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 127
 128                 NIR_PASS(progress, shader, nir_copy_prop);
 129                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 130                 NIR_PASS(progress, shader, nir_opt_dce);
 131                 if (nir_opt_trivial_continues(shader)) {
 132                         progress = true;
 133                         NIR_PASS(progress, shader, nir_copy_prop);
 134                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 135                         NIR_PASS(progress, shader, nir_opt_dce);
 136                 }
 137                 NIR_PASS(progress, shader, nir_opt_if);
 138                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 139                 NIR_PASS(progress, shader, nir_opt_cse);
 140                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 141                 NIR_PASS(progress, shader, nir_opt_algebraic);
 142                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 143                 NIR_PASS(progress, shader, nir_opt_undef);
 144                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 145                 if (shader->options->max_unroll_iterations) {
 146                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 147                 }
 148         } while (progress);
 149 }
 150
 151 nir_shader *
 152 radv_shader_compile_to_nir(struct radv_device *device,
 153                            struct radv_shader_module *module,
 154                            const char *entrypoint_name,
 155                            gl_shader_stage stage,
 156                            const VkSpecializationInfo *spec_info)
 157 {
 158         if (strcmp(entrypoint_name, "main") != 0) {
 159                 radv_finishme("Multiple shaders per module not really supported");
 160         }
 161
 162         nir_shader *nir;
 163         nir_function *entry_point;
 164         if (module->nir) {
 165                 /* Some things such as our meta clear/blit code will give us a NIR
 166                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 167                  * and just use the NIR shader */
 168                 nir = module->nir;
 169                 nir->options = &nir_options;
 170                 nir_validate_shader(nir);
 171
 172                 assert(exec_list_length(&nir->functions) == 1);
 173                 struct exec_node *node = exec_list_get_head(&nir->functions);
 174                 entry_point = exec_node_data(nir_function, node, node);
 175         } else {
 176                 uint32_t *spirv = (uint32_t *) module->data;
 177                 assert(module->size % 4 == 0);
 178
 179                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 180                         radv_print_spirv(spirv, module->size, stderr);
 181
 182                 uint32_t num_spec_entries = 0;
 183                 struct nir_spirv_specialization *spec_entries = NULL;
 184                 if (spec_info && spec_info->mapEntryCount > 0) {
 185                         num_spec_entries = spec_info->mapEntryCount;
 186                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 187                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 188                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 189                                 const void *data = spec_info->pData + entry.offset;
 190                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 191
 192                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 193                                 if (spec_info->dataSize == 8)
 194                                         spec_entries[i].data64 = *(const uint64_t *)data;
 195                                 else
 196                                         spec_entries[i].data32 = *(const uint32_t *)data;
 197                         }
 198                 }
 199                 const struct nir_spirv_supported_extensions supported_ext = {
 200                         .draw_parameters = true,
 201                         .float64 = true,
 202                         .image_read_without_format = true,
 203                         .image_write_without_format = true,
 204                         .tessellation = true,
 205                         .int64 = true,
 206                         .multiview = true,
 207                         .variable_pointers = true,
 208                 };
 209                 entry_point = spirv_to_nir(spirv, module->size / 4,
 210                                            spec_entries, num_spec_entries,
 211                                            stage, entrypoint_name, &supported_ext, &nir_options);
 212                 nir = entry_point->shader;
 213                 assert(nir->info.stage == stage);
 214                 nir_validate_shader(nir);
 215
 216                 free(spec_entries);
 217
 218                 /* We have to lower away local constant initializers right before we
 219                  * inline functions.  That way they get properly initialized at the top
 220                  * of the function and not at the top of its caller.
 221                  */
 222                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 223                 NIR_PASS_V(nir, nir_lower_returns);
 224                 NIR_PASS_V(nir, nir_inline_functions);
 225
 226                 /* Pick off the single entrypoint that we want */
 227                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 228                         if (func != entry_point)
 229                                 exec_node_remove(&func->node);
 230                 }
 231                 assert(exec_list_length(&nir->functions) == 1);
 232                 entry_point->name = ralloc_strdup(entry_point, "main");
 233
 234                 NIR_PASS_V(nir, nir_remove_dead_variables,
 235                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 236
 237                 /* Now that we've deleted all but the main function, we can go ahead and
 238                  * lower the rest of the constant initializers.
 239                  */
 240                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 241                 NIR_PASS_V(nir, nir_lower_system_values);
 242                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 243         }
 244
 245         /* Vulkan uses the separate-shader linking model */
 246         nir->info.separate_shader = true;
 247
 248         nir_shader_gather_info(nir, entry_point->impl);
 249
 250         /* While it would be nice not to have this flag, we are constrained
 251          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 252          * on GFX9.
 253          */
 254         bool llvm_has_working_vgpr_indexing =
 255                 device->physical_device->rad_info.chip_class <= VI;
 256
 257         /* TODO: Indirect indexing of GS inputs is unimplemented.
 258          *
 259          * TCS and TES load inputs directly from LDS or offchip memory, so
 260          * indirect indexing is trivial.
 261          */
 262         nir_variable_mode indirect_mask = 0;
 263         if (nir->info.stage == MESA_SHADER_GEOMETRY ||
 264             (nir->info.stage != MESA_SHADER_TESS_CTRL &&
 265              nir->info.stage != MESA_SHADER_TESS_EVAL &&
 266              !llvm_has_working_vgpr_indexing)) {
 267                 indirect_mask |= nir_var_shader_in;
 268         }
 269         if (!llvm_has_working_vgpr_indexing &&
 270             nir->info.stage != MESA_SHADER_TESS_CTRL)
 271                 indirect_mask |= nir_var_shader_out;
 272
 273         /* TODO: We shouldn't need to do this, however LLVM isn't currently
 274          * smart enough to handle indirects without causing excess spilling
 275          * causing the gpu to hang.
 276          *
 277          * See the following thread for more details of the problem:
 278          * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
 279          */
 280         indirect_mask |= nir_var_local;
 281
 282         nir_lower_indirect_derefs(nir, indirect_mask);
 283
 284         static const nir_lower_tex_options tex_options = {
 285           .lower_txp = ~0,
 286         };
 287
 288         nir_lower_tex(nir, &tex_options);
 289
 290         nir_lower_vars_to_ssa(nir);
 291         nir_lower_var_copies(nir);
 292         nir_lower_global_vars_to_local(nir);
 293         nir_remove_dead_variables(nir, nir_var_local);
 294         radv_optimize_nir(nir);
 295
 296         return nir;
 297 }
 298
 299 void *
 300 radv_alloc_shader_memory(struct radv_device *device,
 301                          struct radv_shader_variant *shader)
 302 {
 303         mtx_lock(&device->shader_slab_mutex);
 304         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 305                 uint64_t offset = 0;
 306                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 307                         if (s->bo_offset - offset >= shader->code_size) {
 308                                 shader->bo = slab->bo;
 309                                 shader->bo_offset = offset;
 310                                 list_addtail(&shader->slab_list, &s->slab_list);
 311                                 mtx_unlock(&device->shader_slab_mutex);
 312                                 return slab->ptr + offset;
 313                         }
 314                         offset = align_u64(s->bo_offset + s->code_size, 256);
 315                 }
 316                 if (slab->size - offset >= shader->code_size) {
 317                         shader->bo = slab->bo;
 318                         shader->bo_offset = offset;
 319                         list_addtail(&shader->slab_list, &slab->shaders);
 320                         mtx_unlock(&device->shader_slab_mutex);
 321                         return slab->ptr + offset;
 322                 }
 323         }
 324
 325         mtx_unlock(&device->shader_slab_mutex);
 326         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 327
 328         slab->size = 256 * 1024;
 329         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 330                                              RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
 331         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 332         list_inithead(&slab->shaders);
 333
 334         mtx_lock(&device->shader_slab_mutex);
 335         list_add(&slab->slabs, &device->shader_slabs);
 336
 337         shader->bo = slab->bo;
 338         shader->bo_offset = 0;
 339         list_add(&shader->slab_list, &slab->shaders);
 340         mtx_unlock(&device->shader_slab_mutex);
 341         return slab->ptr;
 342 }
 343
 344 void
 345 radv_destroy_shader_slabs(struct radv_device *device)
 346 {
 347         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 348                 device->ws->buffer_destroy(slab->bo);
 349                 free(slab);
 350         }
 351         mtx_destroy(&device->shader_slab_mutex);
 352 }
 353
 354 static void
 355 radv_fill_shader_variant(struct radv_device *device,
 356                          struct radv_shader_variant *variant,
 357                          struct ac_shader_binary *binary,
 358                          gl_shader_stage stage)
 359 {
 360         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 361         unsigned vgpr_comp_cnt = 0;
 362
 363         if (scratch_enabled && !device->llvm_supports_spill)
 364                 radv_finishme("shader scratch support only available with LLVM 4.0");
 365
 366         variant->code_size = binary->code_size;
 367         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 368                         S_00B12C_SCRATCH_EN(scratch_enabled);
 369
 370         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 371                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 372                 S_00B848_DX10_CLAMP(1) |
 373                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 374
 375         switch (stage) {
 376         case MESA_SHADER_TESS_EVAL:
 377                 vgpr_comp_cnt = 3;
 378                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 379                 break;
 380         case MESA_SHADER_TESS_CTRL:
 381                 if (device->physical_device->rad_info.chip_class >= GFX9)
 382                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 383                 else
 384                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 385                 break;
 386         case MESA_SHADER_VERTEX:
 387         case MESA_SHADER_GEOMETRY:
 388                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 389                 break;
 390         case MESA_SHADER_FRAGMENT:
 391                 break;
 392         case MESA_SHADER_COMPUTE:
 393                 variant->rsrc2 |=
 394                         S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 395                         S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 396                         S_00B84C_TG_SIZE_EN(1) |
 397                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 398                 break;
 399         default:
 400                 unreachable("unsupported shader type");
 401                 break;
 402         }
 403
 404         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 405             stage == MESA_SHADER_GEOMETRY) {
 406                 /* TODO: Figure out how many we actually need. */
 407                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(3);
 408                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
 409                                   S_00B22C_OC_LDS_EN(1);
 410         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 411             stage == MESA_SHADER_TESS_CTRL)
 412                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 413         else
 414                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 415
 416         void *ptr = radv_alloc_shader_memory(device, variant);
 417         memcpy(ptr, binary->code, binary->code_size);
 418 }
 419
 420 static struct radv_shader_variant *
 421 shader_variant_create(struct radv_device *device,
 422                       struct radv_shader_module *module,
 423                       struct nir_shader * const *shaders,
 424                       int shader_count,
 425                       gl_shader_stage stage,
 426                       struct ac_nir_compiler_options *options,
 427                       bool gs_copy_shader,
 428                       void **code_out,
 429                       unsigned *code_size_out)
 430 {
 431         enum radeon_family chip_family = device->physical_device->rad_info.family;
 432         bool dump_shaders = radv_can_dump_shader(device, module);
 433         enum ac_target_machine_options tm_options = 0;
 434         struct radv_shader_variant *variant;
 435         struct ac_shader_binary binary;
 436         LLVMTargetMachineRef tm;
 437
 438         variant = calloc(1, sizeof(struct radv_shader_variant));
 439         if (!variant)
 440                 return NULL;
 441
 442         options->family = chip_family;
 443         options->chip_class = device->physical_device->rad_info.chip_class;
 444
 445         if (options->supports_spill)
 446                 tm_options |= AC_TM_SUPPORTS_SPILL;
 447         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 448                 tm_options |= AC_TM_SISCHED;
 449         tm = ac_create_target_machine(chip_family, tm_options);
 450
 451         if (gs_copy_shader) {
 452                 assert(shader_count == 1);
 453                 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
 454                                          &variant->info, options, dump_shaders);
 455         } else {
 456                 ac_compile_nir_shader(tm, &binary, &variant->config,
 457                                       &variant->info, shaders, shader_count, options,
 458                                       dump_shaders);
 459         }
 460
 461         LLVMDisposeTargetMachine(tm);
 462
 463         radv_fill_shader_variant(device, variant, &binary, stage);
 464
 465         if (code_out) {
 466                 *code_out = binary.code;
 467                 *code_size_out = binary.code_size;
 468         } else
 469                 free(binary.code);
 470         free(binary.config);
 471         free(binary.rodata);
 472         free(binary.global_symbol_offsets);
 473         free(binary.relocs);
 474         variant->ref_count = 1;
 475
 476         if (device->keep_shader_info) {
 477                 variant->disasm_string = binary.disasm_string;
 478                 if (!gs_copy_shader && !module->nir) {
 479                         variant->nir = *shaders;
 480                         variant->spirv = (uint32_t *)module->data;
 481                         variant->spirv_size = module->size;
 482                 }
 483         } else {
 484                 free(binary.disasm_string);
 485         }
 486
 487         return variant;
 488 }
 489
 490 struct radv_shader_variant *
 491 radv_shader_variant_create(struct radv_device *device,
 492                            struct radv_shader_module *module,
 493                            struct nir_shader *const *shaders,
 494                            int shader_count,
 495                            struct radv_pipeline_layout *layout,
 496                            const struct ac_shader_variant_key *key,
 497                            void **code_out,
 498                            unsigned *code_size_out)
 499 {
 500         struct ac_nir_compiler_options options = {0};
 501
 502         options.layout = layout;
 503         if (key)
 504                 options.key = *key;
 505
 506         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 507         options.supports_spill = device->llvm_supports_spill;
 508
 509         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 510                                      &options, false, code_out, code_size_out);
 511 }
 512
 513 struct radv_shader_variant *
 514 radv_create_gs_copy_shader(struct radv_device *device,
 515                            struct nir_shader *shader,
 516                            void **code_out,
 517                            unsigned *code_size_out,
 518                            bool multiview)
 519 {
 520         struct ac_nir_compiler_options options = {0};
 521
 522         options.key.has_multiview_view_index = multiview;
 523
 524         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 525                                      &options, true, code_out, code_size_out);
 526 }
 527
 528 void
 529 radv_shader_variant_destroy(struct radv_device *device,
 530                             struct radv_shader_variant *variant)
 531 {
 532         if (!p_atomic_dec_zero(&variant->ref_count))
 533                 return;
 534
 535         mtx_lock(&device->shader_slab_mutex);
 536         list_del(&variant->slab_list);
 537         mtx_unlock(&device->shader_slab_mutex);
 538
 539         ralloc_free(variant->nir);
 540         free(variant->disasm_string);
 541         free(variant);
 542 }
 543
 544 const char *
 545 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 546 {
 547         switch (stage) {
 548         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 549         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 550         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 551         case MESA_SHADER_COMPUTE: return "Compute Shader";
 552         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 553         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 554         default:
 555                 return "Unknown shader";
 556         };
 557 }
 558
 559 static uint32_t
 560 get_total_sgprs(struct radv_device *device)
 561 {
 562         if (device->physical_device->rad_info.chip_class >= VI)
 563                 return 800;
 564         else
 565                 return 512;
 566 }
 567
 568 static void
 569 generate_shader_stats(struct radv_device *device,
 570                       struct radv_shader_variant *variant,
 571                       gl_shader_stage stage,
 572                       struct _mesa_string_buffer *buf)
 573 {
 574         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 575         struct ac_shader_config *conf;
 576         unsigned max_simd_waves;
 577         unsigned lds_per_wave = 0;
 578
 579         switch (device->physical_device->rad_info.family) {
 580         /* These always have 8 waves: */
 581         case CHIP_POLARIS10:
 582         case CHIP_POLARIS11:
 583         case CHIP_POLARIS12:
 584                 max_simd_waves = 8;
 585                 break;
 586         default:
 587                 max_simd_waves = 10;
 588         }
 589
 590         conf = &variant->config;
 591
 592         if (stage == MESA_SHADER_FRAGMENT) {
 593                 lds_per_wave = conf->lds_size * lds_increment +
 594                                align(variant->info.fs.num_interp * 48,
 595                                      lds_increment);
 596         }
 597
 598         if (conf->num_sgprs)
 599                 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
 600
 601         if (conf->num_vgprs)
 602                 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 603
 604         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 605          * that PS can use.
 606          */
 607         if (lds_per_wave)
 608                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 609
 610         if (stage == MESA_SHADER_FRAGMENT) {
 611                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 612                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 613                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 614                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 615         }
 616
 617         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 618                                    "SGPRS: %d\n"
 619                                    "VGPRS: %d\n"
 620                                    "Spilled SGPRs: %d\n"
 621                                    "Spilled VGPRs: %d\n"
 622                                    "Code Size: %d bytes\n"
 623                                    "LDS: %d blocks\n"
 624                                    "Scratch: %d bytes per wave\n"
 625                                    "Max Waves: %d\n"
 626                                    "********************\n\n\n",
 627                                    conf->num_sgprs, conf->num_vgprs,
 628                                    conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
 629                                    conf->lds_size, conf->scratch_bytes_per_wave,
 630                                    max_simd_waves);
 631 }
 632
 633 void
 634 radv_shader_dump_stats(struct radv_device *device,
 635                        struct radv_shader_variant *variant,
 636                        gl_shader_stage stage,
 637                        FILE *file)
 638 {
 639         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 640
 641         generate_shader_stats(device, variant, stage, buf);
 642
 643         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 644         fprintf(file, "%s", buf->buf);
 645
 646         _mesa_string_buffer_destroy(buf);
 647 }
 648
 649 VkResult
 650 radv_GetShaderInfoAMD(VkDevice _device,
 651                       VkPipeline _pipeline,
 652                       VkShaderStageFlagBits shaderStage,
 653                       VkShaderInfoTypeAMD infoType,
 654                       size_t* pInfoSize,
 655                       void* pInfo)
 656 {
 657         RADV_FROM_HANDLE(radv_device, device, _device);
 658         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 659         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 660         struct radv_shader_variant *variant = pipeline->shaders[stage];
 661         struct _mesa_string_buffer *buf;
 662         VkResult result = VK_SUCCESS;
 663
 664         /* Spec doesn't indicate what to do if the stage is invalid, so just
 665          * return no info for this. */
 666         if (!variant)
 667                 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
 668
 669         switch (infoType) {
 670         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 671                 if (!pInfo) {
 672                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 673                 } else {
 674                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 675                         struct ac_shader_config *conf = &variant->config;
 676
 677                         VkShaderStatisticsInfoAMD statistics = {};
 678                         statistics.shaderStageMask = shaderStage;
 679                         statistics.numPhysicalVgprs = 256;
 680                         statistics.numPhysicalSgprs = get_total_sgprs(device);
 681                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 682
 683                         if (stage == MESA_SHADER_COMPUTE) {
 684                                 unsigned *local_size = variant->nir->info.cs.local_size;
 685                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 686
 687                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 688                                                                ceil(workgroup_size / statistics.numPhysicalVgprs);
 689
 690                                 statistics.computeWorkGroupSize[0] = local_size[0];
 691                                 statistics.computeWorkGroupSize[1] = local_size[1];
 692                                 statistics.computeWorkGroupSize[2] = local_size[2];
 693                         } else {
 694                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 695                         }
 696
 697                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 698                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 699                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 700                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 701                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 702
 703                         size_t size = *pInfoSize;
 704                         *pInfoSize = sizeof(statistics);
 705
 706                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 707
 708                         if (size < *pInfoSize)
 709                                 result = VK_INCOMPLETE;
 710                 }
 711
 712                 break;
 713         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 714                 buf = _mesa_string_buffer_create(NULL, 1024);
 715
 716                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 717                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 718                 generate_shader_stats(device, variant, stage, buf);
 719
 720                 /* Need to include the null terminator. */
 721                 size_t length = buf->length + 1;
 722
 723                 if (!pInfo) {
 724                         *pInfoSize = length;
 725                 } else {
 726                         size_t size = *pInfoSize;
 727                         *pInfoSize = length;
 728
 729                         memcpy(pInfo, buf->buf, MIN2(size, length));
 730
 731                         if (size < length)
 732                                 result = VK_INCOMPLETE;
 733                 }
 734
 735                 _mesa_string_buffer_destroy(buf);
 736                 break;
 737         default:
 738                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 739                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 740                 break;
 741         }
 742
 743         return result;
 744 }