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radv: fix dumping disassembly with RADV_DEBUG=shaders
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp16 = true,
57 .lower_flrp32 = true,
58 .lower_flrp64 = true,
59 .lower_device_index_to_zero = true,
60 .lower_fsat = true,
61 .lower_fdiv = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 };
82
83 VkResult radv_CreateShaderModule(
84 VkDevice _device,
85 const VkShaderModuleCreateInfo* pCreateInfo,
86 const VkAllocationCallbacks* pAllocator,
87 VkShaderModule* pShaderModule)
88 {
89 RADV_FROM_HANDLE(radv_device, device, _device);
90 struct radv_shader_module *module;
91
92 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
93 assert(pCreateInfo->flags == 0);
94
95 module = vk_alloc2(&device->alloc, pAllocator,
96 sizeof(*module) + pCreateInfo->codeSize, 8,
97 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
98 if (module == NULL)
99 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
100
101 module->nir = NULL;
102 module->size = pCreateInfo->codeSize;
103 memcpy(module->data, pCreateInfo->pCode, module->size);
104
105 _mesa_sha1_compute(module->data, module->size, module->sha1);
106
107 *pShaderModule = radv_shader_module_to_handle(module);
108
109 return VK_SUCCESS;
110 }
111
112 void radv_DestroyShaderModule(
113 VkDevice _device,
114 VkShaderModule _module,
115 const VkAllocationCallbacks* pAllocator)
116 {
117 RADV_FROM_HANDLE(radv_device, device, _device);
118 RADV_FROM_HANDLE(radv_shader_module, module, _module);
119
120 if (!module)
121 return;
122
123 vk_free2(&device->alloc, pAllocator, module);
124 }
125
126 void
127 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
128 bool allow_copies)
129 {
130 bool progress;
131 unsigned lower_flrp =
132 (shader->options->lower_flrp16 ? 16 : 0) |
133 (shader->options->lower_flrp32 ? 32 : 0) |
134 (shader->options->lower_flrp64 ? 64 : 0);
135
136 do {
137 progress = false;
138
139 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
140 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
141
142 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
143 NIR_PASS_V(shader, nir_lower_pack);
144
145 if (allow_copies) {
146 /* Only run this pass in the first call to
147 * radv_optimize_nir. Later calls assume that we've
148 * lowered away any copy_deref instructions and we
149 * don't want to introduce any more.
150 */
151 NIR_PASS(progress, shader, nir_opt_find_array_copies);
152 }
153
154 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
155 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
156
157 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
158 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
159
160 NIR_PASS(progress, shader, nir_copy_prop);
161 NIR_PASS(progress, shader, nir_opt_remove_phis);
162 NIR_PASS(progress, shader, nir_opt_dce);
163 if (nir_opt_trivial_continues(shader)) {
164 progress = true;
165 NIR_PASS(progress, shader, nir_copy_prop);
166 NIR_PASS(progress, shader, nir_opt_remove_phis);
167 NIR_PASS(progress, shader, nir_opt_dce);
168 }
169 NIR_PASS(progress, shader, nir_opt_if, true);
170 NIR_PASS(progress, shader, nir_opt_dead_cf);
171 NIR_PASS(progress, shader, nir_opt_cse);
172 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
173 NIR_PASS(progress, shader, nir_opt_constant_folding);
174 NIR_PASS(progress, shader, nir_opt_algebraic);
175
176 if (lower_flrp != 0) {
177 bool lower_flrp_progress = false;
178 NIR_PASS(lower_flrp_progress,
179 shader,
180 nir_lower_flrp,
181 lower_flrp,
182 false /* always_precise */,
183 shader->options->lower_ffma);
184 if (lower_flrp_progress) {
185 NIR_PASS(progress, shader,
186 nir_opt_constant_folding);
187 progress = true;
188 }
189
190 /* Nothing should rematerialize any flrps, so we only
191 * need to do this lowering once.
192 */
193 lower_flrp = 0;
194 }
195
196 NIR_PASS(progress, shader, nir_opt_undef);
197 if (shader->options->max_unroll_iterations) {
198 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
199 }
200 } while (progress && !optimize_conservatively);
201
202 NIR_PASS(progress, shader, nir_opt_conditional_discard);
203 NIR_PASS(progress, shader, nir_opt_shrink_load);
204 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
205 }
206
207 nir_shader *
208 radv_shader_compile_to_nir(struct radv_device *device,
209 struct radv_shader_module *module,
210 const char *entrypoint_name,
211 gl_shader_stage stage,
212 const VkSpecializationInfo *spec_info,
213 const VkPipelineCreateFlags flags,
214 const struct radv_pipeline_layout *layout)
215 {
216 nir_shader *nir;
217 if (module->nir) {
218 /* Some things such as our meta clear/blit code will give us a NIR
219 * shader directly. In that case, we just ignore the SPIR-V entirely
220 * and just use the NIR shader */
221 nir = module->nir;
222 nir->options = &nir_options;
223 nir_validate_shader(nir, "in internal shader");
224
225 assert(exec_list_length(&nir->functions) == 1);
226 } else {
227 uint32_t *spirv = (uint32_t *) module->data;
228 assert(module->size % 4 == 0);
229
230 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
231 radv_print_spirv(spirv, module->size, stderr);
232
233 uint32_t num_spec_entries = 0;
234 struct nir_spirv_specialization *spec_entries = NULL;
235 if (spec_info && spec_info->mapEntryCount > 0) {
236 num_spec_entries = spec_info->mapEntryCount;
237 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
238 for (uint32_t i = 0; i < num_spec_entries; i++) {
239 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
240 const void *data = spec_info->pData + entry.offset;
241 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
242
243 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
244 if (spec_info->dataSize == 8)
245 spec_entries[i].data64 = *(const uint64_t *)data;
246 else
247 spec_entries[i].data32 = *(const uint32_t *)data;
248 }
249 }
250 const struct spirv_to_nir_options spirv_options = {
251 .lower_ubo_ssbo_access_to_offsets = true,
252 .caps = {
253 .amd_gcn_shader = true,
254 .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT,
255 .amd_trinary_minmax = true,
256 .derivative_group = true,
257 .descriptor_array_dynamic_indexing = true,
258 .descriptor_array_non_uniform_indexing = true,
259 .descriptor_indexing = true,
260 .device_group = true,
261 .draw_parameters = true,
262 .float16 = true,
263 .float64 = true,
264 .geometry_streams = true,
265 .image_read_without_format = true,
266 .image_write_without_format = true,
267 .int8 = true,
268 .int16 = true,
269 .int64 = true,
270 .int64_atomics = true,
271 .multiview = true,
272 .physical_storage_buffer_address = true,
273 .post_depth_coverage = true,
274 .runtime_descriptor_array = true,
275 .shader_viewport_index_layer = true,
276 .stencil_export = true,
277 .storage_8bit = true,
278 .storage_16bit = true,
279 .storage_image_ms = true,
280 .subgroup_arithmetic = true,
281 .subgroup_ballot = true,
282 .subgroup_basic = true,
283 .subgroup_quad = true,
284 .subgroup_shuffle = true,
285 .subgroup_vote = true,
286 .tessellation = true,
287 .transform_feedback = true,
288 .variable_pointers = true,
289 },
290 .ubo_addr_format = nir_address_format_32bit_index_offset,
291 .ssbo_addr_format = nir_address_format_32bit_index_offset,
292 .phys_ssbo_addr_format = nir_address_format_64bit_global,
293 .push_const_addr_format = nir_address_format_logical,
294 .shared_addr_format = nir_address_format_32bit_offset,
295 .frag_coord_is_sysval = true,
296 };
297 nir = spirv_to_nir(spirv, module->size / 4,
298 spec_entries, num_spec_entries,
299 stage, entrypoint_name,
300 &spirv_options, &nir_options);
301 assert(nir->info.stage == stage);
302 nir_validate_shader(nir, "after spirv_to_nir");
303
304 free(spec_entries);
305
306 /* We have to lower away local constant initializers right before we
307 * inline functions. That way they get properly initialized at the top
308 * of the function and not at the top of its caller.
309 */
310 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
311 NIR_PASS_V(nir, nir_lower_returns);
312 NIR_PASS_V(nir, nir_inline_functions);
313 NIR_PASS_V(nir, nir_opt_deref);
314
315 /* Pick off the single entrypoint that we want */
316 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
317 if (func->is_entrypoint)
318 func->name = ralloc_strdup(func, "main");
319 else
320 exec_node_remove(&func->node);
321 }
322 assert(exec_list_length(&nir->functions) == 1);
323
324 /* Make sure we lower constant initializers on output variables so that
325 * nir_remove_dead_variables below sees the corresponding stores
326 */
327 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
328
329 /* Now that we've deleted all but the main function, we can go ahead and
330 * lower the rest of the constant initializers.
331 */
332 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
333
334 /* Split member structs. We do this before lower_io_to_temporaries so that
335 * it doesn't lower system values to temporaries by accident.
336 */
337 NIR_PASS_V(nir, nir_split_var_copies);
338 NIR_PASS_V(nir, nir_split_per_member_structs);
339
340 if (nir->info.stage == MESA_SHADER_FRAGMENT)
341 NIR_PASS_V(nir, nir_lower_input_attachments, true);
342
343 NIR_PASS_V(nir, nir_remove_dead_variables,
344 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
345
346 NIR_PASS_V(nir, nir_lower_system_values);
347 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
348 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
349 }
350
351 /* Vulkan uses the separate-shader linking model */
352 nir->info.separate_shader = true;
353
354 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
355
356 static const nir_lower_tex_options tex_options = {
357 .lower_txp = ~0,
358 .lower_tg4_offsets = true,
359 };
360
361 nir_lower_tex(nir, &tex_options);
362
363 nir_lower_vars_to_ssa(nir);
364
365 if (nir->info.stage == MESA_SHADER_VERTEX ||
366 nir->info.stage == MESA_SHADER_GEOMETRY ||
367 nir->info.stage == MESA_SHADER_FRAGMENT) {
368 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
369 nir_shader_get_entrypoint(nir), true, true);
370 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
371 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
372 nir_shader_get_entrypoint(nir), true, false);
373 }
374
375 nir_split_var_copies(nir);
376
377 nir_lower_global_vars_to_local(nir);
378 nir_remove_dead_variables(nir, nir_var_function_temp);
379 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
380 .subgroup_size = 64,
381 .ballot_bit_size = 64,
382 .lower_to_scalar = 1,
383 .lower_subgroup_masks = 1,
384 .lower_shuffle = 1,
385 .lower_shuffle_to_32bit = 1,
386 .lower_vote_eq_to_ballot = 1,
387 });
388
389 nir_lower_load_const_to_scalar(nir);
390
391 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
392 radv_optimize_nir(nir, false, true);
393
394 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
395 * to remove any copies introduced by nir_opt_find_array_copies().
396 */
397 nir_lower_var_copies(nir);
398
399 /* Indirect lowering must be called after the radv_optimize_nir() loop
400 * has been called at least once. Otherwise indirect lowering can
401 * bloat the instruction count of the loop and cause it to be
402 * considered too large for unrolling.
403 */
404 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
405 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
406
407 return nir;
408 }
409
410 static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info,
411 const struct glsl_type *type,
412 int location)
413 {
414 if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
415 unsigned attrib_count = glsl_count_attribute_slots(type, false);
416 if (glsl_type_is_16bit(type)) {
417 shader_info->fs.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
418 }
419 } else if (glsl_type_is_array(type)) {
420 unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
421 for (unsigned i = 0; i < glsl_get_length(type); ++i) {
422 mark_16bit_fs_input(shader_info, glsl_get_array_element(type), location + i * stride);
423 }
424 } else {
425 assert(glsl_type_is_struct_or_ifc(type));
426 for (unsigned i = 0; i < glsl_get_length(type); i++) {
427 mark_16bit_fs_input(shader_info, glsl_get_struct_field(type, i), location);
428 location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
429 }
430 }
431 }
432
433 static void
434 handle_fs_input_decl(struct radv_shader_variant_info *shader_info,
435 struct nir_variable *variable)
436 {
437 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
438
439 if (variable->data.compact) {
440 unsigned component_count = variable->data.location_frac +
441 glsl_get_length(variable->type);
442 attrib_count = (component_count + 3) / 4;
443 } else {
444 mark_16bit_fs_input(shader_info, variable->type,
445 variable->data.driver_location);
446 }
447
448 uint64_t mask = ((1ull << attrib_count) - 1);
449
450 if (variable->data.interpolation == INTERP_MODE_FLAT)
451 shader_info->fs.flat_shaded_mask |= mask << variable->data.driver_location;
452
453 if (variable->data.location >= VARYING_SLOT_VAR0)
454 shader_info->fs.input_mask |= mask << (variable->data.location - VARYING_SLOT_VAR0);
455 }
456
457 static int
458 type_size_vec4(const struct glsl_type *type, bool bindless)
459 {
460 return glsl_count_attribute_slots(type, false);
461 }
462
463 static nir_variable *
464 find_layer_in_var(nir_shader *nir)
465 {
466 nir_foreach_variable(var, &nir->inputs) {
467 if (var->data.location == VARYING_SLOT_LAYER) {
468 return var;
469 }
470 }
471
472 nir_variable *var =
473 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
474 var->data.location = VARYING_SLOT_LAYER;
475 var->data.interpolation = INTERP_MODE_FLAT;
476 return var;
477 }
478
479 /* We use layered rendering to implement multiview, which means we need to map
480 * view_index to gl_Layer. The attachment lowering also uses needs to know the
481 * layer so that it can sample from the correct layer. The code generates a
482 * load from the layer_id sysval, but since we don't have a way to get at this
483 * information from the fragment shader, we also need to lower this to the
484 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
485 * slot, before lowering io, so that nir_assign_var_locations() will give the
486 * LAYER varying the correct driver_location.
487 */
488
489 static bool
490 lower_view_index(nir_shader *nir)
491 {
492 bool progress = false;
493 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
494 nir_builder b;
495 nir_builder_init(&b, entry);
496
497 nir_variable *layer = NULL;
498 nir_foreach_block(block, entry) {
499 nir_foreach_instr_safe(instr, block) {
500 if (instr->type != nir_instr_type_intrinsic)
501 continue;
502
503 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
504 if (load->intrinsic != nir_intrinsic_load_view_index &&
505 load->intrinsic != nir_intrinsic_load_layer_id)
506 continue;
507
508 if (!layer)
509 layer = find_layer_in_var(nir);
510
511 b.cursor = nir_before_instr(instr);
512 nir_ssa_def *def = nir_load_var(&b, layer);
513 nir_ssa_def_rewrite_uses(&load->dest.ssa,
514 nir_src_for_ssa(def));
515
516 nir_instr_remove(instr);
517 progress = true;
518 }
519 }
520
521 return progress;
522 }
523
524 /* Gather information needed to setup the vs<->ps linking registers in
525 * radv_pipeline_generate_ps_inputs().
526 */
527
528 static void
529 handle_fs_inputs(nir_shader *nir, struct radv_shader_variant_info *shader_info)
530 {
531 shader_info->fs.num_interp = nir->num_inputs;
532
533 nir_foreach_variable(variable, &nir->inputs)
534 handle_fs_input_decl(shader_info, variable);
535 }
536
537 static void
538 lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info)
539 {
540 NIR_PASS_V(nir, lower_view_index);
541 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
542 MESA_SHADER_FRAGMENT);
543
544 handle_fs_inputs(nir, shader_info);
545
546 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
547
548 /* This pass needs actual constants */
549 nir_opt_constant_folding(nir);
550
551 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
552 }
553
554
555 void *
556 radv_alloc_shader_memory(struct radv_device *device,
557 struct radv_shader_variant *shader)
558 {
559 mtx_lock(&device->shader_slab_mutex);
560 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
561 uint64_t offset = 0;
562 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
563 if (s->bo_offset - offset >= shader->code_size) {
564 shader->bo = slab->bo;
565 shader->bo_offset = offset;
566 list_addtail(&shader->slab_list, &s->slab_list);
567 mtx_unlock(&device->shader_slab_mutex);
568 return slab->ptr + offset;
569 }
570 offset = align_u64(s->bo_offset + s->code_size, 256);
571 }
572 if (slab->size - offset >= shader->code_size) {
573 shader->bo = slab->bo;
574 shader->bo_offset = offset;
575 list_addtail(&shader->slab_list, &slab->shaders);
576 mtx_unlock(&device->shader_slab_mutex);
577 return slab->ptr + offset;
578 }
579 }
580
581 mtx_unlock(&device->shader_slab_mutex);
582 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
583
584 slab->size = 256 * 1024;
585 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
586 RADEON_DOMAIN_VRAM,
587 RADEON_FLAG_NO_INTERPROCESS_SHARING |
588 (device->physical_device->cpdma_prefetch_writes_memory ?
589 0 : RADEON_FLAG_READ_ONLY),
590 RADV_BO_PRIORITY_SHADER);
591 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
592 list_inithead(&slab->shaders);
593
594 mtx_lock(&device->shader_slab_mutex);
595 list_add(&slab->slabs, &device->shader_slabs);
596
597 shader->bo = slab->bo;
598 shader->bo_offset = 0;
599 list_add(&shader->slab_list, &slab->shaders);
600 mtx_unlock(&device->shader_slab_mutex);
601 return slab->ptr;
602 }
603
604 void
605 radv_destroy_shader_slabs(struct radv_device *device)
606 {
607 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
608 device->ws->buffer_destroy(slab->bo);
609 free(slab);
610 }
611 mtx_destroy(&device->shader_slab_mutex);
612 }
613
614 /* For the UMR disassembler. */
615 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
616 #define DEBUGGER_NUM_MARKERS 5
617
618 static unsigned
619 radv_get_shader_binary_size(size_t code_size)
620 {
621 return code_size + DEBUGGER_NUM_MARKERS * 4;
622 }
623
624 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
625 const struct ac_shader_config *config_in,
626 const struct radv_shader_variant_info *info,
627 gl_shader_stage stage,
628 struct ac_shader_config *config_out)
629 {
630 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
631 unsigned vgpr_comp_cnt = 0;
632 unsigned num_input_vgprs = info->num_input_vgprs;
633
634 if (stage == MESA_SHADER_FRAGMENT) {
635 num_input_vgprs = 0;
636 if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
637 num_input_vgprs += 2;
638 if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
639 num_input_vgprs += 2;
640 if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
641 num_input_vgprs += 2;
642 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
643 num_input_vgprs += 3;
644 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
645 num_input_vgprs += 2;
646 if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
647 num_input_vgprs += 2;
648 if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
649 num_input_vgprs += 2;
650 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
651 num_input_vgprs += 1;
652 if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
653 num_input_vgprs += 1;
654 if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
655 num_input_vgprs += 1;
656 if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
657 num_input_vgprs += 1;
658 if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
659 num_input_vgprs += 1;
660 if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
661 num_input_vgprs += 1;
662 if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
663 num_input_vgprs += 1;
664 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
665 num_input_vgprs += 1;
666 if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
667 num_input_vgprs += 1;
668 }
669
670 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
671 /* +3 for scratch wave offset and VCC */
672 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
673
674 *config_out = *config_in;
675 config_out->num_vgprs = num_vgprs;
676 config_out->num_sgprs = num_sgprs;
677
678 /* Enable 64-bit and 16-bit denormals, because there is no performance
679 * cost.
680 *
681 * If denormals are enabled, all floating-point output modifiers are
682 * ignored.
683 *
684 * Don't enable denormals for 32-bit floats, because:
685 * - Floating-point output modifiers would be ignored by the hw.
686 * - Some opcodes don't support denormals, such as v_mad_f32. We would
687 * have to stop using those.
688 * - GFX6 & GFX7 would be very slow.
689 */
690 config_out->float_mode |= V_00B028_FP_64_DENORMS;
691
692 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
693 S_00B12C_SCRATCH_EN(scratch_enabled);
694
695 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / 4) |
696 S_00B848_DX10_CLAMP(1) |
697 S_00B848_FLOAT_MODE(config_out->float_mode);
698
699 if (pdevice->rad_info.chip_class >= GFX10) {
700 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
701 } else {
702 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
703 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5) |
704 S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
705 S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
706 S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
707 S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
708 S_00B12C_SO_EN(!!info->info.so.num_outputs);
709 }
710
711 switch (stage) {
712 case MESA_SHADER_TESS_EVAL:
713 if (info->is_ngg) {
714 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
715 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
716 } else if (info->tes.as_es) {
717 assert(pdevice->rad_info.chip_class <= GFX8);
718 vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
719
720 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
721 } else {
722 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
723 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
724
725 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
726 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
727 }
728 break;
729 case MESA_SHADER_TESS_CTRL:
730 if (pdevice->rad_info.chip_class >= GFX9) {
731 /* We need at least 2 components for LS.
732 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
733 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
734 */
735 if (pdevice->rad_info.chip_class >= GFX10) {
736 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 1;
737 } else {
738 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
739 }
740 } else {
741 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
742 }
743 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
744 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
745 break;
746 case MESA_SHADER_VERTEX:
747 if (info->is_ngg) {
748 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
749 } else if (info->vs.as_ls) {
750 assert(pdevice->rad_info.chip_class <= GFX8);
751 /* We need at least 2 components for LS.
752 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
753 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
754 */
755 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
756 } else if (info->vs.as_es) {
757 assert(pdevice->rad_info.chip_class <= GFX8);
758 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
759 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
760 } else {
761 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
762 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
763 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
764 */
765 if (info->vs.export_prim_id) {
766 vgpr_comp_cnt = 2;
767 } else if (info->info.vs.needs_instance_id) {
768 vgpr_comp_cnt = 1;
769 } else {
770 vgpr_comp_cnt = 0;
771 }
772
773 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
774 }
775 break;
776 case MESA_SHADER_FRAGMENT:
777 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
778 break;
779 case MESA_SHADER_GEOMETRY:
780 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
781 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
782 break;
783 case MESA_SHADER_COMPUTE:
784 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
785 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
786 config_out->rsrc2 |=
787 S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) |
788 S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) |
789 S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) |
790 S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 :
791 info->info.cs.uses_thread_id[1] ? 1 : 0) |
792 S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) |
793 S_00B84C_LDS_SIZE(config_in->lds_size);
794 break;
795 default:
796 unreachable("unsupported shader type");
797 break;
798 }
799
800 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
801 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
802 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
803 gl_shader_stage es_stage = stage;
804 if (stage == MESA_SHADER_GEOMETRY)
805 es_stage = info->gs.es_type;
806
807 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
808 if (es_stage == MESA_SHADER_VERTEX) {
809 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0;
810 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
811 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
812 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
813 } else
814 unreachable("Unexpected ES shader stage");
815
816 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
817 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
818 if (info->info.uses_invocation_id || stage == MESA_SHADER_VERTEX) {
819 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
820 } else if (info->info.uses_prim_id) {
821 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
822 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
823 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
824 } else {
825 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
826 }
827
828 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
829 S_00B228_WGP_MODE(1);
830 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
831 S_00B22C_LDS_SIZE(config_in->lds_size) |
832 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
833 } else if (pdevice->rad_info.chip_class >= GFX9 &&
834 stage == MESA_SHADER_GEOMETRY) {
835 unsigned es_type = info->gs.es_type;
836 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
837
838 if (es_type == MESA_SHADER_VERTEX) {
839 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
840 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
841 } else if (es_type == MESA_SHADER_TESS_EVAL) {
842 es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
843 } else {
844 unreachable("invalid shader ES type");
845 }
846
847 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
848 * VGPR[0:4] are always loaded.
849 */
850 if (info->info.uses_invocation_id) {
851 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
852 } else if (info->info.uses_prim_id) {
853 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
854 } else if (info->gs.vertices_in >= 3) {
855 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
856 } else {
857 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
858 }
859
860 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
861 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
862 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
863 } else if (pdevice->rad_info.chip_class >= GFX9 &&
864 stage == MESA_SHADER_TESS_CTRL) {
865 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
866 } else {
867 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
868 }
869 }
870
871 static void radv_init_llvm_target()
872 {
873 LLVMInitializeAMDGPUTargetInfo();
874 LLVMInitializeAMDGPUTarget();
875 LLVMInitializeAMDGPUTargetMC();
876 LLVMInitializeAMDGPUAsmPrinter();
877
878 /* For inline assembly. */
879 LLVMInitializeAMDGPUAsmParser();
880
881 /* Workaround for bug in llvm 4.0 that causes image intrinsics
882 * to disappear.
883 * https://reviews.llvm.org/D26348
884 *
885 * Workaround for bug in llvm that causes the GPU to hang in presence
886 * of nested loops because there is an exec mask issue. The proper
887 * solution is to fix LLVM but this might require a bunch of work.
888 * https://bugs.llvm.org/show_bug.cgi?id=37744
889 *
890 * "mesa" is the prefix for error messages.
891 */
892 if (HAVE_LLVM >= 0x0800) {
893 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
894 LLVMParseCommandLineOptions(2, argv, NULL);
895
896 } else {
897 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
898 "-amdgpu-skip-threshold=1" };
899 LLVMParseCommandLineOptions(3, argv, NULL);
900 }
901 }
902
903 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
904
905 static void radv_init_llvm_once(void)
906 {
907 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
908 }
909
910 struct radv_shader_variant *
911 radv_shader_variant_create(struct radv_device *device,
912 const struct radv_shader_binary *binary)
913 {
914 struct ac_shader_config config = {0};
915 struct ac_rtld_binary rtld_binary = {0};
916 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
917 if (!variant)
918 return NULL;
919
920 variant->ref_count = 1;
921
922 if (binary->type == RADV_BINARY_TYPE_RTLD) {
923 struct ac_rtld_symbol lds_symbols[1];
924 unsigned num_lds_symbols = 0;
925 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
926 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
927 unsigned esgs_ring_size = 0;
928
929 if (device->physical_device->rad_info.chip_class >= GFX9 &&
930 binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) {
931 /* TODO: Do not hardcode this value */
932 esgs_ring_size = 32 * 1024;
933 }
934
935 if (binary->variant_info.is_ngg) {
936 /* GS stores Primitive IDs into LDS at the address
937 * corresponding to the ES thread of the provoking
938 * vertex. All ES threads load and export PrimitiveID
939 * for their thread.
940 */
941 if (binary->stage == MESA_SHADER_VERTEX &&
942 binary->variant_info.vs.export_prim_id) {
943 /* TODO: Do not harcode this value */
944 esgs_ring_size = 256 /* max_out_verts */ * 4;
945 }
946 }
947
948 if (esgs_ring_size) {
949 /* We add this symbol even on LLVM <= 8 to ensure that
950 * shader->config.lds_size is set correctly below.
951 */
952 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
953 sym->name = "esgs_ring";
954 sym->size = esgs_ring_size;
955 sym->align = 64 * 1024;
956
957 /* Make sure to have LDS space for NGG scratch. */
958 /* TODO: Compute this correctly somehow? */
959 if (binary->variant_info.is_ngg)
960 sym->size -= 32;
961 }
962 struct ac_rtld_open_info open_info = {
963 .info = &device->physical_device->rad_info,
964 .shader_type = binary->stage,
965 .wave_size = 64,
966 .num_parts = 1,
967 .elf_ptrs = &elf_data,
968 .elf_sizes = &elf_size,
969 .num_shared_lds_symbols = num_lds_symbols,
970 .shared_lds_symbols = lds_symbols,
971 };
972
973 if (!ac_rtld_open(&rtld_binary, open_info)) {
974 free(variant);
975 return NULL;
976 }
977
978 if (!ac_rtld_read_config(&rtld_binary, &config)) {
979 ac_rtld_close(&rtld_binary);
980 free(variant);
981 return NULL;
982 }
983
984 if (rtld_binary.lds_size > 0) {
985 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
986 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
987 }
988
989 variant->code_size = rtld_binary.rx_size;
990 } else {
991 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
992 config = ((struct radv_shader_binary_legacy *)binary)->config;
993 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
994 }
995
996 variant->info = binary->variant_info;
997 radv_postprocess_config(device->physical_device, &config, &binary->variant_info,
998 binary->stage, &variant->config);
999
1000 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1001
1002 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1003 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1004 struct ac_rtld_upload_info info = {
1005 .binary = &rtld_binary,
1006 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1007 .rx_ptr = dest_ptr,
1008 };
1009
1010 if (!ac_rtld_upload(&info)) {
1011 radv_shader_variant_destroy(device, variant);
1012 ac_rtld_close(&rtld_binary);
1013 return NULL;
1014 }
1015
1016 if (device->keep_shader_info ||
1017 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1018 const char *disasm_data;
1019 size_t disasm_size;
1020 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1021 radv_shader_variant_destroy(device, variant);
1022 ac_rtld_close(&rtld_binary);
1023 return NULL;
1024 }
1025
1026 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1027 variant->disasm_string = malloc(disasm_size + 1);
1028 memcpy(variant->disasm_string, disasm_data, disasm_size);
1029 variant->disasm_string[disasm_size] = 0;
1030 }
1031
1032 ac_rtld_close(&rtld_binary);
1033 } else {
1034 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1035 memcpy(dest_ptr, bin->data, bin->code_size);
1036
1037 /* Add end-of-code markers for the UMR disassembler. */
1038 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1039 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1040 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1041
1042 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1043 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
1044 }
1045 return variant;
1046 }
1047
1048 static struct radv_shader_variant *
1049 shader_variant_compile(struct radv_device *device,
1050 struct radv_shader_module *module,
1051 struct nir_shader * const *shaders,
1052 int shader_count,
1053 gl_shader_stage stage,
1054 struct radv_nir_compiler_options *options,
1055 bool gs_copy_shader,
1056 struct radv_shader_binary **binary_out)
1057 {
1058 enum radeon_family chip_family = device->physical_device->rad_info.family;
1059 enum ac_target_machine_options tm_options = 0;
1060 struct ac_llvm_compiler ac_llvm;
1061 struct radv_shader_binary *binary = NULL;
1062 struct radv_shader_variant_info variant_info = {0};
1063 bool thread_compiler;
1064
1065 if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
1066 lower_fs_io(shaders[0], &variant_info);
1067
1068 options->family = chip_family;
1069 options->chip_class = device->physical_device->rad_info.chip_class;
1070 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1071 options->dump_preoptir = options->dump_shader &&
1072 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1073 options->record_llvm_ir = device->keep_shader_info;
1074 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1075 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1076 options->address32_hi = device->physical_device->rad_info.address32_hi;
1077
1078 if (options->supports_spill)
1079 tm_options |= AC_TM_SUPPORTS_SPILL;
1080 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1081 tm_options |= AC_TM_SISCHED;
1082 if (options->check_ir)
1083 tm_options |= AC_TM_CHECK_IR;
1084 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1085 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1086
1087 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1088 radv_init_llvm_once();
1089 radv_init_llvm_compiler(&ac_llvm,
1090 thread_compiler,
1091 chip_family, tm_options);
1092 if (gs_copy_shader) {
1093 assert(shader_count == 1);
1094 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1095 &variant_info, options);
1096 } else {
1097 radv_compile_nir_shader(&ac_llvm, &binary, &variant_info,
1098 shaders, shader_count, options);
1099 }
1100 binary->variant_info = variant_info;
1101
1102 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1103
1104 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary);
1105 if (!variant) {
1106 free(binary);
1107 return NULL;
1108 }
1109
1110 if (options->dump_shader) {
1111 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1112 }
1113
1114
1115 if (device->keep_shader_info) {
1116 if (!gs_copy_shader && !module->nir) {
1117 variant->nir = *shaders;
1118 variant->spirv = (uint32_t *)module->data;
1119 variant->spirv_size = module->size;
1120 }
1121 }
1122
1123 if (binary_out)
1124 *binary_out = binary;
1125 else
1126 free(binary);
1127
1128 return variant;
1129 }
1130
1131 struct radv_shader_variant *
1132 radv_shader_variant_compile(struct radv_device *device,
1133 struct radv_shader_module *module,
1134 struct nir_shader *const *shaders,
1135 int shader_count,
1136 struct radv_pipeline_layout *layout,
1137 const struct radv_shader_variant_key *key,
1138 struct radv_shader_binary **binary_out)
1139 {
1140 struct radv_nir_compiler_options options = {0};
1141
1142 options.layout = layout;
1143 if (key)
1144 options.key = *key;
1145
1146 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
1147 options.supports_spill = true;
1148
1149 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
1150 &options, false, binary_out);
1151 }
1152
1153 struct radv_shader_variant *
1154 radv_create_gs_copy_shader(struct radv_device *device,
1155 struct nir_shader *shader,
1156 struct radv_shader_binary **binary_out,
1157 bool multiview)
1158 {
1159 struct radv_nir_compiler_options options = {0};
1160
1161 options.key.has_multiview_view_index = multiview;
1162
1163 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1164 &options, true, binary_out);
1165 }
1166
1167 void
1168 radv_shader_variant_destroy(struct radv_device *device,
1169 struct radv_shader_variant *variant)
1170 {
1171 if (!p_atomic_dec_zero(&variant->ref_count))
1172 return;
1173
1174 mtx_lock(&device->shader_slab_mutex);
1175 list_del(&variant->slab_list);
1176 mtx_unlock(&device->shader_slab_mutex);
1177
1178 ralloc_free(variant->nir);
1179 free(variant->disasm_string);
1180 free(variant->llvm_ir_string);
1181 free(variant);
1182 }
1183
1184 const char *
1185 radv_get_shader_name(struct radv_shader_variant_info *info,
1186 gl_shader_stage stage)
1187 {
1188 switch (stage) {
1189 case MESA_SHADER_VERTEX:
1190 if (info->vs.as_ls)
1191 return "Vertex Shader as LS";
1192 else if (info->vs.as_es)
1193 return "Vertex Shader as ES";
1194 else if (info->is_ngg)
1195 return "Vertex Shader as ESGS";
1196 else
1197 return "Vertex Shader as VS";
1198 case MESA_SHADER_TESS_CTRL:
1199 return "Tessellation Control Shader";
1200 case MESA_SHADER_TESS_EVAL:
1201 if (info->tes.as_es)
1202 return "Tessellation Evaluation Shader as ES";
1203 else if (info->is_ngg)
1204 return "Tessellation Evaluation Shader as ESGS";
1205 else
1206 return "Tessellation Evaluation Shader as VS";
1207 case MESA_SHADER_GEOMETRY:
1208 return "Geometry Shader";
1209 case MESA_SHADER_FRAGMENT:
1210 return "Pixel Shader";
1211 case MESA_SHADER_COMPUTE:
1212 return "Compute Shader";
1213 default:
1214 return "Unknown shader";
1215 };
1216 }
1217
1218 static void
1219 generate_shader_stats(struct radv_device *device,
1220 struct radv_shader_variant *variant,
1221 gl_shader_stage stage,
1222 struct _mesa_string_buffer *buf)
1223 {
1224 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1225 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1226 struct ac_shader_config *conf;
1227 unsigned max_simd_waves;
1228 unsigned lds_per_wave = 0;
1229
1230 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
1231
1232 conf = &variant->config;
1233
1234 if (stage == MESA_SHADER_FRAGMENT) {
1235 lds_per_wave = conf->lds_size * lds_increment +
1236 align(variant->info.fs.num_interp * 48,
1237 lds_increment);
1238 } else if (stage == MESA_SHADER_COMPUTE) {
1239 unsigned max_workgroup_size =
1240 radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
1241 lds_per_wave = (conf->lds_size * lds_increment) /
1242 DIV_ROUND_UP(max_workgroup_size, 64);
1243 }
1244
1245 if (conf->num_sgprs)
1246 max_simd_waves =
1247 MIN2(max_simd_waves,
1248 ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
1249
1250 if (conf->num_vgprs)
1251 max_simd_waves =
1252 MIN2(max_simd_waves,
1253 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1254
1255 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1256 * that PS can use.
1257 */
1258 if (lds_per_wave)
1259 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1260
1261 if (stage == MESA_SHADER_FRAGMENT) {
1262 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1263 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1264 "SPI_PS_INPUT_ENA = 0x%04x\n",
1265 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1266 }
1267
1268 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1269 "SGPRS: %d\n"
1270 "VGPRS: %d\n"
1271 "Spilled SGPRs: %d\n"
1272 "Spilled VGPRs: %d\n"
1273 "PrivMem VGPRS: %d\n"
1274 "Code Size: %d bytes\n"
1275 "LDS: %d blocks\n"
1276 "Scratch: %d bytes per wave\n"
1277 "Max Waves: %d\n"
1278 "********************\n\n\n",
1279 conf->num_sgprs, conf->num_vgprs,
1280 conf->spilled_sgprs, conf->spilled_vgprs,
1281 variant->info.private_mem_vgprs, variant->code_size,
1282 conf->lds_size, conf->scratch_bytes_per_wave,
1283 max_simd_waves);
1284 }
1285
1286 void
1287 radv_shader_dump_stats(struct radv_device *device,
1288 struct radv_shader_variant *variant,
1289 gl_shader_stage stage,
1290 FILE *file)
1291 {
1292 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1293
1294 generate_shader_stats(device, variant, stage, buf);
1295
1296 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1297 fprintf(file, "%s", buf->buf);
1298
1299 _mesa_string_buffer_destroy(buf);
1300 }
1301
1302 VkResult
1303 radv_GetShaderInfoAMD(VkDevice _device,
1304 VkPipeline _pipeline,
1305 VkShaderStageFlagBits shaderStage,
1306 VkShaderInfoTypeAMD infoType,
1307 size_t* pInfoSize,
1308 void* pInfo)
1309 {
1310 RADV_FROM_HANDLE(radv_device, device, _device);
1311 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1312 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1313 struct radv_shader_variant *variant = pipeline->shaders[stage];
1314 struct _mesa_string_buffer *buf;
1315 VkResult result = VK_SUCCESS;
1316
1317 /* Spec doesn't indicate what to do if the stage is invalid, so just
1318 * return no info for this. */
1319 if (!variant)
1320 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1321
1322 switch (infoType) {
1323 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1324 if (!pInfo) {
1325 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1326 } else {
1327 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1328 struct ac_shader_config *conf = &variant->config;
1329
1330 VkShaderStatisticsInfoAMD statistics = {};
1331 statistics.shaderStageMask = shaderStage;
1332 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1333 statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
1334 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1335
1336 if (stage == MESA_SHADER_COMPUTE) {
1337 unsigned *local_size = variant->nir->info.cs.local_size;
1338 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1339
1340 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1341 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1342
1343 statistics.computeWorkGroupSize[0] = local_size[0];
1344 statistics.computeWorkGroupSize[1] = local_size[1];
1345 statistics.computeWorkGroupSize[2] = local_size[2];
1346 } else {
1347 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1348 }
1349
1350 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1351 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1352 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1353 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1354 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1355
1356 size_t size = *pInfoSize;
1357 *pInfoSize = sizeof(statistics);
1358
1359 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1360
1361 if (size < *pInfoSize)
1362 result = VK_INCOMPLETE;
1363 }
1364
1365 break;
1366 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1367 buf = _mesa_string_buffer_create(NULL, 1024);
1368
1369 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1370 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
1371 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1372 generate_shader_stats(device, variant, stage, buf);
1373
1374 /* Need to include the null terminator. */
1375 size_t length = buf->length + 1;
1376
1377 if (!pInfo) {
1378 *pInfoSize = length;
1379 } else {
1380 size_t size = *pInfoSize;
1381 *pInfoSize = length;
1382
1383 memcpy(pInfo, buf->buf, MIN2(size, length));
1384
1385 if (size < length)
1386 result = VK_INCOMPLETE;
1387 }
1388
1389 _mesa_string_buffer_destroy(buf);
1390 break;
1391 default:
1392 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1393 result = VK_ERROR_FEATURE_NOT_PRESENT;
1394 break;
1395 }
1396
1397 return result;
1398 }