2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
58 .lower_device_index_to_zero
= true,
62 .lower_pack_snorm_2x16
= true,
63 .lower_pack_snorm_4x8
= true,
64 .lower_pack_unorm_2x16
= true,
65 .lower_pack_unorm_4x8
= true,
66 .lower_unpack_snorm_2x16
= true,
67 .lower_unpack_snorm_4x8
= true,
68 .lower_unpack_unorm_2x16
= true,
69 .lower_unpack_unorm_4x8
= true,
70 .lower_extract_byte
= true,
71 .lower_extract_word
= true,
74 .max_unroll_iterations
= 32
77 VkResult
radv_CreateShaderModule(
79 const VkShaderModuleCreateInfo
* pCreateInfo
,
80 const VkAllocationCallbacks
* pAllocator
,
81 VkShaderModule
* pShaderModule
)
83 RADV_FROM_HANDLE(radv_device
, device
, _device
);
84 struct radv_shader_module
*module
;
86 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
87 assert(pCreateInfo
->flags
== 0);
89 module
= vk_alloc2(&device
->alloc
, pAllocator
,
90 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
91 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
93 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
96 module
->size
= pCreateInfo
->codeSize
;
97 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
99 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
101 *pShaderModule
= radv_shader_module_to_handle(module
);
106 void radv_DestroyShaderModule(
108 VkShaderModule _module
,
109 const VkAllocationCallbacks
* pAllocator
)
111 RADV_FROM_HANDLE(radv_device
, device
, _device
);
112 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
117 vk_free2(&device
->alloc
, pAllocator
, module
);
121 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
129 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_local
);
130 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_local
);
132 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
133 NIR_PASS_V(shader
, nir_lower_pack
);
136 /* Only run this pass in the first call to
137 * radv_optimize_nir. Later calls assume that we've
138 * lowered away any copy_deref instructions and we
139 * don't want to introduce any more.
141 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
144 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
145 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
147 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
148 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
150 NIR_PASS(progress
, shader
, nir_copy_prop
);
151 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
152 NIR_PASS(progress
, shader
, nir_opt_dce
);
153 if (nir_opt_trivial_continues(shader
)) {
155 NIR_PASS(progress
, shader
, nir_copy_prop
);
156 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
157 NIR_PASS(progress
, shader
, nir_opt_dce
);
159 NIR_PASS(progress
, shader
, nir_opt_if
);
160 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
161 NIR_PASS(progress
, shader
, nir_opt_cse
);
162 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
163 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
164 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
165 NIR_PASS(progress
, shader
, nir_opt_undef
);
166 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
167 if (shader
->options
->max_unroll_iterations
) {
168 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
170 } while (progress
&& !optimize_conservatively
);
172 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
173 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
177 radv_shader_compile_to_nir(struct radv_device
*device
,
178 struct radv_shader_module
*module
,
179 const char *entrypoint_name
,
180 gl_shader_stage stage
,
181 const VkSpecializationInfo
*spec_info
,
182 const VkPipelineCreateFlags flags
)
185 nir_function
*entry_point
;
187 /* Some things such as our meta clear/blit code will give us a NIR
188 * shader directly. In that case, we just ignore the SPIR-V entirely
189 * and just use the NIR shader */
191 nir
->options
= &nir_options
;
192 nir_validate_shader(nir
, "in internal shader");
194 assert(exec_list_length(&nir
->functions
) == 1);
195 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
196 entry_point
= exec_node_data(nir_function
, node
, node
);
198 uint32_t *spirv
= (uint32_t *) module
->data
;
199 assert(module
->size
% 4 == 0);
201 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
202 radv_print_spirv(spirv
, module
->size
, stderr
);
204 uint32_t num_spec_entries
= 0;
205 struct nir_spirv_specialization
*spec_entries
= NULL
;
206 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
207 num_spec_entries
= spec_info
->mapEntryCount
;
208 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
209 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
210 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
211 const void *data
= spec_info
->pData
+ entry
.offset
;
212 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
214 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
215 if (spec_info
->dataSize
== 8)
216 spec_entries
[i
].data64
= *(const uint64_t *)data
;
218 spec_entries
[i
].data32
= *(const uint32_t *)data
;
221 const struct spirv_to_nir_options spirv_options
= {
223 .device_group
= true,
224 .draw_parameters
= true,
226 .image_read_without_format
= true,
227 .image_write_without_format
= true,
228 .tessellation
= true,
232 .subgroup_arithmetic
= true,
233 .subgroup_ballot
= true,
234 .subgroup_basic
= true,
235 .subgroup_quad
= true,
236 .subgroup_shuffle
= true,
237 .subgroup_vote
= true,
238 .variable_pointers
= true,
240 .trinary_minmax
= true,
241 .shader_viewport_index_layer
= true,
242 .descriptor_array_dynamic_indexing
= true,
243 .runtime_descriptor_array
= true,
244 .stencil_export
= true,
245 .storage_16bit
= true,
246 .geometry_streams
= true,
247 .transform_feedback
= true,
248 .storage_image_ms
= true,
250 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
251 .ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
252 .push_const_ptr_type
= glsl_uint_type(),
253 .shared_ptr_type
= glsl_uint_type(),
255 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
256 spec_entries
, num_spec_entries
,
257 stage
, entrypoint_name
,
258 &spirv_options
, &nir_options
);
259 nir
= entry_point
->shader
;
260 assert(nir
->info
.stage
== stage
);
261 nir_validate_shader(nir
, "after spirv_to_nir");
265 /* We have to lower away local constant initializers right before we
266 * inline functions. That way they get properly initialized at the top
267 * of the function and not at the top of its caller.
269 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
270 NIR_PASS_V(nir
, nir_lower_returns
);
271 NIR_PASS_V(nir
, nir_inline_functions
);
272 NIR_PASS_V(nir
, nir_opt_deref
);
274 /* Pick off the single entrypoint that we want */
275 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
276 if (func
!= entry_point
)
277 exec_node_remove(&func
->node
);
279 assert(exec_list_length(&nir
->functions
) == 1);
280 entry_point
->name
= ralloc_strdup(entry_point
, "main");
282 /* Make sure we lower constant initializers on output variables so that
283 * nir_remove_dead_variables below sees the corresponding stores
285 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
287 /* Now that we've deleted all but the main function, we can go ahead and
288 * lower the rest of the constant initializers.
290 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
292 /* Split member structs. We do this before lower_io_to_temporaries so that
293 * it doesn't lower system values to temporaries by accident.
295 NIR_PASS_V(nir
, nir_split_var_copies
);
296 NIR_PASS_V(nir
, nir_split_per_member_structs
);
298 NIR_PASS_V(nir
, nir_remove_dead_variables
,
299 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
301 NIR_PASS_V(nir
, nir_lower_system_values
);
302 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
305 /* Vulkan uses the separate-shader linking model */
306 nir
->info
.separate_shader
= true;
308 nir_shader_gather_info(nir
, entry_point
->impl
);
310 static const nir_lower_tex_options tex_options
= {
314 nir_lower_tex(nir
, &tex_options
);
316 nir_lower_vars_to_ssa(nir
);
318 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
319 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
320 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
321 nir_shader_get_entrypoint(nir
), true, true);
322 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
323 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
324 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
325 nir_shader_get_entrypoint(nir
), true, false);
328 nir_split_var_copies(nir
);
330 nir_lower_global_vars_to_local(nir
);
331 nir_remove_dead_variables(nir
, nir_var_local
);
332 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
334 .ballot_bit_size
= 64,
335 .lower_to_scalar
= 1,
336 .lower_subgroup_masks
= 1,
338 .lower_shuffle_to_32bit
= 1,
339 .lower_vote_eq_to_ballot
= 1,
342 nir_lower_load_const_to_scalar(nir
);
344 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
345 radv_optimize_nir(nir
, false, true);
347 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
348 * to remove any copies introduced by nir_opt_find_array_copies().
350 nir_lower_var_copies(nir
);
352 /* Indirect lowering must be called after the radv_optimize_nir() loop
353 * has been called at least once. Otherwise indirect lowering can
354 * bloat the instruction count of the loop and cause it to be
355 * considered too large for unrolling.
357 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
358 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
364 radv_alloc_shader_memory(struct radv_device
*device
,
365 struct radv_shader_variant
*shader
)
367 mtx_lock(&device
->shader_slab_mutex
);
368 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
370 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
371 if (s
->bo_offset
- offset
>= shader
->code_size
) {
372 shader
->bo
= slab
->bo
;
373 shader
->bo_offset
= offset
;
374 list_addtail(&shader
->slab_list
, &s
->slab_list
);
375 mtx_unlock(&device
->shader_slab_mutex
);
376 return slab
->ptr
+ offset
;
378 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
380 if (slab
->size
- offset
>= shader
->code_size
) {
381 shader
->bo
= slab
->bo
;
382 shader
->bo_offset
= offset
;
383 list_addtail(&shader
->slab_list
, &slab
->shaders
);
384 mtx_unlock(&device
->shader_slab_mutex
);
385 return slab
->ptr
+ offset
;
389 mtx_unlock(&device
->shader_slab_mutex
);
390 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
392 slab
->size
= 256 * 1024;
393 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
395 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
396 (device
->physical_device
->cpdma_prefetch_writes_memory
?
397 0 : RADEON_FLAG_READ_ONLY
));
398 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
399 list_inithead(&slab
->shaders
);
401 mtx_lock(&device
->shader_slab_mutex
);
402 list_add(&slab
->slabs
, &device
->shader_slabs
);
404 shader
->bo
= slab
->bo
;
405 shader
->bo_offset
= 0;
406 list_add(&shader
->slab_list
, &slab
->shaders
);
407 mtx_unlock(&device
->shader_slab_mutex
);
412 radv_destroy_shader_slabs(struct radv_device
*device
)
414 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
415 device
->ws
->buffer_destroy(slab
->bo
);
418 mtx_destroy(&device
->shader_slab_mutex
);
421 /* For the UMR disassembler. */
422 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
423 #define DEBUGGER_NUM_MARKERS 5
426 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
428 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
432 radv_fill_shader_variant(struct radv_device
*device
,
433 struct radv_shader_variant
*variant
,
434 struct ac_shader_binary
*binary
,
435 gl_shader_stage stage
)
437 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
438 struct radv_shader_info
*info
= &variant
->info
.info
;
439 unsigned vgpr_comp_cnt
= 0;
441 variant
->code_size
= radv_get_shader_binary_size(binary
);
442 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
443 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
444 S_00B12C_SCRATCH_EN(scratch_enabled
) |
445 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
446 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
447 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
448 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
449 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
451 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
452 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
453 S_00B848_DX10_CLAMP(1) |
454 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
457 case MESA_SHADER_TESS_EVAL
:
459 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
461 case MESA_SHADER_TESS_CTRL
:
462 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
463 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
465 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
468 case MESA_SHADER_VERTEX
:
469 case MESA_SHADER_GEOMETRY
:
470 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
472 case MESA_SHADER_FRAGMENT
:
474 case MESA_SHADER_COMPUTE
:
476 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
477 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
478 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
479 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
480 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
481 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
482 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
485 unreachable("unsupported shader type");
489 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
490 stage
== MESA_SHADER_GEOMETRY
) {
491 unsigned es_type
= variant
->info
.gs
.es_type
;
492 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
494 if (es_type
== MESA_SHADER_VERTEX
) {
495 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
496 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
497 es_vgpr_comp_cnt
= 3;
499 unreachable("invalid shader ES type");
502 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
503 * VGPR[0:4] are always loaded.
505 if (info
->uses_invocation_id
) {
506 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
507 } else if (info
->uses_prim_id
) {
508 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
509 } else if (variant
->info
.gs
.vertices_in
>= 3) {
510 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
512 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
515 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
516 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
517 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
518 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
519 stage
== MESA_SHADER_TESS_CTRL
) {
520 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
522 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
525 void *ptr
= radv_alloc_shader_memory(device
, variant
);
526 memcpy(ptr
, binary
->code
, binary
->code_size
);
528 /* Add end-of-code markers for the UMR disassembler. */
529 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
530 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
531 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
535 static void radv_init_llvm_target()
537 LLVMInitializeAMDGPUTargetInfo();
538 LLVMInitializeAMDGPUTarget();
539 LLVMInitializeAMDGPUTargetMC();
540 LLVMInitializeAMDGPUAsmPrinter();
542 /* For inline assembly. */
543 LLVMInitializeAMDGPUAsmParser();
545 /* Workaround for bug in llvm 4.0 that causes image intrinsics
547 * https://reviews.llvm.org/D26348
549 * Workaround for bug in llvm that causes the GPU to hang in presence
550 * of nested loops because there is an exec mask issue. The proper
551 * solution is to fix LLVM but this might require a bunch of work.
552 * https://bugs.llvm.org/show_bug.cgi?id=37744
554 * "mesa" is the prefix for error messages.
556 if (HAVE_LLVM
>= 0x0800) {
557 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
558 LLVMParseCommandLineOptions(2, argv
, NULL
);
561 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
562 "-amdgpu-skip-threshold=1" };
563 LLVMParseCommandLineOptions(3, argv
, NULL
);
567 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
569 static void radv_init_llvm_once(void)
571 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
574 static struct radv_shader_variant
*
575 shader_variant_create(struct radv_device
*device
,
576 struct radv_shader_module
*module
,
577 struct nir_shader
* const *shaders
,
579 gl_shader_stage stage
,
580 struct radv_nir_compiler_options
*options
,
583 unsigned *code_size_out
)
585 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
586 enum ac_target_machine_options tm_options
= 0;
587 struct radv_shader_variant
*variant
;
588 struct ac_shader_binary binary
;
589 struct ac_llvm_compiler ac_llvm
;
590 bool thread_compiler
;
591 variant
= calloc(1, sizeof(struct radv_shader_variant
));
595 options
->family
= chip_family
;
596 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
597 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
598 options
->dump_preoptir
= options
->dump_shader
&&
599 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
600 options
->record_llvm_ir
= device
->keep_shader_info
;
601 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
602 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
603 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
605 if (options
->supports_spill
)
606 tm_options
|= AC_TM_SUPPORTS_SPILL
;
607 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
608 tm_options
|= AC_TM_SISCHED
;
609 if (options
->check_ir
)
610 tm_options
|= AC_TM_CHECK_IR
;
612 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
613 radv_init_llvm_once();
614 radv_init_llvm_compiler(&ac_llvm
,
616 chip_family
, tm_options
);
617 if (gs_copy_shader
) {
618 assert(shader_count
== 1);
619 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
620 &variant
->config
, &variant
->info
,
623 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
624 &variant
->info
, shaders
, shader_count
,
628 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
630 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
633 *code_out
= binary
.code
;
634 *code_size_out
= binary
.code_size
;
639 free(binary
.global_symbol_offsets
);
641 variant
->ref_count
= 1;
643 if (device
->keep_shader_info
) {
644 variant
->disasm_string
= binary
.disasm_string
;
645 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
646 if (!gs_copy_shader
&& !module
->nir
) {
647 variant
->nir
= *shaders
;
648 variant
->spirv
= (uint32_t *)module
->data
;
649 variant
->spirv_size
= module
->size
;
652 free(binary
.disasm_string
);
658 struct radv_shader_variant
*
659 radv_shader_variant_create(struct radv_device
*device
,
660 struct radv_shader_module
*module
,
661 struct nir_shader
*const *shaders
,
663 struct radv_pipeline_layout
*layout
,
664 const struct radv_shader_variant_key
*key
,
666 unsigned *code_size_out
)
668 struct radv_nir_compiler_options options
= {0};
670 options
.layout
= layout
;
674 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
675 options
.supports_spill
= true;
677 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
678 &options
, false, code_out
, code_size_out
);
681 struct radv_shader_variant
*
682 radv_create_gs_copy_shader(struct radv_device
*device
,
683 struct nir_shader
*shader
,
685 unsigned *code_size_out
,
688 struct radv_nir_compiler_options options
= {0};
690 options
.key
.has_multiview_view_index
= multiview
;
692 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
693 &options
, true, code_out
, code_size_out
);
697 radv_shader_variant_destroy(struct radv_device
*device
,
698 struct radv_shader_variant
*variant
)
700 if (!p_atomic_dec_zero(&variant
->ref_count
))
703 mtx_lock(&device
->shader_slab_mutex
);
704 list_del(&variant
->slab_list
);
705 mtx_unlock(&device
->shader_slab_mutex
);
707 ralloc_free(variant
->nir
);
708 free(variant
->disasm_string
);
709 free(variant
->llvm_ir_string
);
714 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
717 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
718 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
719 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
720 case MESA_SHADER_COMPUTE
: return "Compute Shader";
721 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
722 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
724 return "Unknown shader";
729 generate_shader_stats(struct radv_device
*device
,
730 struct radv_shader_variant
*variant
,
731 gl_shader_stage stage
,
732 struct _mesa_string_buffer
*buf
)
734 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
735 struct ac_shader_config
*conf
;
736 unsigned max_simd_waves
;
737 unsigned lds_per_wave
= 0;
739 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
741 conf
= &variant
->config
;
743 if (stage
== MESA_SHADER_FRAGMENT
) {
744 lds_per_wave
= conf
->lds_size
* lds_increment
+
745 align(variant
->info
.fs
.num_interp
* 48,
752 radv_get_num_physical_sgprs(device
->physical_device
) / conf
->num_sgprs
);
757 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
759 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
763 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
765 if (stage
== MESA_SHADER_FRAGMENT
) {
766 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
767 "SPI_PS_INPUT_ADDR = 0x%04x\n"
768 "SPI_PS_INPUT_ENA = 0x%04x\n",
769 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
772 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
775 "Spilled SGPRs: %d\n"
776 "Spilled VGPRs: %d\n"
777 "PrivMem VGPRS: %d\n"
778 "Code Size: %d bytes\n"
780 "Scratch: %d bytes per wave\n"
782 "********************\n\n\n",
783 conf
->num_sgprs
, conf
->num_vgprs
,
784 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
785 variant
->info
.private_mem_vgprs
, variant
->code_size
,
786 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
791 radv_shader_dump_stats(struct radv_device
*device
,
792 struct radv_shader_variant
*variant
,
793 gl_shader_stage stage
,
796 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
798 generate_shader_stats(device
, variant
, stage
, buf
);
800 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
801 fprintf(file
, "%s", buf
->buf
);
803 _mesa_string_buffer_destroy(buf
);
807 radv_GetShaderInfoAMD(VkDevice _device
,
808 VkPipeline _pipeline
,
809 VkShaderStageFlagBits shaderStage
,
810 VkShaderInfoTypeAMD infoType
,
814 RADV_FROM_HANDLE(radv_device
, device
, _device
);
815 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
816 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
817 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
818 struct _mesa_string_buffer
*buf
;
819 VkResult result
= VK_SUCCESS
;
821 /* Spec doesn't indicate what to do if the stage is invalid, so just
822 * return no info for this. */
824 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
827 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
829 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
831 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
832 struct ac_shader_config
*conf
= &variant
->config
;
834 VkShaderStatisticsInfoAMD statistics
= {};
835 statistics
.shaderStageMask
= shaderStage
;
836 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
837 statistics
.numPhysicalSgprs
= radv_get_num_physical_sgprs(device
->physical_device
);
838 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
840 if (stage
== MESA_SHADER_COMPUTE
) {
841 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
842 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
844 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
845 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
847 statistics
.computeWorkGroupSize
[0] = local_size
[0];
848 statistics
.computeWorkGroupSize
[1] = local_size
[1];
849 statistics
.computeWorkGroupSize
[2] = local_size
[2];
851 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
854 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
855 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
856 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
857 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
858 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
860 size_t size
= *pInfoSize
;
861 *pInfoSize
= sizeof(statistics
);
863 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
865 if (size
< *pInfoSize
)
866 result
= VK_INCOMPLETE
;
870 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
871 buf
= _mesa_string_buffer_create(NULL
, 1024);
873 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
874 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
875 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
876 generate_shader_stats(device
, variant
, stage
, buf
);
878 /* Need to include the null terminator. */
879 size_t length
= buf
->length
+ 1;
884 size_t size
= *pInfoSize
;
887 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
890 result
= VK_INCOMPLETE
;
893 _mesa_string_buffer_destroy(buf
);
896 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
897 result
= VK_ERROR_FEATURE_NOT_PRESENT
;