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radv/gfx10: Set MEM_ORDERED flags on shaders.
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp16 = true,
57 .lower_flrp32 = true,
58 .lower_flrp64 = true,
59 .lower_device_index_to_zero = true,
60 .lower_fsat = true,
61 .lower_fdiv = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32
80 };
81
82 VkResult radv_CreateShaderModule(
83 VkDevice _device,
84 const VkShaderModuleCreateInfo* pCreateInfo,
85 const VkAllocationCallbacks* pAllocator,
86 VkShaderModule* pShaderModule)
87 {
88 RADV_FROM_HANDLE(radv_device, device, _device);
89 struct radv_shader_module *module;
90
91 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
92 assert(pCreateInfo->flags == 0);
93
94 module = vk_alloc2(&device->alloc, pAllocator,
95 sizeof(*module) + pCreateInfo->codeSize, 8,
96 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
97 if (module == NULL)
98 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
99
100 module->nir = NULL;
101 module->size = pCreateInfo->codeSize;
102 memcpy(module->data, pCreateInfo->pCode, module->size);
103
104 _mesa_sha1_compute(module->data, module->size, module->sha1);
105
106 *pShaderModule = radv_shader_module_to_handle(module);
107
108 return VK_SUCCESS;
109 }
110
111 void radv_DestroyShaderModule(
112 VkDevice _device,
113 VkShaderModule _module,
114 const VkAllocationCallbacks* pAllocator)
115 {
116 RADV_FROM_HANDLE(radv_device, device, _device);
117 RADV_FROM_HANDLE(radv_shader_module, module, _module);
118
119 if (!module)
120 return;
121
122 vk_free2(&device->alloc, pAllocator, module);
123 }
124
125 void
126 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
127 bool allow_copies)
128 {
129 bool progress;
130 unsigned lower_flrp =
131 (shader->options->lower_flrp16 ? 16 : 0) |
132 (shader->options->lower_flrp32 ? 32 : 0) |
133 (shader->options->lower_flrp64 ? 64 : 0);
134
135 do {
136 progress = false;
137
138 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
139 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
140
141 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
142 NIR_PASS_V(shader, nir_lower_pack);
143
144 if (allow_copies) {
145 /* Only run this pass in the first call to
146 * radv_optimize_nir. Later calls assume that we've
147 * lowered away any copy_deref instructions and we
148 * don't want to introduce any more.
149 */
150 NIR_PASS(progress, shader, nir_opt_find_array_copies);
151 }
152
153 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
154 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
155
156 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
157 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
158
159 NIR_PASS(progress, shader, nir_copy_prop);
160 NIR_PASS(progress, shader, nir_opt_remove_phis);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 if (nir_opt_trivial_continues(shader)) {
163 progress = true;
164 NIR_PASS(progress, shader, nir_copy_prop);
165 NIR_PASS(progress, shader, nir_opt_remove_phis);
166 NIR_PASS(progress, shader, nir_opt_dce);
167 }
168 NIR_PASS(progress, shader, nir_opt_if, true);
169 NIR_PASS(progress, shader, nir_opt_dead_cf);
170 NIR_PASS(progress, shader, nir_opt_cse);
171 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
172 NIR_PASS(progress, shader, nir_opt_constant_folding);
173 NIR_PASS(progress, shader, nir_opt_algebraic);
174
175 if (lower_flrp != 0) {
176 bool lower_flrp_progress = false;
177 NIR_PASS(lower_flrp_progress,
178 shader,
179 nir_lower_flrp,
180 lower_flrp,
181 false /* always_precise */,
182 shader->options->lower_ffma);
183 if (lower_flrp_progress) {
184 NIR_PASS(progress, shader,
185 nir_opt_constant_folding);
186 progress = true;
187 }
188
189 /* Nothing should rematerialize any flrps, so we only
190 * need to do this lowering once.
191 */
192 lower_flrp = 0;
193 }
194
195 NIR_PASS(progress, shader, nir_opt_undef);
196 NIR_PASS(progress, shader, nir_opt_conditional_discard);
197 if (shader->options->max_unroll_iterations) {
198 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
199 }
200 } while (progress && !optimize_conservatively);
201
202 NIR_PASS(progress, shader, nir_opt_shrink_load);
203 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
204 }
205
206 nir_shader *
207 radv_shader_compile_to_nir(struct radv_device *device,
208 struct radv_shader_module *module,
209 const char *entrypoint_name,
210 gl_shader_stage stage,
211 const VkSpecializationInfo *spec_info,
212 const VkPipelineCreateFlags flags,
213 const struct radv_pipeline_layout *layout)
214 {
215 nir_shader *nir;
216 if (module->nir) {
217 /* Some things such as our meta clear/blit code will give us a NIR
218 * shader directly. In that case, we just ignore the SPIR-V entirely
219 * and just use the NIR shader */
220 nir = module->nir;
221 nir->options = &nir_options;
222 nir_validate_shader(nir, "in internal shader");
223
224 assert(exec_list_length(&nir->functions) == 1);
225 } else {
226 uint32_t *spirv = (uint32_t *) module->data;
227 assert(module->size % 4 == 0);
228
229 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
230 radv_print_spirv(spirv, module->size, stderr);
231
232 uint32_t num_spec_entries = 0;
233 struct nir_spirv_specialization *spec_entries = NULL;
234 if (spec_info && spec_info->mapEntryCount > 0) {
235 num_spec_entries = spec_info->mapEntryCount;
236 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
237 for (uint32_t i = 0; i < num_spec_entries; i++) {
238 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
239 const void *data = spec_info->pData + entry.offset;
240 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
241
242 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
243 if (spec_info->dataSize == 8)
244 spec_entries[i].data64 = *(const uint64_t *)data;
245 else
246 spec_entries[i].data32 = *(const uint32_t *)data;
247 }
248 }
249 const struct spirv_to_nir_options spirv_options = {
250 .lower_ubo_ssbo_access_to_offsets = true,
251 .caps = {
252 .amd_gcn_shader = true,
253 .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT,
254 .amd_trinary_minmax = true,
255 .derivative_group = true,
256 .descriptor_array_dynamic_indexing = true,
257 .descriptor_array_non_uniform_indexing = true,
258 .descriptor_indexing = true,
259 .device_group = true,
260 .draw_parameters = true,
261 .float16 = true,
262 .float64 = true,
263 .geometry_streams = true,
264 .image_read_without_format = true,
265 .image_write_without_format = true,
266 .int8 = true,
267 .int16 = true,
268 .int64 = true,
269 .int64_atomics = true,
270 .multiview = true,
271 .physical_storage_buffer_address = true,
272 .runtime_descriptor_array = true,
273 .shader_viewport_index_layer = true,
274 .stencil_export = true,
275 .storage_8bit = true,
276 .storage_16bit = true,
277 .storage_image_ms = true,
278 .subgroup_arithmetic = true,
279 .subgroup_ballot = true,
280 .subgroup_basic = true,
281 .subgroup_quad = true,
282 .subgroup_shuffle = true,
283 .subgroup_vote = true,
284 .tessellation = true,
285 .transform_feedback = true,
286 .variable_pointers = true,
287 },
288 .ubo_addr_format = nir_address_format_32bit_index_offset,
289 .ssbo_addr_format = nir_address_format_32bit_index_offset,
290 .phys_ssbo_addr_format = nir_address_format_64bit_global,
291 .push_const_addr_format = nir_address_format_logical,
292 .shared_addr_format = nir_address_format_32bit_offset,
293 };
294 nir = spirv_to_nir(spirv, module->size / 4,
295 spec_entries, num_spec_entries,
296 stage, entrypoint_name,
297 &spirv_options, &nir_options);
298 assert(nir->info.stage == stage);
299 nir_validate_shader(nir, "after spirv_to_nir");
300
301 free(spec_entries);
302
303 /* We have to lower away local constant initializers right before we
304 * inline functions. That way they get properly initialized at the top
305 * of the function and not at the top of its caller.
306 */
307 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
308 NIR_PASS_V(nir, nir_lower_returns);
309 NIR_PASS_V(nir, nir_inline_functions);
310 NIR_PASS_V(nir, nir_opt_deref);
311
312 /* Pick off the single entrypoint that we want */
313 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
314 if (func->is_entrypoint)
315 func->name = ralloc_strdup(func, "main");
316 else
317 exec_node_remove(&func->node);
318 }
319 assert(exec_list_length(&nir->functions) == 1);
320
321 /* Make sure we lower constant initializers on output variables so that
322 * nir_remove_dead_variables below sees the corresponding stores
323 */
324 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
325
326 /* Now that we've deleted all but the main function, we can go ahead and
327 * lower the rest of the constant initializers.
328 */
329 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
330
331 /* Split member structs. We do this before lower_io_to_temporaries so that
332 * it doesn't lower system values to temporaries by accident.
333 */
334 NIR_PASS_V(nir, nir_split_var_copies);
335 NIR_PASS_V(nir, nir_split_per_member_structs);
336
337 NIR_PASS_V(nir, nir_remove_dead_variables,
338 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
339
340 NIR_PASS_V(nir, nir_lower_system_values);
341 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
342 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
343 }
344
345 /* Vulkan uses the separate-shader linking model */
346 nir->info.separate_shader = true;
347
348 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
349
350 static const nir_lower_tex_options tex_options = {
351 .lower_txp = ~0,
352 .lower_tg4_offsets = true,
353 };
354
355 nir_lower_tex(nir, &tex_options);
356
357 nir_lower_vars_to_ssa(nir);
358
359 if (nir->info.stage == MESA_SHADER_VERTEX ||
360 nir->info.stage == MESA_SHADER_GEOMETRY) {
361 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
362 nir_shader_get_entrypoint(nir), true, true);
363 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
364 nir->info.stage == MESA_SHADER_FRAGMENT) {
365 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
366 nir_shader_get_entrypoint(nir), true, false);
367 }
368
369 nir_split_var_copies(nir);
370
371 nir_lower_global_vars_to_local(nir);
372 nir_remove_dead_variables(nir, nir_var_function_temp);
373 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
374 .subgroup_size = 64,
375 .ballot_bit_size = 64,
376 .lower_to_scalar = 1,
377 .lower_subgroup_masks = 1,
378 .lower_shuffle = 1,
379 .lower_shuffle_to_32bit = 1,
380 .lower_vote_eq_to_ballot = 1,
381 });
382
383 nir_lower_load_const_to_scalar(nir);
384
385 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
386 radv_optimize_nir(nir, false, true);
387
388 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
389 * to remove any copies introduced by nir_opt_find_array_copies().
390 */
391 nir_lower_var_copies(nir);
392
393 /* Indirect lowering must be called after the radv_optimize_nir() loop
394 * has been called at least once. Otherwise indirect lowering can
395 * bloat the instruction count of the loop and cause it to be
396 * considered too large for unrolling.
397 */
398 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
399 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
400
401 return nir;
402 }
403
404 void *
405 radv_alloc_shader_memory(struct radv_device *device,
406 struct radv_shader_variant *shader)
407 {
408 mtx_lock(&device->shader_slab_mutex);
409 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
410 uint64_t offset = 0;
411 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
412 if (s->bo_offset - offset >= shader->code_size) {
413 shader->bo = slab->bo;
414 shader->bo_offset = offset;
415 list_addtail(&shader->slab_list, &s->slab_list);
416 mtx_unlock(&device->shader_slab_mutex);
417 return slab->ptr + offset;
418 }
419 offset = align_u64(s->bo_offset + s->code_size, 256);
420 }
421 if (slab->size - offset >= shader->code_size) {
422 shader->bo = slab->bo;
423 shader->bo_offset = offset;
424 list_addtail(&shader->slab_list, &slab->shaders);
425 mtx_unlock(&device->shader_slab_mutex);
426 return slab->ptr + offset;
427 }
428 }
429
430 mtx_unlock(&device->shader_slab_mutex);
431 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
432
433 slab->size = 256 * 1024;
434 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
435 RADEON_DOMAIN_VRAM,
436 RADEON_FLAG_NO_INTERPROCESS_SHARING |
437 (device->physical_device->cpdma_prefetch_writes_memory ?
438 0 : RADEON_FLAG_READ_ONLY),
439 RADV_BO_PRIORITY_SHADER);
440 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
441 list_inithead(&slab->shaders);
442
443 mtx_lock(&device->shader_slab_mutex);
444 list_add(&slab->slabs, &device->shader_slabs);
445
446 shader->bo = slab->bo;
447 shader->bo_offset = 0;
448 list_add(&shader->slab_list, &slab->shaders);
449 mtx_unlock(&device->shader_slab_mutex);
450 return slab->ptr;
451 }
452
453 void
454 radv_destroy_shader_slabs(struct radv_device *device)
455 {
456 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
457 device->ws->buffer_destroy(slab->bo);
458 free(slab);
459 }
460 mtx_destroy(&device->shader_slab_mutex);
461 }
462
463 /* For the UMR disassembler. */
464 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
465 #define DEBUGGER_NUM_MARKERS 5
466
467 static unsigned
468 radv_get_shader_binary_size(size_t code_size)
469 {
470 return code_size + DEBUGGER_NUM_MARKERS * 4;
471 }
472
473 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
474 const struct ac_shader_config *config_in,
475 const struct radv_shader_variant_info *info,
476 gl_shader_stage stage,
477 struct ac_shader_config *config_out)
478 {
479 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
480 unsigned vgpr_comp_cnt = 0;
481 unsigned num_input_vgprs = info->num_input_vgprs;
482
483 if (stage == MESA_SHADER_FRAGMENT) {
484 num_input_vgprs = 0;
485 if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
486 num_input_vgprs += 2;
487 if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
488 num_input_vgprs += 2;
489 if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
490 num_input_vgprs += 2;
491 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
492 num_input_vgprs += 3;
493 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
494 num_input_vgprs += 2;
495 if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
496 num_input_vgprs += 2;
497 if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
498 num_input_vgprs += 2;
499 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
500 num_input_vgprs += 1;
501 if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
502 num_input_vgprs += 1;
503 if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
504 num_input_vgprs += 1;
505 if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
506 num_input_vgprs += 1;
507 if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
508 num_input_vgprs += 1;
509 if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
510 num_input_vgprs += 1;
511 if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
512 num_input_vgprs += 1;
513 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
514 num_input_vgprs += 1;
515 if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
516 num_input_vgprs += 1;
517 }
518
519 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
520 /* +3 for scratch wave offset and VCC */
521 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
522
523 *config_out = *config_in;
524 config_out->num_vgprs = num_vgprs;
525 config_out->num_sgprs = num_sgprs;
526
527 /* Enable 64-bit and 16-bit denormals, because there is no performance
528 * cost.
529 *
530 * If denormals are enabled, all floating-point output modifiers are
531 * ignored.
532 *
533 * Don't enable denormals for 32-bit floats, because:
534 * - Floating-point output modifiers would be ignored by the hw.
535 * - Some opcodes don't support denormals, such as v_mad_f32. We would
536 * have to stop using those.
537 * - GFX6 & GFX7 would be very slow.
538 */
539 config_out->float_mode |= V_00B028_FP_64_DENORMS;
540
541 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
542 S_00B12C_SCRATCH_EN(scratch_enabled);
543
544 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / 4) |
545 S_00B848_DX10_CLAMP(1) |
546 S_00B848_FLOAT_MODE(config_out->float_mode);
547
548 if (pdevice->rad_info.chip_class >= GFX10) {
549 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
550 } else {
551 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
552 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5) |
553 S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
554 S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
555 S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
556 S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
557 S_00B12C_SO_EN(!!info->info.so.num_outputs);
558 }
559
560 switch (stage) {
561 case MESA_SHADER_TESS_EVAL:
562 if (info->tes.as_es) {
563 assert(pdevice->rad_info.chip_class <= GFX8);
564 vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
565 } else {
566 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
567 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
568
569 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
570 }
571 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
572 break;
573 case MESA_SHADER_TESS_CTRL:
574 if (pdevice->rad_info.chip_class >= GFX9) {
575 /* We need at least 2 components for LS.
576 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
577 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
578 */
579 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
580 } else {
581 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
582 }
583 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
584 break;
585 case MESA_SHADER_VERTEX:
586 if (info->vs.as_ls) {
587 assert(pdevice->rad_info.chip_class <= GFX8);
588 /* We need at least 2 components for LS.
589 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
590 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
591 */
592 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
593 } else if (info->vs.as_es) {
594 assert(pdevice->rad_info.chip_class <= GFX8);
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
597 } else {
598 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
599 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
600 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
601 */
602 if (info->vs.export_prim_id) {
603 vgpr_comp_cnt = 2;
604 } else if (info->info.vs.needs_instance_id) {
605 vgpr_comp_cnt = 1;
606 } else {
607 vgpr_comp_cnt = 0;
608 }
609
610 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
611 }
612 break;
613 case MESA_SHADER_FRAGMENT:
614 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
615 break;
616 case MESA_SHADER_GEOMETRY:
617 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
618 break;
619 case MESA_SHADER_COMPUTE:
620 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
621 config_out->rsrc2 |=
622 S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) |
623 S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) |
624 S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) |
625 S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 :
626 info->info.cs.uses_thread_id[1] ? 1 : 0) |
627 S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) |
628 S_00B84C_LDS_SIZE(config_in->lds_size);
629 break;
630 default:
631 unreachable("unsupported shader type");
632 break;
633 }
634
635 if (pdevice->rad_info.chip_class >= GFX9 &&
636 stage == MESA_SHADER_GEOMETRY) {
637 unsigned es_type = info->gs.es_type;
638 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
639
640 if (es_type == MESA_SHADER_VERTEX) {
641 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
642 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
643 } else if (es_type == MESA_SHADER_TESS_EVAL) {
644 es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
645 } else {
646 unreachable("invalid shader ES type");
647 }
648
649 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
650 * VGPR[0:4] are always loaded.
651 */
652 if (info->info.uses_invocation_id) {
653 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
654 } else if (info->info.uses_prim_id) {
655 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
656 } else if (info->gs.vertices_in >= 3) {
657 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
658 } else {
659 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
660 }
661
662 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
663 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
664 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
665 } else if (pdevice->rad_info.chip_class >= GFX9 &&
666 stage == MESA_SHADER_TESS_CTRL) {
667 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
668 } else {
669 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
670 }
671 }
672
673 static void radv_init_llvm_target()
674 {
675 LLVMInitializeAMDGPUTargetInfo();
676 LLVMInitializeAMDGPUTarget();
677 LLVMInitializeAMDGPUTargetMC();
678 LLVMInitializeAMDGPUAsmPrinter();
679
680 /* For inline assembly. */
681 LLVMInitializeAMDGPUAsmParser();
682
683 /* Workaround for bug in llvm 4.0 that causes image intrinsics
684 * to disappear.
685 * https://reviews.llvm.org/D26348
686 *
687 * Workaround for bug in llvm that causes the GPU to hang in presence
688 * of nested loops because there is an exec mask issue. The proper
689 * solution is to fix LLVM but this might require a bunch of work.
690 * https://bugs.llvm.org/show_bug.cgi?id=37744
691 *
692 * "mesa" is the prefix for error messages.
693 */
694 if (HAVE_LLVM >= 0x0800) {
695 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
696 LLVMParseCommandLineOptions(2, argv, NULL);
697
698 } else {
699 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
700 "-amdgpu-skip-threshold=1" };
701 LLVMParseCommandLineOptions(3, argv, NULL);
702 }
703 }
704
705 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
706
707 static void radv_init_llvm_once(void)
708 {
709 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
710 }
711
712 struct radv_shader_variant *
713 radv_shader_variant_create(struct radv_device *device,
714 const struct radv_shader_binary *binary)
715 {
716 struct ac_shader_config config = {0};
717 struct ac_rtld_binary rtld_binary = {0};
718 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
719 if (!variant)
720 return NULL;
721
722 variant->ref_count = 1;
723
724 if (binary->type == RADV_BINARY_TYPE_RTLD) {
725 struct ac_rtld_symbol lds_symbols[1];
726 unsigned num_lds_symbols = 0;
727 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
728 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
729
730 if (device->physical_device->rad_info.chip_class >= GFX9 &&
731 binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) {
732 /* We add this symbol even on LLVM <= 8 to ensure that
733 * shader->config.lds_size is set correctly below.
734 */
735 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
736 sym->name = "esgs_ring";
737 sym->size = 32 * 1024;
738 sym->align = 64 * 1024;
739 }
740 struct ac_rtld_open_info open_info = {
741 .info = &device->physical_device->rad_info,
742 .shader_type = binary->stage,
743 .num_parts = 1,
744 .elf_ptrs = &elf_data,
745 .elf_sizes = &elf_size,
746 .num_shared_lds_symbols = num_lds_symbols,
747 .shared_lds_symbols = lds_symbols,
748 };
749
750 if (!ac_rtld_open(&rtld_binary, open_info)) {
751 free(variant);
752 return NULL;
753 }
754
755 if (!ac_rtld_read_config(&rtld_binary, &config)) {
756 ac_rtld_close(&rtld_binary);
757 free(variant);
758 return NULL;
759 }
760
761 if (rtld_binary.lds_size > 0) {
762 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
763 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
764 }
765
766 variant->code_size = rtld_binary.rx_size;
767 } else {
768 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
769 config = ((struct radv_shader_binary_legacy *)binary)->config;
770 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
771 }
772
773 variant->info = binary->variant_info;
774 radv_postprocess_config(device->physical_device, &config, &binary->variant_info,
775 binary->stage, &variant->config);
776
777 void *dest_ptr = radv_alloc_shader_memory(device, variant);
778
779 if (binary->type == RADV_BINARY_TYPE_RTLD) {
780 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
781 struct ac_rtld_upload_info info = {
782 .binary = &rtld_binary,
783 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
784 .rx_ptr = dest_ptr,
785 };
786
787 if (!ac_rtld_upload(&info)) {
788 radv_shader_variant_destroy(device, variant);
789 ac_rtld_close(&rtld_binary);
790 return NULL;
791 }
792
793 const char *disasm_data;
794 size_t disasm_size;
795 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
796 radv_shader_variant_destroy(device, variant);
797 ac_rtld_close(&rtld_binary);
798 return NULL;
799 }
800
801 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
802 variant->disasm_string = malloc(disasm_size + 1);
803 memcpy(variant->disasm_string, disasm_data, disasm_size);
804 variant->disasm_string[disasm_size] = 0;
805
806 ac_rtld_close(&rtld_binary);
807 } else {
808 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
809 memcpy(dest_ptr, bin->data, bin->code_size);
810
811 /* Add end-of-code markers for the UMR disassembler. */
812 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
813 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
814 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
815
816 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
817 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
818 }
819 return variant;
820 }
821
822 static struct radv_shader_variant *
823 shader_variant_compile(struct radv_device *device,
824 struct radv_shader_module *module,
825 struct nir_shader * const *shaders,
826 int shader_count,
827 gl_shader_stage stage,
828 struct radv_nir_compiler_options *options,
829 bool gs_copy_shader,
830 struct radv_shader_binary **binary_out)
831 {
832 enum radeon_family chip_family = device->physical_device->rad_info.family;
833 enum ac_target_machine_options tm_options = 0;
834 struct ac_llvm_compiler ac_llvm;
835 struct radv_shader_binary *binary = NULL;
836 struct radv_shader_variant_info variant_info = {0};
837 bool thread_compiler;
838
839 options->family = chip_family;
840 options->chip_class = device->physical_device->rad_info.chip_class;
841 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
842 options->dump_preoptir = options->dump_shader &&
843 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
844 options->record_llvm_ir = device->keep_shader_info;
845 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
846 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
847 options->address32_hi = device->physical_device->rad_info.address32_hi;
848
849 if (options->supports_spill)
850 tm_options |= AC_TM_SUPPORTS_SPILL;
851 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
852 tm_options |= AC_TM_SISCHED;
853 if (options->check_ir)
854 tm_options |= AC_TM_CHECK_IR;
855 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
856 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
857
858 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
859 radv_init_llvm_once();
860 radv_init_llvm_compiler(&ac_llvm,
861 thread_compiler,
862 chip_family, tm_options);
863 if (gs_copy_shader) {
864 assert(shader_count == 1);
865 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
866 &variant_info, options);
867 } else {
868 radv_compile_nir_shader(&ac_llvm, &binary, &variant_info,
869 shaders, shader_count, options);
870 }
871 binary->variant_info = variant_info;
872
873 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
874
875 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary);
876 if (!variant) {
877 free(binary);
878 return NULL;
879 }
880
881 if (options->dump_shader) {
882 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
883 }
884
885
886 if (device->keep_shader_info) {
887 if (!gs_copy_shader && !module->nir) {
888 variant->nir = *shaders;
889 variant->spirv = (uint32_t *)module->data;
890 variant->spirv_size = module->size;
891 }
892 }
893
894 if (binary_out)
895 *binary_out = binary;
896 else
897 free(binary);
898
899 return variant;
900 }
901
902 struct radv_shader_variant *
903 radv_shader_variant_compile(struct radv_device *device,
904 struct radv_shader_module *module,
905 struct nir_shader *const *shaders,
906 int shader_count,
907 struct radv_pipeline_layout *layout,
908 const struct radv_shader_variant_key *key,
909 struct radv_shader_binary **binary_out)
910 {
911 struct radv_nir_compiler_options options = {0};
912
913 options.layout = layout;
914 if (key)
915 options.key = *key;
916
917 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
918 options.supports_spill = true;
919
920 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
921 &options, false, binary_out);
922 }
923
924 struct radv_shader_variant *
925 radv_create_gs_copy_shader(struct radv_device *device,
926 struct nir_shader *shader,
927 struct radv_shader_binary **binary_out,
928 bool multiview)
929 {
930 struct radv_nir_compiler_options options = {0};
931
932 options.key.has_multiview_view_index = multiview;
933
934 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
935 &options, true, binary_out);
936 }
937
938 void
939 radv_shader_variant_destroy(struct radv_device *device,
940 struct radv_shader_variant *variant)
941 {
942 if (!p_atomic_dec_zero(&variant->ref_count))
943 return;
944
945 mtx_lock(&device->shader_slab_mutex);
946 list_del(&variant->slab_list);
947 mtx_unlock(&device->shader_slab_mutex);
948
949 ralloc_free(variant->nir);
950 free(variant->disasm_string);
951 free(variant->llvm_ir_string);
952 free(variant);
953 }
954
955 const char *
956 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
957 {
958 switch (stage) {
959 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
960 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
961 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
962 case MESA_SHADER_COMPUTE: return "Compute Shader";
963 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
964 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
965 default:
966 return "Unknown shader";
967 };
968 }
969
970 static void
971 generate_shader_stats(struct radv_device *device,
972 struct radv_shader_variant *variant,
973 gl_shader_stage stage,
974 struct _mesa_string_buffer *buf)
975 {
976 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
977 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
978 struct ac_shader_config *conf;
979 unsigned max_simd_waves;
980 unsigned lds_per_wave = 0;
981
982 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
983
984 conf = &variant->config;
985
986 if (stage == MESA_SHADER_FRAGMENT) {
987 lds_per_wave = conf->lds_size * lds_increment +
988 align(variant->info.fs.num_interp * 48,
989 lds_increment);
990 } else if (stage == MESA_SHADER_COMPUTE) {
991 unsigned max_workgroup_size =
992 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
993 lds_per_wave = (conf->lds_size * lds_increment) /
994 DIV_ROUND_UP(max_workgroup_size, 64);
995 }
996
997 if (conf->num_sgprs)
998 max_simd_waves =
999 MIN2(max_simd_waves,
1000 ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
1001
1002 if (conf->num_vgprs)
1003 max_simd_waves =
1004 MIN2(max_simd_waves,
1005 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1006
1007 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1008 * that PS can use.
1009 */
1010 if (lds_per_wave)
1011 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1012
1013 if (stage == MESA_SHADER_FRAGMENT) {
1014 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1015 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1016 "SPI_PS_INPUT_ENA = 0x%04x\n",
1017 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1018 }
1019
1020 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1021 "SGPRS: %d\n"
1022 "VGPRS: %d\n"
1023 "Spilled SGPRs: %d\n"
1024 "Spilled VGPRs: %d\n"
1025 "PrivMem VGPRS: %d\n"
1026 "Code Size: %d bytes\n"
1027 "LDS: %d blocks\n"
1028 "Scratch: %d bytes per wave\n"
1029 "Max Waves: %d\n"
1030 "********************\n\n\n",
1031 conf->num_sgprs, conf->num_vgprs,
1032 conf->spilled_sgprs, conf->spilled_vgprs,
1033 variant->info.private_mem_vgprs, variant->code_size,
1034 conf->lds_size, conf->scratch_bytes_per_wave,
1035 max_simd_waves);
1036 }
1037
1038 void
1039 radv_shader_dump_stats(struct radv_device *device,
1040 struct radv_shader_variant *variant,
1041 gl_shader_stage stage,
1042 FILE *file)
1043 {
1044 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1045
1046 generate_shader_stats(device, variant, stage, buf);
1047
1048 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
1049 fprintf(file, "%s", buf->buf);
1050
1051 _mesa_string_buffer_destroy(buf);
1052 }
1053
1054 VkResult
1055 radv_GetShaderInfoAMD(VkDevice _device,
1056 VkPipeline _pipeline,
1057 VkShaderStageFlagBits shaderStage,
1058 VkShaderInfoTypeAMD infoType,
1059 size_t* pInfoSize,
1060 void* pInfo)
1061 {
1062 RADV_FROM_HANDLE(radv_device, device, _device);
1063 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1064 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1065 struct radv_shader_variant *variant = pipeline->shaders[stage];
1066 struct _mesa_string_buffer *buf;
1067 VkResult result = VK_SUCCESS;
1068
1069 /* Spec doesn't indicate what to do if the stage is invalid, so just
1070 * return no info for this. */
1071 if (!variant)
1072 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1073
1074 switch (infoType) {
1075 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1076 if (!pInfo) {
1077 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1078 } else {
1079 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1080 struct ac_shader_config *conf = &variant->config;
1081
1082 VkShaderStatisticsInfoAMD statistics = {};
1083 statistics.shaderStageMask = shaderStage;
1084 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1085 statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
1086 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1087
1088 if (stage == MESA_SHADER_COMPUTE) {
1089 unsigned *local_size = variant->nir->info.cs.local_size;
1090 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1091
1092 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1093 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1094
1095 statistics.computeWorkGroupSize[0] = local_size[0];
1096 statistics.computeWorkGroupSize[1] = local_size[1];
1097 statistics.computeWorkGroupSize[2] = local_size[2];
1098 } else {
1099 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1100 }
1101
1102 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1103 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1104 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1105 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1106 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1107
1108 size_t size = *pInfoSize;
1109 *pInfoSize = sizeof(statistics);
1110
1111 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1112
1113 if (size < *pInfoSize)
1114 result = VK_INCOMPLETE;
1115 }
1116
1117 break;
1118 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1119 buf = _mesa_string_buffer_create(NULL, 1024);
1120
1121 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
1122 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
1123 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1124 generate_shader_stats(device, variant, stage, buf);
1125
1126 /* Need to include the null terminator. */
1127 size_t length = buf->length + 1;
1128
1129 if (!pInfo) {
1130 *pInfoSize = length;
1131 } else {
1132 size_t size = *pInfoSize;
1133 *pInfoSize = length;
1134
1135 memcpy(pInfo, buf->buf, MIN2(size, length));
1136
1137 if (size < length)
1138 result = VK_INCOMPLETE;
1139 }
1140
1141 _mesa_string_buffer_destroy(buf);
1142 break;
1143 default:
1144 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1145 result = VK_ERROR_FEATURE_NOT_PRESENT;
1146 break;
1147 }
1148
1149 return result;
1150 }