src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39 #include <llvm-c/Support.h>
  40
  41 #include "sid.h"
  42 #include "gfx9d.h"
  43 #include "ac_binary.h"
  44 #include "ac_llvm_util.h"
  45 #include "ac_nir_to_llvm.h"
  46 #include "vk_format.h"
  47 #include "util/debug.h"
  48 #include "ac_exp_param.h"
  49
  50 #include "util/string_buffer.h"
  51
  52 static const struct nir_shader_compiler_options nir_options = {
  53         .vertex_id_zero_based = true,
  54         .lower_scmp = true,
  55         .lower_flrp32 = true,
  56         .lower_flrp64 = true,
  57         .lower_device_index_to_zero = true,
  58         .lower_fsat = true,
  59         .lower_fdiv = true,
  60         .lower_sub = true,
  61         .lower_pack_snorm_2x16 = true,
  62         .lower_pack_snorm_4x8 = true,
  63         .lower_pack_unorm_2x16 = true,
  64         .lower_pack_unorm_4x8 = true,
  65         .lower_unpack_snorm_2x16 = true,
  66         .lower_unpack_snorm_4x8 = true,
  67         .lower_unpack_unorm_2x16 = true,
  68         .lower_unpack_unorm_4x8 = true,
  69         .lower_extract_byte = true,
  70         .lower_extract_word = true,
  71         .lower_ffma = true,
  72         .lower_fpow = true,
  73         .vs_inputs_dual_locations = true,
  74         .max_unroll_iterations = 32
  75 };
  76
  77 VkResult radv_CreateShaderModule(
  78         VkDevice                                    _device,
  79         const VkShaderModuleCreateInfo*             pCreateInfo,
  80         const VkAllocationCallbacks*                pAllocator,
  81         VkShaderModule*                             pShaderModule)
  82 {
  83         RADV_FROM_HANDLE(radv_device, device, _device);
  84         struct radv_shader_module *module;
  85
  86         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  87         assert(pCreateInfo->flags == 0);
  88
  89         module = vk_alloc2(&device->alloc, pAllocator,
  90                              sizeof(*module) + pCreateInfo->codeSize, 8,
  91                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  92         if (module == NULL)
  93                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  94
  95         module->nir = NULL;
  96         module->size = pCreateInfo->codeSize;
  97         memcpy(module->data, pCreateInfo->pCode, module->size);
  98
  99         _mesa_sha1_compute(module->data, module->size, module->sha1);
 100
 101         *pShaderModule = radv_shader_module_to_handle(module);
 102
 103         return VK_SUCCESS;
 104 }
 105
 106 void radv_DestroyShaderModule(
 107         VkDevice                                    _device,
 108         VkShaderModule                              _module,
 109         const VkAllocationCallbacks*                pAllocator)
 110 {
 111         RADV_FROM_HANDLE(radv_device, device, _device);
 112         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 113
 114         if (!module)
 115                 return;
 116
 117         vk_free2(&device->alloc, pAllocator, module);
 118 }
 119
 120 void
 121 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
 122 {
 123         bool progress;
 124
 125         do {
 126                 progress = false;
 127
 128                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 129                 NIR_PASS_V(shader, nir_lower_pack);
 130                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 131                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 132
 133                 NIR_PASS(progress, shader, nir_copy_prop);
 134                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 135                 NIR_PASS(progress, shader, nir_opt_dce);
 136                 if (nir_opt_trivial_continues(shader)) {
 137                         progress = true;
 138                         NIR_PASS(progress, shader, nir_copy_prop);
 139                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 140                         NIR_PASS(progress, shader, nir_opt_dce);
 141                 }
 142                 NIR_PASS(progress, shader, nir_opt_if);
 143                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 144                 NIR_PASS(progress, shader, nir_opt_cse);
 145                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 146                 NIR_PASS(progress, shader, nir_opt_algebraic);
 147                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 148                 NIR_PASS(progress, shader, nir_opt_undef);
 149                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 150                 if (shader->options->max_unroll_iterations) {
 151                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 152                 }
 153         } while (progress && !optimize_conservatively);
 154
 155         NIR_PASS(progress, shader, nir_opt_shrink_load);
 156         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 157 }
 158
 159 nir_shader *
 160 radv_shader_compile_to_nir(struct radv_device *device,
 161                            struct radv_shader_module *module,
 162                            const char *entrypoint_name,
 163                            gl_shader_stage stage,
 164                            const VkSpecializationInfo *spec_info,
 165                            const VkPipelineCreateFlags flags)
 166 {
 167         nir_shader *nir;
 168         nir_function *entry_point;
 169         if (module->nir) {
 170                 /* Some things such as our meta clear/blit code will give us a NIR
 171                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 172                  * and just use the NIR shader */
 173                 nir = module->nir;
 174                 nir->options = &nir_options;
 175                 nir_validate_shader(nir);
 176
 177                 assert(exec_list_length(&nir->functions) == 1);
 178                 struct exec_node *node = exec_list_get_head(&nir->functions);
 179                 entry_point = exec_node_data(nir_function, node, node);
 180
 181                 NIR_PASS_V(nir, nir_lower_deref_instrs, ~0);
 182         } else {
 183                 uint32_t *spirv = (uint32_t *) module->data;
 184                 assert(module->size % 4 == 0);
 185
 186                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 187                         radv_print_spirv(spirv, module->size, stderr);
 188
 189                 uint32_t num_spec_entries = 0;
 190                 struct nir_spirv_specialization *spec_entries = NULL;
 191                 if (spec_info && spec_info->mapEntryCount > 0) {
 192                         num_spec_entries = spec_info->mapEntryCount;
 193                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 194                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 195                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 196                                 const void *data = spec_info->pData + entry.offset;
 197                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 198
 199                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 200                                 if (spec_info->dataSize == 8)
 201                                         spec_entries[i].data64 = *(const uint64_t *)data;
 202                                 else
 203                                         spec_entries[i].data32 = *(const uint32_t *)data;
 204                         }
 205                 }
 206                 const struct spirv_to_nir_options spirv_options = {
 207                         .caps = {
 208                                 .device_group = true,
 209                                 .draw_parameters = true,
 210                                 .float64 = true,
 211                                 .image_read_without_format = true,
 212                                 .image_write_without_format = true,
 213                                 .tessellation = true,
 214                                 .int64 = true,
 215                                 .multiview = true,
 216                                 .subgroup_ballot = true,
 217                                 .subgroup_basic = true,
 218                                 .subgroup_quad = true,
 219                                 .subgroup_shuffle = true,
 220                                 .subgroup_vote = true,
 221                                 .variable_pointers = true,
 222                                 .gcn_shader = true,
 223                                 .trinary_minmax = true,
 224                                 .shader_viewport_index_layer = true,
 225                                 .descriptor_array_dynamic_indexing = true,
 226                                 .runtime_descriptor_array = true,
 227                         },
 228                 };
 229                 entry_point = spirv_to_nir(spirv, module->size / 4,
 230                                            spec_entries, num_spec_entries,
 231                                            stage, entrypoint_name,
 232                                            &spirv_options, &nir_options);
 233                 nir = entry_point->shader;
 234                 assert(nir->info.stage == stage);
 235                 nir_validate_shader(nir);
 236
 237                 free(spec_entries);
 238
 239                 NIR_PASS_V(nir, nir_lower_deref_instrs, ~0);
 240
 241                 /* We have to lower away local constant initializers right before we
 242                  * inline functions.  That way they get properly initialized at the top
 243                  * of the function and not at the top of its caller.
 244                  */
 245                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 246                 NIR_PASS_V(nir, nir_lower_returns);
 247                 NIR_PASS_V(nir, nir_inline_functions);
 248
 249                 /* Pick off the single entrypoint that we want */
 250                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 251                         if (func != entry_point)
 252                                 exec_node_remove(&func->node);
 253                 }
 254                 assert(exec_list_length(&nir->functions) == 1);
 255                 entry_point->name = ralloc_strdup(entry_point, "main");
 256
 257                 /* Make sure we lower constant initializers on output variables so that
 258                  * nir_remove_dead_variables below sees the corresponding stores
 259                  */
 260                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 261
 262                 NIR_PASS_V(nir, nir_remove_dead_variables,
 263                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 264
 265                 /* Now that we've deleted all but the main function, we can go ahead and
 266                  * lower the rest of the constant initializers.
 267                  */
 268                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 269
 270                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 271                  * it doesn't lower system values to temporaries by accident.
 272                  */
 273                 NIR_PASS_V(nir, nir_split_var_copies);
 274                 NIR_PASS_V(nir, nir_split_per_member_structs);
 275
 276                 NIR_PASS_V(nir, nir_lower_system_values);
 277                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 278         }
 279
 280         /* Vulkan uses the separate-shader linking model */
 281         nir->info.separate_shader = true;
 282
 283         nir_shader_gather_info(nir, entry_point->impl);
 284
 285         static const nir_lower_tex_options tex_options = {
 286           .lower_txp = ~0,
 287         };
 288
 289         nir_lower_tex(nir, &tex_options);
 290
 291         nir_lower_vars_to_ssa(nir);
 292
 293         if (nir->info.stage == MESA_SHADER_VERTEX ||
 294             nir->info.stage == MESA_SHADER_GEOMETRY) {
 295                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 296                            nir_shader_get_entrypoint(nir), true, true);
 297         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 298                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 299                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 300                            nir_shader_get_entrypoint(nir), true, false);
 301         }
 302
 303         nir_split_var_copies(nir);
 304         nir_lower_var_copies(nir);
 305
 306         nir_lower_global_vars_to_local(nir);
 307         nir_remove_dead_variables(nir, nir_var_local);
 308         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 309                         .subgroup_size = 64,
 310                         .ballot_bit_size = 64,
 311                         .lower_to_scalar = 1,
 312                         .lower_subgroup_masks = 1,
 313                         .lower_shuffle = 1,
 314                         .lower_shuffle_to_32bit = 1,
 315                         .lower_vote_eq_to_ballot = 1,
 316                 });
 317
 318         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 319                 radv_optimize_nir(nir, false);
 320
 321         /* Indirect lowering must be called after the radv_optimize_nir() loop
 322          * has been called at least once. Otherwise indirect lowering can
 323          * bloat the instruction count of the loop and cause it to be
 324          * considered too large for unrolling.
 325          */
 326         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 327         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
 328
 329         return nir;
 330 }
 331
 332 void *
 333 radv_alloc_shader_memory(struct radv_device *device,
 334                          struct radv_shader_variant *shader)
 335 {
 336         mtx_lock(&device->shader_slab_mutex);
 337         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 338                 uint64_t offset = 0;
 339                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 340                         if (s->bo_offset - offset >= shader->code_size) {
 341                                 shader->bo = slab->bo;
 342                                 shader->bo_offset = offset;
 343                                 list_addtail(&shader->slab_list, &s->slab_list);
 344                                 mtx_unlock(&device->shader_slab_mutex);
 345                                 return slab->ptr + offset;
 346                         }
 347                         offset = align_u64(s->bo_offset + s->code_size, 256);
 348                 }
 349                 if (slab->size - offset >= shader->code_size) {
 350                         shader->bo = slab->bo;
 351                         shader->bo_offset = offset;
 352                         list_addtail(&shader->slab_list, &slab->shaders);
 353                         mtx_unlock(&device->shader_slab_mutex);
 354                         return slab->ptr + offset;
 355                 }
 356         }
 357
 358         mtx_unlock(&device->shader_slab_mutex);
 359         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 360
 361         slab->size = 256 * 1024;
 362         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 363                                              RADEON_DOMAIN_VRAM,
 364                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 365                                              device->physical_device->cpdma_prefetch_writes_memory ?
 366                                                      0 : RADEON_FLAG_READ_ONLY);
 367         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 368         list_inithead(&slab->shaders);
 369
 370         mtx_lock(&device->shader_slab_mutex);
 371         list_add(&slab->slabs, &device->shader_slabs);
 372
 373         shader->bo = slab->bo;
 374         shader->bo_offset = 0;
 375         list_add(&shader->slab_list, &slab->shaders);
 376         mtx_unlock(&device->shader_slab_mutex);
 377         return slab->ptr;
 378 }
 379
 380 void
 381 radv_destroy_shader_slabs(struct radv_device *device)
 382 {
 383         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 384                 device->ws->buffer_destroy(slab->bo);
 385                 free(slab);
 386         }
 387         mtx_destroy(&device->shader_slab_mutex);
 388 }
 389
 390 static void
 391 radv_fill_shader_variant(struct radv_device *device,
 392                          struct radv_shader_variant *variant,
 393                          struct ac_shader_binary *binary,
 394                          gl_shader_stage stage)
 395 {
 396         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 397         struct radv_shader_info *info = &variant->info.info;
 398         unsigned vgpr_comp_cnt = 0;
 399
 400         variant->code_size = binary->code_size;
 401         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 402                          S_00B12C_SCRATCH_EN(scratch_enabled);
 403
 404         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 405                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 406                 S_00B848_DX10_CLAMP(1) |
 407                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 408
 409         switch (stage) {
 410         case MESA_SHADER_TESS_EVAL:
 411                 vgpr_comp_cnt = 3;
 412                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 413                 break;
 414         case MESA_SHADER_TESS_CTRL:
 415                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 416                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 417                 } else {
 418                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 419                 }
 420                 break;
 421         case MESA_SHADER_VERTEX:
 422         case MESA_SHADER_GEOMETRY:
 423                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 424                 break;
 425         case MESA_SHADER_FRAGMENT:
 426                 break;
 427         case MESA_SHADER_COMPUTE:
 428                 variant->rsrc2 |=
 429                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 430                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 431                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 432                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 433                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 434                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 435                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 436                 break;
 437         default:
 438                 unreachable("unsupported shader type");
 439                 break;
 440         }
 441
 442         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 443             stage == MESA_SHADER_GEOMETRY) {
 444                 unsigned es_type = variant->info.gs.es_type;
 445                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 446
 447                 if (es_type == MESA_SHADER_VERTEX) {
 448                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 449                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 450                         es_vgpr_comp_cnt = 3;
 451                 } else {
 452                         unreachable("invalid shader ES type");
 453                 }
 454
 455                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 456                  * VGPR[0:4] are always loaded.
 457                  */
 458                 if (info->uses_invocation_id) {
 459                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 460                 } else if (info->uses_prim_id) {
 461                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 462                 } else if (variant->info.gs.vertices_in >= 3) {
 463                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 464                 } else {
 465                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 466                 }
 467
 468                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 469                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 470                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 471         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 472                    stage == MESA_SHADER_TESS_CTRL) {
 473                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 474         } else {
 475                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 476         }
 477
 478         void *ptr = radv_alloc_shader_memory(device, variant);
 479         memcpy(ptr, binary->code, binary->code_size);
 480 }
 481
 482 static void radv_init_llvm_target()
 483 {
 484         LLVMInitializeAMDGPUTargetInfo();
 485         LLVMInitializeAMDGPUTarget();
 486         LLVMInitializeAMDGPUTargetMC();
 487         LLVMInitializeAMDGPUAsmPrinter();
 488
 489         /* For inline assembly. */
 490         LLVMInitializeAMDGPUAsmParser();
 491
 492         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 493          * to disappear.
 494          * https://reviews.llvm.org/D26348
 495          *
 496          * Workaround for bug in llvm that causes the GPU to hang in presence
 497          * of nested loops because there is an exec mask issue. The proper
 498          * solution is to fix LLVM but this might require a bunch of work.
 499          * https://bugs.llvm.org/show_bug.cgi?id=37744
 500          *
 501          * "mesa" is the prefix for error messages.
 502          */
 503         const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 504                                 "-amdgpu-skip-threshold=1" };
 505         LLVMParseCommandLineOptions(3, argv, NULL);
 506 }
 507
 508 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 509
 510 static LLVMTargetRef radv_get_llvm_target(const char *triple)
 511 {
 512         LLVMTargetRef target = NULL;
 513         char *err_message = NULL;
 514
 515         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 516
 517         if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
 518                 fprintf(stderr, "Cannot find target for triple %s ", triple);
 519                 if (err_message) {
 520                         fprintf(stderr, "%s\n", err_message);
 521                 }
 522                 LLVMDisposeMessage(err_message);
 523                 return NULL;
 524         }
 525         return target;
 526 }
 527
 528 static LLVMTargetMachineRef radv_create_target_machine(enum radeon_family family,
 529                                                        enum ac_target_machine_options tm_options,
 530                                                        const char **out_triple)
 531 {
 532         assert(family >= CHIP_TAHITI);
 533         char features[256];
 534         const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
 535         LLVMTargetRef target = radv_get_llvm_target(triple);
 536
 537         snprintf(features, sizeof(features),
 538                  "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
 539                  tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
 540                  tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 541                  tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
 542                  tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "");
 543
 544         LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 545                                      target,
 546                                      triple,
 547                                      ac_get_llvm_processor_name(family),
 548                                      features,
 549                                      LLVMCodeGenLevelDefault,
 550                                      LLVMRelocDefault,
 551                                      LLVMCodeModelDefault);
 552
 553         if (out_triple)
 554                 *out_triple = triple;
 555         return tm;
 556 }
 557
 558 static struct radv_shader_variant *
 559 shader_variant_create(struct radv_device *device,
 560                       struct radv_shader_module *module,
 561                       struct nir_shader * const *shaders,
 562                       int shader_count,
 563                       gl_shader_stage stage,
 564                       struct radv_nir_compiler_options *options,
 565                       bool gs_copy_shader,
 566                       void **code_out,
 567                       unsigned *code_size_out)
 568 {
 569         enum radeon_family chip_family = device->physical_device->rad_info.family;
 570         enum ac_target_machine_options tm_options = 0;
 571         struct radv_shader_variant *variant;
 572         struct ac_shader_binary binary;
 573         LLVMTargetMachineRef tm;
 574
 575         variant = calloc(1, sizeof(struct radv_shader_variant));
 576         if (!variant)
 577                 return NULL;
 578
 579         options->family = chip_family;
 580         options->chip_class = device->physical_device->rad_info.chip_class;
 581         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 582         options->dump_preoptir = options->dump_shader &&
 583                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 584         options->record_llvm_ir = device->keep_shader_info;
 585         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 586         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 587         options->address32_hi = device->physical_device->rad_info.address32_hi;
 588
 589         if (options->supports_spill)
 590                 tm_options |= AC_TM_SUPPORTS_SPILL;
 591         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 592                 tm_options |= AC_TM_SISCHED;
 593         tm = radv_create_target_machine(chip_family, tm_options, NULL);
 594
 595         if (gs_copy_shader) {
 596                 assert(shader_count == 1);
 597                 radv_compile_gs_copy_shader(tm, *shaders, &binary,
 598                                             &variant->config, &variant->info,
 599                                             options);
 600         } else {
 601                 radv_compile_nir_shader(tm, &binary, &variant->config,
 602                                         &variant->info, shaders, shader_count,
 603                                         options);
 604         }
 605
 606         LLVMDisposeTargetMachine(tm);
 607
 608         radv_fill_shader_variant(device, variant, &binary, stage);
 609
 610         if (code_out) {
 611                 *code_out = binary.code;
 612                 *code_size_out = binary.code_size;
 613         } else
 614                 free(binary.code);
 615         free(binary.config);
 616         free(binary.rodata);
 617         free(binary.global_symbol_offsets);
 618         free(binary.relocs);
 619         variant->ref_count = 1;
 620
 621         if (device->keep_shader_info) {
 622                 variant->disasm_string = binary.disasm_string;
 623                 variant->llvm_ir_string = binary.llvm_ir_string;
 624                 if (!gs_copy_shader && !module->nir) {
 625                         variant->nir = *shaders;
 626                         variant->spirv = (uint32_t *)module->data;
 627                         variant->spirv_size = module->size;
 628                 }
 629         } else {
 630                 free(binary.disasm_string);
 631         }
 632
 633         return variant;
 634 }
 635
 636 struct radv_shader_variant *
 637 radv_shader_variant_create(struct radv_device *device,
 638                            struct radv_shader_module *module,
 639                            struct nir_shader *const *shaders,
 640                            int shader_count,
 641                            struct radv_pipeline_layout *layout,
 642                            const struct radv_shader_variant_key *key,
 643                            void **code_out,
 644                            unsigned *code_size_out)
 645 {
 646         struct radv_nir_compiler_options options = {0};
 647
 648         options.layout = layout;
 649         if (key)
 650                 options.key = *key;
 651
 652         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 653         options.supports_spill = true;
 654
 655         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 656                                      &options, false, code_out, code_size_out);
 657 }
 658
 659 struct radv_shader_variant *
 660 radv_create_gs_copy_shader(struct radv_device *device,
 661                            struct nir_shader *shader,
 662                            void **code_out,
 663                            unsigned *code_size_out,
 664                            bool multiview)
 665 {
 666         struct radv_nir_compiler_options options = {0};
 667
 668         options.key.has_multiview_view_index = multiview;
 669
 670         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 671                                      &options, true, code_out, code_size_out);
 672 }
 673
 674 void
 675 radv_shader_variant_destroy(struct radv_device *device,
 676                             struct radv_shader_variant *variant)
 677 {
 678         if (!p_atomic_dec_zero(&variant->ref_count))
 679                 return;
 680
 681         mtx_lock(&device->shader_slab_mutex);
 682         list_del(&variant->slab_list);
 683         mtx_unlock(&device->shader_slab_mutex);
 684
 685         ralloc_free(variant->nir);
 686         free(variant->disasm_string);
 687         free(variant->llvm_ir_string);
 688         free(variant);
 689 }
 690
 691 const char *
 692 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 693 {
 694         switch (stage) {
 695         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 696         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 697         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 698         case MESA_SHADER_COMPUTE: return "Compute Shader";
 699         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 700         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 701         default:
 702                 return "Unknown shader";
 703         };
 704 }
 705
 706 static void
 707 generate_shader_stats(struct radv_device *device,
 708                       struct radv_shader_variant *variant,
 709                       gl_shader_stage stage,
 710                       struct _mesa_string_buffer *buf)
 711 {
 712         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 713         struct ac_shader_config *conf;
 714         unsigned max_simd_waves;
 715         unsigned lds_per_wave = 0;
 716
 717         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 718
 719         conf = &variant->config;
 720
 721         if (stage == MESA_SHADER_FRAGMENT) {
 722                 lds_per_wave = conf->lds_size * lds_increment +
 723                                align(variant->info.fs.num_interp * 48,
 724                                      lds_increment);
 725         }
 726
 727         if (conf->num_sgprs)
 728                 max_simd_waves =
 729                         MIN2(max_simd_waves,
 730                              radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
 731
 732         if (conf->num_vgprs)
 733                 max_simd_waves =
 734                         MIN2(max_simd_waves,
 735                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 736
 737         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 738          * that PS can use.
 739          */
 740         if (lds_per_wave)
 741                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 742
 743         if (stage == MESA_SHADER_FRAGMENT) {
 744                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 745                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 746                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 747                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 748         }
 749
 750         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 751                                    "SGPRS: %d\n"
 752                                    "VGPRS: %d\n"
 753                                    "Spilled SGPRs: %d\n"
 754                                    "Spilled VGPRs: %d\n"
 755                                    "PrivMem VGPRS: %d\n"
 756                                    "Code Size: %d bytes\n"
 757                                    "LDS: %d blocks\n"
 758                                    "Scratch: %d bytes per wave\n"
 759                                    "Max Waves: %d\n"
 760                                    "********************\n\n\n",
 761                                    conf->num_sgprs, conf->num_vgprs,
 762                                    conf->spilled_sgprs, conf->spilled_vgprs,
 763                                    variant->info.private_mem_vgprs, variant->code_size,
 764                                    conf->lds_size, conf->scratch_bytes_per_wave,
 765                                    max_simd_waves);
 766 }
 767
 768 void
 769 radv_shader_dump_stats(struct radv_device *device,
 770                        struct radv_shader_variant *variant,
 771                        gl_shader_stage stage,
 772                        FILE *file)
 773 {
 774         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 775
 776         generate_shader_stats(device, variant, stage, buf);
 777
 778         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 779         fprintf(file, "%s", buf->buf);
 780
 781         _mesa_string_buffer_destroy(buf);
 782 }
 783
 784 VkResult
 785 radv_GetShaderInfoAMD(VkDevice _device,
 786                       VkPipeline _pipeline,
 787                       VkShaderStageFlagBits shaderStage,
 788                       VkShaderInfoTypeAMD infoType,
 789                       size_t* pInfoSize,
 790                       void* pInfo)
 791 {
 792         RADV_FROM_HANDLE(radv_device, device, _device);
 793         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 794         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 795         struct radv_shader_variant *variant = pipeline->shaders[stage];
 796         struct _mesa_string_buffer *buf;
 797         VkResult result = VK_SUCCESS;
 798
 799         /* Spec doesn't indicate what to do if the stage is invalid, so just
 800          * return no info for this. */
 801         if (!variant)
 802                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 803
 804         switch (infoType) {
 805         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 806                 if (!pInfo) {
 807                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 808                 } else {
 809                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 810                         struct ac_shader_config *conf = &variant->config;
 811
 812                         VkShaderStatisticsInfoAMD statistics = {};
 813                         statistics.shaderStageMask = shaderStage;
 814                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 815                         statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
 816                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 817
 818                         if (stage == MESA_SHADER_COMPUTE) {
 819                                 unsigned *local_size = variant->nir->info.cs.local_size;
 820                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 821
 822                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 823                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 824
 825                                 statistics.computeWorkGroupSize[0] = local_size[0];
 826                                 statistics.computeWorkGroupSize[1] = local_size[1];
 827                                 statistics.computeWorkGroupSize[2] = local_size[2];
 828                         } else {
 829                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 830                         }
 831
 832                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 833                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 834                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 835                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 836                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 837
 838                         size_t size = *pInfoSize;
 839                         *pInfoSize = sizeof(statistics);
 840
 841                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 842
 843                         if (size < *pInfoSize)
 844                                 result = VK_INCOMPLETE;
 845                 }
 846
 847                 break;
 848         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 849                 buf = _mesa_string_buffer_create(NULL, 1024);
 850
 851                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 852                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 853                 generate_shader_stats(device, variant, stage, buf);
 854
 855                 /* Need to include the null terminator. */
 856                 size_t length = buf->length + 1;
 857
 858                 if (!pInfo) {
 859                         *pInfoSize = length;
 860                 } else {
 861                         size_t size = *pInfoSize;
 862                         *pInfoSize = length;
 863
 864                         memcpy(pInfo, buf->buf, MIN2(size, length));
 865
 866                         if (size < length)
 867                                 result = VK_INCOMPLETE;
 868                 }
 869
 870                 _mesa_string_buffer_destroy(buf);
 871                 break;
 872         default:
 873                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 874                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 875                 break;
 876         }
 877
 878         return result;
 879 }