2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
49 #include "util/string_buffer.h"
51 static const struct nir_shader_compiler_options nir_options
= {
52 .vertex_id_zero_based
= true,
56 .lower_device_index_to_zero
= true,
60 .lower_pack_snorm_2x16
= true,
61 .lower_pack_snorm_4x8
= true,
62 .lower_pack_unorm_2x16
= true,
63 .lower_pack_unorm_4x8
= true,
64 .lower_unpack_snorm_2x16
= true,
65 .lower_unpack_snorm_4x8
= true,
66 .lower_unpack_unorm_2x16
= true,
67 .lower_unpack_unorm_4x8
= true,
68 .lower_extract_byte
= true,
69 .lower_extract_word
= true,
72 .vs_inputs_dual_locations
= true,
73 .max_unroll_iterations
= 32
76 VkResult
radv_CreateShaderModule(
78 const VkShaderModuleCreateInfo
* pCreateInfo
,
79 const VkAllocationCallbacks
* pAllocator
,
80 VkShaderModule
* pShaderModule
)
82 RADV_FROM_HANDLE(radv_device
, device
, _device
);
83 struct radv_shader_module
*module
;
85 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
86 assert(pCreateInfo
->flags
== 0);
88 module
= vk_alloc2(&device
->alloc
, pAllocator
,
89 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
90 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
92 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
95 module
->size
= pCreateInfo
->codeSize
;
96 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
98 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
100 *pShaderModule
= radv_shader_module_to_handle(module
);
105 void radv_DestroyShaderModule(
107 VkShaderModule _module
,
108 const VkAllocationCallbacks
* pAllocator
)
110 RADV_FROM_HANDLE(radv_device
, device
, _device
);
111 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
116 vk_free2(&device
->alloc
, pAllocator
, module
);
120 radv_optimize_nir(struct nir_shader
*shader
)
127 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
128 NIR_PASS_V(shader
, nir_lower_64bit_pack
);
129 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
130 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
132 NIR_PASS(progress
, shader
, nir_copy_prop
);
133 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
134 NIR_PASS(progress
, shader
, nir_opt_dce
);
135 if (nir_opt_trivial_continues(shader
)) {
137 NIR_PASS(progress
, shader
, nir_copy_prop
);
138 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
139 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_if
);
142 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
143 NIR_PASS(progress
, shader
, nir_opt_cse
);
144 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
145 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
146 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
147 NIR_PASS(progress
, shader
, nir_opt_undef
);
148 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
149 if (shader
->options
->max_unroll_iterations
) {
150 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
154 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
158 radv_shader_compile_to_nir(struct radv_device
*device
,
159 struct radv_shader_module
*module
,
160 const char *entrypoint_name
,
161 gl_shader_stage stage
,
162 const VkSpecializationInfo
*spec_info
)
164 if (strcmp(entrypoint_name
, "main") != 0) {
165 radv_finishme("Multiple shaders per module not really supported");
169 nir_function
*entry_point
;
171 /* Some things such as our meta clear/blit code will give us a NIR
172 * shader directly. In that case, we just ignore the SPIR-V entirely
173 * and just use the NIR shader */
175 nir
->options
= &nir_options
;
176 nir_validate_shader(nir
);
178 assert(exec_list_length(&nir
->functions
) == 1);
179 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
180 entry_point
= exec_node_data(nir_function
, node
, node
);
182 uint32_t *spirv
= (uint32_t *) module
->data
;
183 assert(module
->size
% 4 == 0);
185 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
186 radv_print_spirv(spirv
, module
->size
, stderr
);
188 uint32_t num_spec_entries
= 0;
189 struct nir_spirv_specialization
*spec_entries
= NULL
;
190 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
191 num_spec_entries
= spec_info
->mapEntryCount
;
192 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
193 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
194 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
195 const void *data
= spec_info
->pData
+ entry
.offset
;
196 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
198 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
199 if (spec_info
->dataSize
== 8)
200 spec_entries
[i
].data64
= *(const uint64_t *)data
;
202 spec_entries
[i
].data32
= *(const uint32_t *)data
;
205 const struct spirv_to_nir_options spirv_options
= {
207 .device_group
= true,
208 .draw_parameters
= true,
210 .image_read_without_format
= true,
211 .image_write_without_format
= true,
212 .tessellation
= true,
215 .subgroup_basic
= true,
216 .variable_pointers
= true,
219 .AMD_gcn_shader
= true,
222 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
223 spec_entries
, num_spec_entries
,
224 stage
, entrypoint_name
,
225 &spirv_options
, &nir_options
);
226 nir
= entry_point
->shader
;
227 assert(nir
->info
.stage
== stage
);
228 nir_validate_shader(nir
);
232 /* We have to lower away local constant initializers right before we
233 * inline functions. That way they get properly initialized at the top
234 * of the function and not at the top of its caller.
236 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
237 NIR_PASS_V(nir
, nir_lower_returns
);
238 NIR_PASS_V(nir
, nir_inline_functions
);
240 /* Pick off the single entrypoint that we want */
241 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
242 if (func
!= entry_point
)
243 exec_node_remove(&func
->node
);
245 assert(exec_list_length(&nir
->functions
) == 1);
246 entry_point
->name
= ralloc_strdup(entry_point
, "main");
248 NIR_PASS_V(nir
, nir_remove_dead_variables
,
249 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
251 /* Now that we've deleted all but the main function, we can go ahead and
252 * lower the rest of the constant initializers.
254 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
255 NIR_PASS_V(nir
, nir_lower_system_values
);
256 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
259 /* Vulkan uses the separate-shader linking model */
260 nir
->info
.separate_shader
= true;
262 nir_shader_gather_info(nir
, entry_point
->impl
);
264 static const nir_lower_tex_options tex_options
= {
268 nir_lower_tex(nir
, &tex_options
);
270 nir_lower_vars_to_ssa(nir
);
271 nir_lower_var_copies(nir
);
272 nir_lower_global_vars_to_local(nir
);
273 nir_remove_dead_variables(nir
, nir_var_local
);
274 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
275 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
277 .ballot_bit_size
= 64,
278 .lower_to_scalar
= 1,
279 .lower_subgroup_masks
= 1,
284 radv_optimize_nir(nir
);
290 radv_alloc_shader_memory(struct radv_device
*device
,
291 struct radv_shader_variant
*shader
)
293 mtx_lock(&device
->shader_slab_mutex
);
294 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
296 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
297 if (s
->bo_offset
- offset
>= shader
->code_size
) {
298 shader
->bo
= slab
->bo
;
299 shader
->bo_offset
= offset
;
300 list_addtail(&shader
->slab_list
, &s
->slab_list
);
301 mtx_unlock(&device
->shader_slab_mutex
);
302 return slab
->ptr
+ offset
;
304 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
306 if (slab
->size
- offset
>= shader
->code_size
) {
307 shader
->bo
= slab
->bo
;
308 shader
->bo_offset
= offset
;
309 list_addtail(&shader
->slab_list
, &slab
->shaders
);
310 mtx_unlock(&device
->shader_slab_mutex
);
311 return slab
->ptr
+ offset
;
315 mtx_unlock(&device
->shader_slab_mutex
);
316 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
318 slab
->size
= 256 * 1024;
319 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
321 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
322 device
->physical_device
->cpdma_prefetch_writes_memory
?
323 0 : RADEON_FLAG_READ_ONLY
);
324 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
325 list_inithead(&slab
->shaders
);
327 mtx_lock(&device
->shader_slab_mutex
);
328 list_add(&slab
->slabs
, &device
->shader_slabs
);
330 shader
->bo
= slab
->bo
;
331 shader
->bo_offset
= 0;
332 list_add(&shader
->slab_list
, &slab
->shaders
);
333 mtx_unlock(&device
->shader_slab_mutex
);
338 radv_destroy_shader_slabs(struct radv_device
*device
)
340 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
341 device
->ws
->buffer_destroy(slab
->bo
);
344 mtx_destroy(&device
->shader_slab_mutex
);
348 radv_fill_shader_variant(struct radv_device
*device
,
349 struct radv_shader_variant
*variant
,
350 struct ac_shader_binary
*binary
,
351 gl_shader_stage stage
)
353 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
354 unsigned vgpr_comp_cnt
= 0;
356 if (scratch_enabled
&& !device
->llvm_supports_spill
)
357 radv_finishme("shader scratch support only available with LLVM 4.0");
359 variant
->code_size
= binary
->code_size
;
360 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
361 S_00B12C_SCRATCH_EN(scratch_enabled
);
363 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
364 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
365 S_00B848_DX10_CLAMP(1) |
366 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
369 case MESA_SHADER_TESS_EVAL
:
371 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
373 case MESA_SHADER_TESS_CTRL
:
374 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
375 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
377 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
379 case MESA_SHADER_VERTEX
:
380 case MESA_SHADER_GEOMETRY
:
381 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
383 case MESA_SHADER_FRAGMENT
:
385 case MESA_SHADER_COMPUTE
: {
386 struct ac_shader_info
*info
= &variant
->info
.info
;
388 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
389 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
390 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
391 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
392 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
393 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
394 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
398 unreachable("unsupported shader type");
402 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
403 stage
== MESA_SHADER_GEOMETRY
) {
404 struct ac_shader_info
*info
= &variant
->info
.info
;
405 unsigned es_type
= variant
->info
.gs
.es_type
;
406 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
408 if (es_type
== MESA_SHADER_VERTEX
) {
409 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
410 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
411 es_vgpr_comp_cnt
= 3;
413 unreachable("invalid shader ES type");
416 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
417 * VGPR[0:4] are always loaded.
419 if (info
->uses_invocation_id
)
420 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
421 else if (info
->uses_prim_id
)
422 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
423 else if (variant
->info
.gs
.vertices_in
>= 3)
424 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
426 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
428 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
429 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
430 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
431 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
432 stage
== MESA_SHADER_TESS_CTRL
)
433 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
435 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
437 void *ptr
= radv_alloc_shader_memory(device
, variant
);
438 memcpy(ptr
, binary
->code
, binary
->code_size
);
441 static struct radv_shader_variant
*
442 shader_variant_create(struct radv_device
*device
,
443 struct radv_shader_module
*module
,
444 struct nir_shader
* const *shaders
,
446 gl_shader_stage stage
,
447 struct ac_nir_compiler_options
*options
,
450 unsigned *code_size_out
)
452 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
453 bool dump_shaders
= radv_can_dump_shader(device
, module
);
454 enum ac_target_machine_options tm_options
= 0;
455 struct radv_shader_variant
*variant
;
456 struct ac_shader_binary binary
;
457 LLVMTargetMachineRef tm
;
459 variant
= calloc(1, sizeof(struct radv_shader_variant
));
463 options
->family
= chip_family
;
464 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
465 options
->dump_preoptir
= radv_can_dump_shader(device
, module
) &&
466 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
468 if (options
->supports_spill
)
469 tm_options
|= AC_TM_SUPPORTS_SPILL
;
470 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
471 tm_options
|= AC_TM_SISCHED
;
472 tm
= ac_create_target_machine(chip_family
, tm_options
);
474 if (gs_copy_shader
) {
475 assert(shader_count
== 1);
476 radv_compile_gs_copy_shader(tm
, *shaders
, &binary
,
477 &variant
->config
, &variant
->info
,
478 options
, dump_shaders
);
480 radv_compile_nir_shader(tm
, &binary
, &variant
->config
,
481 &variant
->info
, shaders
, shader_count
,
482 options
, dump_shaders
);
485 LLVMDisposeTargetMachine(tm
);
487 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
490 *code_out
= binary
.code
;
491 *code_size_out
= binary
.code_size
;
496 free(binary
.global_symbol_offsets
);
498 variant
->ref_count
= 1;
500 if (device
->keep_shader_info
) {
501 variant
->disasm_string
= binary
.disasm_string
;
502 if (!gs_copy_shader
&& !module
->nir
) {
503 variant
->nir
= *shaders
;
504 variant
->spirv
= (uint32_t *)module
->data
;
505 variant
->spirv_size
= module
->size
;
508 free(binary
.disasm_string
);
514 struct radv_shader_variant
*
515 radv_shader_variant_create(struct radv_device
*device
,
516 struct radv_shader_module
*module
,
517 struct nir_shader
*const *shaders
,
519 struct radv_pipeline_layout
*layout
,
520 const struct ac_shader_variant_key
*key
,
522 unsigned *code_size_out
)
524 struct ac_nir_compiler_options options
= {0};
526 options
.layout
= layout
;
530 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
531 options
.supports_spill
= device
->llvm_supports_spill
;
533 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
534 &options
, false, code_out
, code_size_out
);
537 struct radv_shader_variant
*
538 radv_create_gs_copy_shader(struct radv_device
*device
,
539 struct nir_shader
*shader
,
541 unsigned *code_size_out
,
544 struct ac_nir_compiler_options options
= {0};
546 options
.key
.has_multiview_view_index
= multiview
;
548 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
549 &options
, true, code_out
, code_size_out
);
553 radv_shader_variant_destroy(struct radv_device
*device
,
554 struct radv_shader_variant
*variant
)
556 if (!p_atomic_dec_zero(&variant
->ref_count
))
559 mtx_lock(&device
->shader_slab_mutex
);
560 list_del(&variant
->slab_list
);
561 mtx_unlock(&device
->shader_slab_mutex
);
563 ralloc_free(variant
->nir
);
564 free(variant
->disasm_string
);
569 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
572 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
573 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
574 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
575 case MESA_SHADER_COMPUTE
: return "Compute Shader";
576 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
577 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
579 return "Unknown shader";
584 get_total_sgprs(struct radv_device
*device
)
586 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
593 generate_shader_stats(struct radv_device
*device
,
594 struct radv_shader_variant
*variant
,
595 gl_shader_stage stage
,
596 struct _mesa_string_buffer
*buf
)
598 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
599 struct ac_shader_config
*conf
;
600 unsigned max_simd_waves
;
601 unsigned lds_per_wave
= 0;
603 switch (device
->physical_device
->rad_info
.family
) {
604 /* These always have 8 waves: */
614 conf
= &variant
->config
;
616 if (stage
== MESA_SHADER_FRAGMENT
) {
617 lds_per_wave
= conf
->lds_size
* lds_increment
+
618 align(variant
->info
.fs
.num_interp
* 48,
623 max_simd_waves
= MIN2(max_simd_waves
, get_total_sgprs(device
) / conf
->num_sgprs
);
626 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
628 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
632 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
634 if (stage
== MESA_SHADER_FRAGMENT
) {
635 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
636 "SPI_PS_INPUT_ADDR = 0x%04x\n"
637 "SPI_PS_INPUT_ENA = 0x%04x\n",
638 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
641 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
644 "Spilled SGPRs: %d\n"
645 "Spilled VGPRs: %d\n"
646 "PrivMem VGPRS: %d\n"
647 "Code Size: %d bytes\n"
649 "Scratch: %d bytes per wave\n"
651 "********************\n\n\n",
652 conf
->num_sgprs
, conf
->num_vgprs
,
653 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
654 variant
->info
.private_mem_vgprs
, variant
->code_size
,
655 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
660 radv_shader_dump_stats(struct radv_device
*device
,
661 struct radv_shader_variant
*variant
,
662 gl_shader_stage stage
,
665 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
667 generate_shader_stats(device
, variant
, stage
, buf
);
669 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
670 fprintf(file
, "%s", buf
->buf
);
672 _mesa_string_buffer_destroy(buf
);
676 radv_GetShaderInfoAMD(VkDevice _device
,
677 VkPipeline _pipeline
,
678 VkShaderStageFlagBits shaderStage
,
679 VkShaderInfoTypeAMD infoType
,
683 RADV_FROM_HANDLE(radv_device
, device
, _device
);
684 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
685 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
686 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
687 struct _mesa_string_buffer
*buf
;
688 VkResult result
= VK_SUCCESS
;
690 /* Spec doesn't indicate what to do if the stage is invalid, so just
691 * return no info for this. */
693 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
696 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
698 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
700 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
701 struct ac_shader_config
*conf
= &variant
->config
;
703 VkShaderStatisticsInfoAMD statistics
= {};
704 statistics
.shaderStageMask
= shaderStage
;
705 statistics
.numPhysicalVgprs
= 256;
706 statistics
.numPhysicalSgprs
= get_total_sgprs(device
);
707 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
709 if (stage
== MESA_SHADER_COMPUTE
) {
710 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
711 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
713 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
714 ceil(workgroup_size
/ statistics
.numPhysicalVgprs
);
716 statistics
.computeWorkGroupSize
[0] = local_size
[0];
717 statistics
.computeWorkGroupSize
[1] = local_size
[1];
718 statistics
.computeWorkGroupSize
[2] = local_size
[2];
720 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
723 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
724 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
725 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
726 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
727 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
729 size_t size
= *pInfoSize
;
730 *pInfoSize
= sizeof(statistics
);
732 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
734 if (size
< *pInfoSize
)
735 result
= VK_INCOMPLETE
;
739 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
740 buf
= _mesa_string_buffer_create(NULL
, 1024);
742 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
743 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
744 generate_shader_stats(device
, variant
, stage
, buf
);
746 /* Need to include the null terminator. */
747 size_t length
= buf
->length
+ 1;
752 size_t size
= *pInfoSize
;
755 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
758 result
= VK_INCOMPLETE
;
761 _mesa_string_buffer_destroy(buf
);
764 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
765 result
= VK_ERROR_FEATURE_NOT_PRESENT
;