2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
63 .lower_pack_snorm_2x16
= true,
64 .lower_pack_snorm_4x8
= true,
65 .lower_pack_unorm_2x16
= true,
66 .lower_pack_unorm_4x8
= true,
67 .lower_unpack_snorm_2x16
= true,
68 .lower_unpack_snorm_4x8
= true,
69 .lower_unpack_unorm_2x16
= true,
70 .lower_unpack_unorm_4x8
= true,
71 .lower_extract_byte
= true,
72 .lower_extract_word
= true,
75 .lower_mul_2x32_64
= true,
76 .max_unroll_iterations
= 32
79 VkResult
radv_CreateShaderModule(
81 const VkShaderModuleCreateInfo
* pCreateInfo
,
82 const VkAllocationCallbacks
* pAllocator
,
83 VkShaderModule
* pShaderModule
)
85 RADV_FROM_HANDLE(radv_device
, device
, _device
);
86 struct radv_shader_module
*module
;
88 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
89 assert(pCreateInfo
->flags
== 0);
91 module
= vk_alloc2(&device
->alloc
, pAllocator
,
92 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
93 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
95 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
98 module
->size
= pCreateInfo
->codeSize
;
99 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
101 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
103 *pShaderModule
= radv_shader_module_to_handle(module
);
108 void radv_DestroyShaderModule(
110 VkShaderModule _module
,
111 const VkAllocationCallbacks
* pAllocator
)
113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
114 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
119 vk_free2(&device
->alloc
, pAllocator
, module
);
123 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
131 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
132 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
134 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
135 NIR_PASS_V(shader
, nir_lower_pack
);
138 /* Only run this pass in the first call to
139 * radv_optimize_nir. Later calls assume that we've
140 * lowered away any copy_deref instructions and we
141 * don't want to introduce any more.
143 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
146 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
147 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
149 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
150 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
152 NIR_PASS(progress
, shader
, nir_copy_prop
);
153 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
154 NIR_PASS(progress
, shader
, nir_opt_dce
);
155 if (nir_opt_trivial_continues(shader
)) {
157 NIR_PASS(progress
, shader
, nir_copy_prop
);
158 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
159 NIR_PASS(progress
, shader
, nir_opt_dce
);
161 NIR_PASS(progress
, shader
, nir_opt_if
);
162 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
163 NIR_PASS(progress
, shader
, nir_opt_cse
);
164 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
165 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
166 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
167 NIR_PASS(progress
, shader
, nir_opt_undef
);
168 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
169 if (shader
->options
->max_unroll_iterations
) {
170 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
172 } while (progress
&& !optimize_conservatively
);
174 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
175 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
179 radv_shader_compile_to_nir(struct radv_device
*device
,
180 struct radv_shader_module
*module
,
181 const char *entrypoint_name
,
182 gl_shader_stage stage
,
183 const VkSpecializationInfo
*spec_info
,
184 const VkPipelineCreateFlags flags
)
187 nir_function
*entry_point
;
189 /* Some things such as our meta clear/blit code will give us a NIR
190 * shader directly. In that case, we just ignore the SPIR-V entirely
191 * and just use the NIR shader */
193 nir
->options
= &nir_options
;
194 nir_validate_shader(nir
, "in internal shader");
196 assert(exec_list_length(&nir
->functions
) == 1);
197 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
198 entry_point
= exec_node_data(nir_function
, node
, node
);
200 uint32_t *spirv
= (uint32_t *) module
->data
;
201 assert(module
->size
% 4 == 0);
203 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
204 radv_print_spirv(spirv
, module
->size
, stderr
);
206 uint32_t num_spec_entries
= 0;
207 struct nir_spirv_specialization
*spec_entries
= NULL
;
208 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
209 num_spec_entries
= spec_info
->mapEntryCount
;
210 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
211 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
212 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
213 const void *data
= spec_info
->pData
+ entry
.offset
;
214 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
216 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
217 if (spec_info
->dataSize
== 8)
218 spec_entries
[i
].data64
= *(const uint64_t *)data
;
220 spec_entries
[i
].data32
= *(const uint32_t *)data
;
223 const struct spirv_to_nir_options spirv_options
= {
224 .lower_ubo_ssbo_access_to_offsets
= true,
226 .descriptor_array_dynamic_indexing
= true,
227 .device_group
= true,
228 .draw_parameters
= true,
231 .geometry_streams
= true,
232 .image_read_without_format
= true,
233 .image_write_without_format
= true,
237 .physical_storage_buffer_address
= true,
238 .runtime_descriptor_array
= true,
239 .shader_viewport_index_layer
= true,
240 .stencil_export
= true,
241 .storage_16bit
= true,
242 .storage_image_ms
= true,
243 .subgroup_arithmetic
= true,
244 .subgroup_ballot
= true,
245 .subgroup_basic
= true,
246 .subgroup_quad
= true,
247 .subgroup_shuffle
= true,
248 .subgroup_vote
= true,
249 .tessellation
= true,
250 .transform_feedback
= true,
251 .trinary_minmax
= true,
252 .variable_pointers
= true,
253 .storage_8bit
= true,
256 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
257 .ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
258 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
259 .push_const_ptr_type
= glsl_uint_type(),
260 .shared_ptr_type
= glsl_uint_type(),
262 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
263 spec_entries
, num_spec_entries
,
264 stage
, entrypoint_name
,
265 &spirv_options
, &nir_options
);
266 nir
= entry_point
->shader
;
267 assert(nir
->info
.stage
== stage
);
268 nir_validate_shader(nir
, "after spirv_to_nir");
272 /* We have to lower away local constant initializers right before we
273 * inline functions. That way they get properly initialized at the top
274 * of the function and not at the top of its caller.
276 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
277 NIR_PASS_V(nir
, nir_lower_returns
);
278 NIR_PASS_V(nir
, nir_inline_functions
);
279 NIR_PASS_V(nir
, nir_opt_deref
);
281 /* Pick off the single entrypoint that we want */
282 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
283 if (func
!= entry_point
)
284 exec_node_remove(&func
->node
);
286 assert(exec_list_length(&nir
->functions
) == 1);
287 entry_point
->name
= ralloc_strdup(entry_point
, "main");
289 /* Make sure we lower constant initializers on output variables so that
290 * nir_remove_dead_variables below sees the corresponding stores
292 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
294 /* Now that we've deleted all but the main function, we can go ahead and
295 * lower the rest of the constant initializers.
297 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
299 /* Split member structs. We do this before lower_io_to_temporaries so that
300 * it doesn't lower system values to temporaries by accident.
302 NIR_PASS_V(nir
, nir_split_var_copies
);
303 NIR_PASS_V(nir
, nir_split_per_member_structs
);
305 NIR_PASS_V(nir
, nir_remove_dead_variables
,
306 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
308 NIR_PASS_V(nir
, nir_lower_system_values
);
309 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
312 /* Vulkan uses the separate-shader linking model */
313 nir
->info
.separate_shader
= true;
315 nir_shader_gather_info(nir
, entry_point
->impl
);
317 static const nir_lower_tex_options tex_options
= {
319 .lower_tg4_offsets
= true,
322 nir_lower_tex(nir
, &tex_options
);
324 nir_lower_vars_to_ssa(nir
);
326 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
327 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
328 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
329 nir_shader_get_entrypoint(nir
), true, true);
330 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
331 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
332 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
333 nir_shader_get_entrypoint(nir
), true, false);
336 nir_split_var_copies(nir
);
338 nir_lower_global_vars_to_local(nir
);
339 nir_remove_dead_variables(nir
, nir_var_function_temp
);
340 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
342 .ballot_bit_size
= 64,
343 .lower_to_scalar
= 1,
344 .lower_subgroup_masks
= 1,
346 .lower_shuffle_to_32bit
= 1,
347 .lower_vote_eq_to_ballot
= 1,
350 nir_lower_load_const_to_scalar(nir
);
352 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
353 radv_optimize_nir(nir
, false, true);
355 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
356 * to remove any copies introduced by nir_opt_find_array_copies().
358 nir_lower_var_copies(nir
);
360 /* Indirect lowering must be called after the radv_optimize_nir() loop
361 * has been called at least once. Otherwise indirect lowering can
362 * bloat the instruction count of the loop and cause it to be
363 * considered too large for unrolling.
365 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
366 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
372 radv_alloc_shader_memory(struct radv_device
*device
,
373 struct radv_shader_variant
*shader
)
375 mtx_lock(&device
->shader_slab_mutex
);
376 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
378 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
379 if (s
->bo_offset
- offset
>= shader
->code_size
) {
380 shader
->bo
= slab
->bo
;
381 shader
->bo_offset
= offset
;
382 list_addtail(&shader
->slab_list
, &s
->slab_list
);
383 mtx_unlock(&device
->shader_slab_mutex
);
384 return slab
->ptr
+ offset
;
386 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
388 if (slab
->size
- offset
>= shader
->code_size
) {
389 shader
->bo
= slab
->bo
;
390 shader
->bo_offset
= offset
;
391 list_addtail(&shader
->slab_list
, &slab
->shaders
);
392 mtx_unlock(&device
->shader_slab_mutex
);
393 return slab
->ptr
+ offset
;
397 mtx_unlock(&device
->shader_slab_mutex
);
398 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
400 slab
->size
= 256 * 1024;
401 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
403 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
404 (device
->physical_device
->cpdma_prefetch_writes_memory
?
405 0 : RADEON_FLAG_READ_ONLY
),
406 RADV_BO_PRIORITY_SHADER
);
407 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
408 list_inithead(&slab
->shaders
);
410 mtx_lock(&device
->shader_slab_mutex
);
411 list_add(&slab
->slabs
, &device
->shader_slabs
);
413 shader
->bo
= slab
->bo
;
414 shader
->bo_offset
= 0;
415 list_add(&shader
->slab_list
, &slab
->shaders
);
416 mtx_unlock(&device
->shader_slab_mutex
);
421 radv_destroy_shader_slabs(struct radv_device
*device
)
423 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
424 device
->ws
->buffer_destroy(slab
->bo
);
427 mtx_destroy(&device
->shader_slab_mutex
);
430 /* For the UMR disassembler. */
431 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
432 #define DEBUGGER_NUM_MARKERS 5
435 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
437 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
441 radv_fill_shader_variant(struct radv_device
*device
,
442 struct radv_shader_variant
*variant
,
443 struct ac_shader_binary
*binary
,
444 gl_shader_stage stage
)
446 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
447 struct radv_shader_info
*info
= &variant
->info
.info
;
448 unsigned vgpr_comp_cnt
= 0;
450 variant
->code_size
= radv_get_shader_binary_size(binary
);
451 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
452 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
453 S_00B12C_SCRATCH_EN(scratch_enabled
) |
454 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
455 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
456 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
457 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
458 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
460 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
461 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
462 S_00B848_DX10_CLAMP(1) |
463 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
466 case MESA_SHADER_TESS_EVAL
:
468 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
470 case MESA_SHADER_TESS_CTRL
:
471 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
472 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
474 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
477 case MESA_SHADER_VERTEX
:
478 case MESA_SHADER_GEOMETRY
:
479 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
481 case MESA_SHADER_FRAGMENT
:
483 case MESA_SHADER_COMPUTE
:
485 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
486 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
487 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
488 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
489 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
490 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
491 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
494 unreachable("unsupported shader type");
498 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
499 stage
== MESA_SHADER_GEOMETRY
) {
500 unsigned es_type
= variant
->info
.gs
.es_type
;
501 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
503 if (es_type
== MESA_SHADER_VERTEX
) {
504 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
505 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
506 es_vgpr_comp_cnt
= 3;
508 unreachable("invalid shader ES type");
511 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
512 * VGPR[0:4] are always loaded.
514 if (info
->uses_invocation_id
) {
515 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
516 } else if (info
->uses_prim_id
) {
517 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
518 } else if (variant
->info
.gs
.vertices_in
>= 3) {
519 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
521 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
524 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
525 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
526 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
527 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
528 stage
== MESA_SHADER_TESS_CTRL
) {
529 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
531 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
534 void *ptr
= radv_alloc_shader_memory(device
, variant
);
535 memcpy(ptr
, binary
->code
, binary
->code_size
);
537 /* Add end-of-code markers for the UMR disassembler. */
538 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
539 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
540 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
544 static void radv_init_llvm_target()
546 LLVMInitializeAMDGPUTargetInfo();
547 LLVMInitializeAMDGPUTarget();
548 LLVMInitializeAMDGPUTargetMC();
549 LLVMInitializeAMDGPUAsmPrinter();
551 /* For inline assembly. */
552 LLVMInitializeAMDGPUAsmParser();
554 /* Workaround for bug in llvm 4.0 that causes image intrinsics
556 * https://reviews.llvm.org/D26348
558 * Workaround for bug in llvm that causes the GPU to hang in presence
559 * of nested loops because there is an exec mask issue. The proper
560 * solution is to fix LLVM but this might require a bunch of work.
561 * https://bugs.llvm.org/show_bug.cgi?id=37744
563 * "mesa" is the prefix for error messages.
565 if (HAVE_LLVM
>= 0x0800) {
566 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
567 LLVMParseCommandLineOptions(2, argv
, NULL
);
570 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
571 "-amdgpu-skip-threshold=1" };
572 LLVMParseCommandLineOptions(3, argv
, NULL
);
576 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
578 static void radv_init_llvm_once(void)
580 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
583 static struct radv_shader_variant
*
584 shader_variant_create(struct radv_device
*device
,
585 struct radv_shader_module
*module
,
586 struct nir_shader
* const *shaders
,
588 gl_shader_stage stage
,
589 struct radv_nir_compiler_options
*options
,
592 unsigned *code_size_out
)
594 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
595 enum ac_target_machine_options tm_options
= 0;
596 struct radv_shader_variant
*variant
;
597 struct ac_shader_binary binary
;
598 struct ac_llvm_compiler ac_llvm
;
599 bool thread_compiler
;
600 variant
= calloc(1, sizeof(struct radv_shader_variant
));
604 options
->family
= chip_family
;
605 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
606 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
607 options
->dump_preoptir
= options
->dump_shader
&&
608 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
609 options
->record_llvm_ir
= device
->keep_shader_info
;
610 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
611 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
612 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
614 if (options
->supports_spill
)
615 tm_options
|= AC_TM_SUPPORTS_SPILL
;
616 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
617 tm_options
|= AC_TM_SISCHED
;
618 if (options
->check_ir
)
619 tm_options
|= AC_TM_CHECK_IR
;
621 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
622 radv_init_llvm_once();
623 radv_init_llvm_compiler(&ac_llvm
,
625 chip_family
, tm_options
);
626 if (gs_copy_shader
) {
627 assert(shader_count
== 1);
628 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
629 &variant
->config
, &variant
->info
,
632 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
633 &variant
->info
, shaders
, shader_count
,
637 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
639 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
642 *code_out
= binary
.code
;
643 *code_size_out
= binary
.code_size
;
648 free(binary
.global_symbol_offsets
);
650 variant
->ref_count
= 1;
652 if (device
->keep_shader_info
) {
653 variant
->disasm_string
= binary
.disasm_string
;
654 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
655 if (!gs_copy_shader
&& !module
->nir
) {
656 variant
->nir
= *shaders
;
657 variant
->spirv
= (uint32_t *)module
->data
;
658 variant
->spirv_size
= module
->size
;
661 free(binary
.disasm_string
);
667 struct radv_shader_variant
*
668 radv_shader_variant_create(struct radv_device
*device
,
669 struct radv_shader_module
*module
,
670 struct nir_shader
*const *shaders
,
672 struct radv_pipeline_layout
*layout
,
673 const struct radv_shader_variant_key
*key
,
675 unsigned *code_size_out
)
677 struct radv_nir_compiler_options options
= {0};
679 options
.layout
= layout
;
683 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
684 options
.supports_spill
= true;
686 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
687 &options
, false, code_out
, code_size_out
);
690 struct radv_shader_variant
*
691 radv_create_gs_copy_shader(struct radv_device
*device
,
692 struct nir_shader
*shader
,
694 unsigned *code_size_out
,
697 struct radv_nir_compiler_options options
= {0};
699 options
.key
.has_multiview_view_index
= multiview
;
701 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
702 &options
, true, code_out
, code_size_out
);
706 radv_shader_variant_destroy(struct radv_device
*device
,
707 struct radv_shader_variant
*variant
)
709 if (!p_atomic_dec_zero(&variant
->ref_count
))
712 mtx_lock(&device
->shader_slab_mutex
);
713 list_del(&variant
->slab_list
);
714 mtx_unlock(&device
->shader_slab_mutex
);
716 ralloc_free(variant
->nir
);
717 free(variant
->disasm_string
);
718 free(variant
->llvm_ir_string
);
723 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
726 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
727 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
728 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
729 case MESA_SHADER_COMPUTE
: return "Compute Shader";
730 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
731 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
733 return "Unknown shader";
738 generate_shader_stats(struct radv_device
*device
,
739 struct radv_shader_variant
*variant
,
740 gl_shader_stage stage
,
741 struct _mesa_string_buffer
*buf
)
743 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
744 unsigned lds_increment
= chip_class
>= CIK
? 512 : 256;
745 struct ac_shader_config
*conf
;
746 unsigned max_simd_waves
;
747 unsigned lds_per_wave
= 0;
749 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
751 conf
= &variant
->config
;
753 if (stage
== MESA_SHADER_FRAGMENT
) {
754 lds_per_wave
= conf
->lds_size
* lds_increment
+
755 align(variant
->info
.fs
.num_interp
* 48,
757 } else if (stage
== MESA_SHADER_COMPUTE
) {
758 unsigned max_workgroup_size
=
759 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
760 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
761 DIV_ROUND_UP(max_workgroup_size
, 64);
767 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
772 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
774 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
778 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
780 if (stage
== MESA_SHADER_FRAGMENT
) {
781 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
782 "SPI_PS_INPUT_ADDR = 0x%04x\n"
783 "SPI_PS_INPUT_ENA = 0x%04x\n",
784 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
787 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
790 "Spilled SGPRs: %d\n"
791 "Spilled VGPRs: %d\n"
792 "PrivMem VGPRS: %d\n"
793 "Code Size: %d bytes\n"
795 "Scratch: %d bytes per wave\n"
797 "********************\n\n\n",
798 conf
->num_sgprs
, conf
->num_vgprs
,
799 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
800 variant
->info
.private_mem_vgprs
, variant
->code_size
,
801 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
806 radv_shader_dump_stats(struct radv_device
*device
,
807 struct radv_shader_variant
*variant
,
808 gl_shader_stage stage
,
811 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
813 generate_shader_stats(device
, variant
, stage
, buf
);
815 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
816 fprintf(file
, "%s", buf
->buf
);
818 _mesa_string_buffer_destroy(buf
);
822 radv_GetShaderInfoAMD(VkDevice _device
,
823 VkPipeline _pipeline
,
824 VkShaderStageFlagBits shaderStage
,
825 VkShaderInfoTypeAMD infoType
,
829 RADV_FROM_HANDLE(radv_device
, device
, _device
);
830 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
831 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
832 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
833 struct _mesa_string_buffer
*buf
;
834 VkResult result
= VK_SUCCESS
;
836 /* Spec doesn't indicate what to do if the stage is invalid, so just
837 * return no info for this. */
839 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
842 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
844 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
846 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
847 struct ac_shader_config
*conf
= &variant
->config
;
849 VkShaderStatisticsInfoAMD statistics
= {};
850 statistics
.shaderStageMask
= shaderStage
;
851 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
852 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
853 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
855 if (stage
== MESA_SHADER_COMPUTE
) {
856 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
857 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
859 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
860 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
862 statistics
.computeWorkGroupSize
[0] = local_size
[0];
863 statistics
.computeWorkGroupSize
[1] = local_size
[1];
864 statistics
.computeWorkGroupSize
[2] = local_size
[2];
866 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
869 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
870 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
871 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
872 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
873 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
875 size_t size
= *pInfoSize
;
876 *pInfoSize
= sizeof(statistics
);
878 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
880 if (size
< *pInfoSize
)
881 result
= VK_INCOMPLETE
;
885 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
886 buf
= _mesa_string_buffer_create(NULL
, 1024);
888 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
889 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
890 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
891 generate_shader_stats(device
, variant
, stage
, buf
);
893 /* Need to include the null terminator. */
894 size_t length
= buf
->length
+ 1;
899 size_t size
= *pInfoSize
;
902 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
905 result
= VK_INCOMPLETE
;
908 _mesa_string_buffer_destroy(buf
);
911 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
912 result
= VK_ERROR_FEATURE_NOT_PRESENT
;