2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
63 .lower_pack_snorm_2x16
= true,
64 .lower_pack_snorm_4x8
= true,
65 .lower_pack_unorm_2x16
= true,
66 .lower_pack_unorm_4x8
= true,
67 .lower_unpack_snorm_2x16
= true,
68 .lower_unpack_snorm_4x8
= true,
69 .lower_unpack_unorm_2x16
= true,
70 .lower_unpack_unorm_4x8
= true,
71 .lower_extract_byte
= true,
72 .lower_extract_word
= true,
75 .lower_mul_2x32_64
= true,
76 .max_unroll_iterations
= 32
79 VkResult
radv_CreateShaderModule(
81 const VkShaderModuleCreateInfo
* pCreateInfo
,
82 const VkAllocationCallbacks
* pAllocator
,
83 VkShaderModule
* pShaderModule
)
85 RADV_FROM_HANDLE(radv_device
, device
, _device
);
86 struct radv_shader_module
*module
;
88 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
89 assert(pCreateInfo
->flags
== 0);
91 module
= vk_alloc2(&device
->alloc
, pAllocator
,
92 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
93 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
95 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
98 module
->size
= pCreateInfo
->codeSize
;
99 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
101 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
103 *pShaderModule
= radv_shader_module_to_handle(module
);
108 void radv_DestroyShaderModule(
110 VkShaderModule _module
,
111 const VkAllocationCallbacks
* pAllocator
)
113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
114 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
119 vk_free2(&device
->alloc
, pAllocator
, module
);
123 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
127 unsigned lower_flrp
=
128 (shader
->options
->lower_flrp16
? 16 : 0) |
129 (shader
->options
->lower_flrp32
? 32 : 0) |
130 (shader
->options
->lower_flrp64
? 64 : 0);
135 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
136 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
138 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
139 NIR_PASS_V(shader
, nir_lower_pack
);
142 /* Only run this pass in the first call to
143 * radv_optimize_nir. Later calls assume that we've
144 * lowered away any copy_deref instructions and we
145 * don't want to introduce any more.
147 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
150 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
151 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
153 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
);
154 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
156 NIR_PASS(progress
, shader
, nir_copy_prop
);
157 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
158 NIR_PASS(progress
, shader
, nir_opt_dce
);
159 if (nir_opt_trivial_continues(shader
)) {
161 NIR_PASS(progress
, shader
, nir_copy_prop
);
162 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
163 NIR_PASS(progress
, shader
, nir_opt_dce
);
165 NIR_PASS(progress
, shader
, nir_opt_if
, true);
166 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
167 NIR_PASS(progress
, shader
, nir_opt_cse
);
168 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
169 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
170 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
172 if (lower_flrp
!= 0) {
173 bool lower_flrp_progress
= false;
174 NIR_PASS(lower_flrp_progress
,
178 false /* always_precise */,
179 shader
->options
->lower_ffma
);
180 if (lower_flrp_progress
) {
181 NIR_PASS(progress
, shader
,
182 nir_opt_constant_folding
);
186 /* Nothing should rematerialize any flrps, so we only
187 * need to do this lowering once.
192 NIR_PASS(progress
, shader
, nir_opt_undef
);
193 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
194 if (shader
->options
->max_unroll_iterations
) {
195 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
197 } while (progress
&& !optimize_conservatively
);
199 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
200 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
204 radv_shader_compile_to_nir(struct radv_device
*device
,
205 struct radv_shader_module
*module
,
206 const char *entrypoint_name
,
207 gl_shader_stage stage
,
208 const VkSpecializationInfo
*spec_info
,
209 const VkPipelineCreateFlags flags
,
210 const struct radv_pipeline_layout
*layout
)
213 nir_function
*entry_point
;
215 /* Some things such as our meta clear/blit code will give us a NIR
216 * shader directly. In that case, we just ignore the SPIR-V entirely
217 * and just use the NIR shader */
219 nir
->options
= &nir_options
;
220 nir_validate_shader(nir
, "in internal shader");
222 assert(exec_list_length(&nir
->functions
) == 1);
223 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
224 entry_point
= exec_node_data(nir_function
, node
, node
);
226 uint32_t *spirv
= (uint32_t *) module
->data
;
227 assert(module
->size
% 4 == 0);
229 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
230 radv_print_spirv(spirv
, module
->size
, stderr
);
232 uint32_t num_spec_entries
= 0;
233 struct nir_spirv_specialization
*spec_entries
= NULL
;
234 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
235 num_spec_entries
= spec_info
->mapEntryCount
;
236 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
237 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
238 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
239 const void *data
= spec_info
->pData
+ entry
.offset
;
240 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
242 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
243 if (spec_info
->dataSize
== 8)
244 spec_entries
[i
].data64
= *(const uint64_t *)data
;
246 spec_entries
[i
].data32
= *(const uint32_t *)data
;
249 const struct spirv_to_nir_options spirv_options
= {
250 .lower_ubo_ssbo_access_to_offsets
= true,
252 .derivative_group
= true,
253 .descriptor_array_dynamic_indexing
= true,
254 .descriptor_array_non_uniform_indexing
= true,
255 .descriptor_indexing
= true,
256 .device_group
= true,
257 .draw_parameters
= true,
261 .geometry_streams
= true,
262 .image_read_without_format
= true,
263 .image_write_without_format
= true,
267 .int64_atomics
= true,
269 .physical_storage_buffer_address
= true,
270 .runtime_descriptor_array
= true,
271 .shader_viewport_index_layer
= true,
272 .stencil_export
= true,
273 .storage_8bit
= true,
274 .storage_16bit
= true,
275 .storage_image_ms
= true,
276 .subgroup_arithmetic
= true,
277 .subgroup_ballot
= true,
278 .subgroup_basic
= true,
279 .subgroup_quad
= true,
280 .subgroup_shuffle
= true,
281 .subgroup_vote
= true,
282 .tessellation
= true,
283 .transform_feedback
= true,
284 .trinary_minmax
= true,
285 .variable_pointers
= true,
287 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
288 .ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
289 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
290 .push_const_ptr_type
= glsl_uint_type(),
291 .shared_ptr_type
= glsl_uint_type(),
293 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
294 spec_entries
, num_spec_entries
,
295 stage
, entrypoint_name
,
296 &spirv_options
, &nir_options
);
297 nir
= entry_point
->shader
;
298 assert(nir
->info
.stage
== stage
);
299 nir_validate_shader(nir
, "after spirv_to_nir");
303 /* We have to lower away local constant initializers right before we
304 * inline functions. That way they get properly initialized at the top
305 * of the function and not at the top of its caller.
307 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
308 NIR_PASS_V(nir
, nir_lower_returns
);
309 NIR_PASS_V(nir
, nir_inline_functions
);
310 NIR_PASS_V(nir
, nir_opt_deref
);
312 /* Pick off the single entrypoint that we want */
313 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
314 if (func
!= entry_point
)
315 exec_node_remove(&func
->node
);
317 assert(exec_list_length(&nir
->functions
) == 1);
318 entry_point
->name
= ralloc_strdup(entry_point
, "main");
320 /* Make sure we lower constant initializers on output variables so that
321 * nir_remove_dead_variables below sees the corresponding stores
323 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
325 /* Now that we've deleted all but the main function, we can go ahead and
326 * lower the rest of the constant initializers.
328 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
330 /* Split member structs. We do this before lower_io_to_temporaries so that
331 * it doesn't lower system values to temporaries by accident.
333 NIR_PASS_V(nir
, nir_split_var_copies
);
334 NIR_PASS_V(nir
, nir_split_per_member_structs
);
336 NIR_PASS_V(nir
, nir_remove_dead_variables
,
337 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
339 NIR_PASS_V(nir
, nir_lower_system_values
);
340 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
341 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
344 /* Vulkan uses the separate-shader linking model */
345 nir
->info
.separate_shader
= true;
347 nir_shader_gather_info(nir
, entry_point
->impl
);
349 static const nir_lower_tex_options tex_options
= {
351 .lower_tg4_offsets
= true,
354 nir_lower_tex(nir
, &tex_options
);
356 nir_lower_vars_to_ssa(nir
);
358 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
359 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
360 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
361 nir_shader_get_entrypoint(nir
), true, true);
362 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
363 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
364 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
365 nir_shader_get_entrypoint(nir
), true, false);
368 nir_split_var_copies(nir
);
370 nir_lower_global_vars_to_local(nir
);
371 nir_remove_dead_variables(nir
, nir_var_function_temp
);
372 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
374 .ballot_bit_size
= 64,
375 .lower_to_scalar
= 1,
376 .lower_subgroup_masks
= 1,
378 .lower_shuffle_to_32bit
= 1,
379 .lower_vote_eq_to_ballot
= 1,
382 nir_lower_load_const_to_scalar(nir
);
384 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
385 radv_optimize_nir(nir
, false, true);
387 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
388 * to remove any copies introduced by nir_opt_find_array_copies().
390 nir_lower_var_copies(nir
);
392 /* Indirect lowering must be called after the radv_optimize_nir() loop
393 * has been called at least once. Otherwise indirect lowering can
394 * bloat the instruction count of the loop and cause it to be
395 * considered too large for unrolling.
397 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
398 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
404 radv_alloc_shader_memory(struct radv_device
*device
,
405 struct radv_shader_variant
*shader
)
407 mtx_lock(&device
->shader_slab_mutex
);
408 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
410 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
411 if (s
->bo_offset
- offset
>= shader
->code_size
) {
412 shader
->bo
= slab
->bo
;
413 shader
->bo_offset
= offset
;
414 list_addtail(&shader
->slab_list
, &s
->slab_list
);
415 mtx_unlock(&device
->shader_slab_mutex
);
416 return slab
->ptr
+ offset
;
418 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
420 if (slab
->size
- offset
>= shader
->code_size
) {
421 shader
->bo
= slab
->bo
;
422 shader
->bo_offset
= offset
;
423 list_addtail(&shader
->slab_list
, &slab
->shaders
);
424 mtx_unlock(&device
->shader_slab_mutex
);
425 return slab
->ptr
+ offset
;
429 mtx_unlock(&device
->shader_slab_mutex
);
430 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
432 slab
->size
= 256 * 1024;
433 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
435 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
436 (device
->physical_device
->cpdma_prefetch_writes_memory
?
437 0 : RADEON_FLAG_READ_ONLY
),
438 RADV_BO_PRIORITY_SHADER
);
439 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
440 list_inithead(&slab
->shaders
);
442 mtx_lock(&device
->shader_slab_mutex
);
443 list_add(&slab
->slabs
, &device
->shader_slabs
);
445 shader
->bo
= slab
->bo
;
446 shader
->bo_offset
= 0;
447 list_add(&shader
->slab_list
, &slab
->shaders
);
448 mtx_unlock(&device
->shader_slab_mutex
);
453 radv_destroy_shader_slabs(struct radv_device
*device
)
455 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
456 device
->ws
->buffer_destroy(slab
->bo
);
459 mtx_destroy(&device
->shader_slab_mutex
);
462 /* For the UMR disassembler. */
463 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
464 #define DEBUGGER_NUM_MARKERS 5
467 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
469 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
473 radv_fill_shader_variant(struct radv_device
*device
,
474 struct radv_shader_variant
*variant
,
475 struct ac_shader_binary
*binary
,
476 gl_shader_stage stage
)
478 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
479 struct radv_shader_info
*info
= &variant
->info
.info
;
480 unsigned vgpr_comp_cnt
= 0;
482 variant
->code_size
= radv_get_shader_binary_size(binary
);
483 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
484 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
485 S_00B12C_SCRATCH_EN(scratch_enabled
) |
486 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
487 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
488 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
489 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
490 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
492 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
493 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
494 S_00B848_DX10_CLAMP(1) |
495 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
498 case MESA_SHADER_TESS_EVAL
:
500 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
502 case MESA_SHADER_TESS_CTRL
:
503 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
504 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
506 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
509 case MESA_SHADER_VERTEX
:
510 case MESA_SHADER_GEOMETRY
:
511 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
513 case MESA_SHADER_FRAGMENT
:
515 case MESA_SHADER_COMPUTE
:
517 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
518 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
519 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
520 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
521 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
522 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
523 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
526 unreachable("unsupported shader type");
530 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
531 stage
== MESA_SHADER_GEOMETRY
) {
532 unsigned es_type
= variant
->info
.gs
.es_type
;
533 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
535 if (es_type
== MESA_SHADER_VERTEX
) {
536 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
537 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
538 es_vgpr_comp_cnt
= 3;
540 unreachable("invalid shader ES type");
543 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
544 * VGPR[0:4] are always loaded.
546 if (info
->uses_invocation_id
) {
547 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
548 } else if (info
->uses_prim_id
) {
549 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
550 } else if (variant
->info
.gs
.vertices_in
>= 3) {
551 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
553 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
556 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
557 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
558 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
559 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
560 stage
== MESA_SHADER_TESS_CTRL
) {
561 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
563 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
566 void *ptr
= radv_alloc_shader_memory(device
, variant
);
567 memcpy(ptr
, binary
->code
, binary
->code_size
);
569 /* Add end-of-code markers for the UMR disassembler. */
570 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
571 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
572 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
576 static void radv_init_llvm_target()
578 LLVMInitializeAMDGPUTargetInfo();
579 LLVMInitializeAMDGPUTarget();
580 LLVMInitializeAMDGPUTargetMC();
581 LLVMInitializeAMDGPUAsmPrinter();
583 /* For inline assembly. */
584 LLVMInitializeAMDGPUAsmParser();
586 /* Workaround for bug in llvm 4.0 that causes image intrinsics
588 * https://reviews.llvm.org/D26348
590 * Workaround for bug in llvm that causes the GPU to hang in presence
591 * of nested loops because there is an exec mask issue. The proper
592 * solution is to fix LLVM but this might require a bunch of work.
593 * https://bugs.llvm.org/show_bug.cgi?id=37744
595 * "mesa" is the prefix for error messages.
597 if (HAVE_LLVM
>= 0x0800) {
598 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
599 LLVMParseCommandLineOptions(2, argv
, NULL
);
602 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
603 "-amdgpu-skip-threshold=1" };
604 LLVMParseCommandLineOptions(3, argv
, NULL
);
608 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
610 static void radv_init_llvm_once(void)
612 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
615 static struct radv_shader_variant
*
616 shader_variant_create(struct radv_device
*device
,
617 struct radv_shader_module
*module
,
618 struct nir_shader
* const *shaders
,
620 gl_shader_stage stage
,
621 struct radv_nir_compiler_options
*options
,
624 unsigned *code_size_out
)
626 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
627 enum ac_target_machine_options tm_options
= 0;
628 struct radv_shader_variant
*variant
;
629 struct ac_shader_binary binary
;
630 struct ac_llvm_compiler ac_llvm
;
631 bool thread_compiler
;
632 variant
= calloc(1, sizeof(struct radv_shader_variant
));
636 options
->family
= chip_family
;
637 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
638 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
639 options
->dump_preoptir
= options
->dump_shader
&&
640 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
641 options
->record_llvm_ir
= device
->keep_shader_info
;
642 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
643 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
644 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
646 if (options
->supports_spill
)
647 tm_options
|= AC_TM_SUPPORTS_SPILL
;
648 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
649 tm_options
|= AC_TM_SISCHED
;
650 if (options
->check_ir
)
651 tm_options
|= AC_TM_CHECK_IR
;
652 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
653 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
655 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
656 radv_init_llvm_once();
657 radv_init_llvm_compiler(&ac_llvm
,
659 chip_family
, tm_options
);
660 if (gs_copy_shader
) {
661 assert(shader_count
== 1);
662 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
663 &variant
->config
, &variant
->info
,
666 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
667 &variant
->info
, shaders
, shader_count
,
671 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
673 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
676 *code_out
= binary
.code
;
677 *code_size_out
= binary
.code_size
;
682 free(binary
.global_symbol_offsets
);
684 variant
->ref_count
= 1;
686 if (device
->keep_shader_info
) {
687 variant
->disasm_string
= binary
.disasm_string
;
688 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
689 if (!gs_copy_shader
&& !module
->nir
) {
690 variant
->nir
= *shaders
;
691 variant
->spirv
= (uint32_t *)module
->data
;
692 variant
->spirv_size
= module
->size
;
695 free(binary
.disasm_string
);
701 struct radv_shader_variant
*
702 radv_shader_variant_create(struct radv_device
*device
,
703 struct radv_shader_module
*module
,
704 struct nir_shader
*const *shaders
,
706 struct radv_pipeline_layout
*layout
,
707 const struct radv_shader_variant_key
*key
,
709 unsigned *code_size_out
)
711 struct radv_nir_compiler_options options
= {0};
713 options
.layout
= layout
;
717 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
718 options
.supports_spill
= true;
720 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
721 &options
, false, code_out
, code_size_out
);
724 struct radv_shader_variant
*
725 radv_create_gs_copy_shader(struct radv_device
*device
,
726 struct nir_shader
*shader
,
728 unsigned *code_size_out
,
731 struct radv_nir_compiler_options options
= {0};
733 options
.key
.has_multiview_view_index
= multiview
;
735 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
736 &options
, true, code_out
, code_size_out
);
740 radv_shader_variant_destroy(struct radv_device
*device
,
741 struct radv_shader_variant
*variant
)
743 if (!p_atomic_dec_zero(&variant
->ref_count
))
746 mtx_lock(&device
->shader_slab_mutex
);
747 list_del(&variant
->slab_list
);
748 mtx_unlock(&device
->shader_slab_mutex
);
750 ralloc_free(variant
->nir
);
751 free(variant
->disasm_string
);
752 free(variant
->llvm_ir_string
);
757 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
760 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
761 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
762 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
763 case MESA_SHADER_COMPUTE
: return "Compute Shader";
764 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
765 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
767 return "Unknown shader";
772 generate_shader_stats(struct radv_device
*device
,
773 struct radv_shader_variant
*variant
,
774 gl_shader_stage stage
,
775 struct _mesa_string_buffer
*buf
)
777 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
778 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
779 struct ac_shader_config
*conf
;
780 unsigned max_simd_waves
;
781 unsigned lds_per_wave
= 0;
783 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
785 conf
= &variant
->config
;
787 if (stage
== MESA_SHADER_FRAGMENT
) {
788 lds_per_wave
= conf
->lds_size
* lds_increment
+
789 align(variant
->info
.fs
.num_interp
* 48,
791 } else if (stage
== MESA_SHADER_COMPUTE
) {
792 unsigned max_workgroup_size
=
793 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
794 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
795 DIV_ROUND_UP(max_workgroup_size
, 64);
801 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
806 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
808 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
812 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
814 if (stage
== MESA_SHADER_FRAGMENT
) {
815 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
816 "SPI_PS_INPUT_ADDR = 0x%04x\n"
817 "SPI_PS_INPUT_ENA = 0x%04x\n",
818 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
821 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
824 "Spilled SGPRs: %d\n"
825 "Spilled VGPRs: %d\n"
826 "PrivMem VGPRS: %d\n"
827 "Code Size: %d bytes\n"
829 "Scratch: %d bytes per wave\n"
831 "********************\n\n\n",
832 conf
->num_sgprs
, conf
->num_vgprs
,
833 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
834 variant
->info
.private_mem_vgprs
, variant
->code_size
,
835 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
840 radv_shader_dump_stats(struct radv_device
*device
,
841 struct radv_shader_variant
*variant
,
842 gl_shader_stage stage
,
845 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
847 generate_shader_stats(device
, variant
, stage
, buf
);
849 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
850 fprintf(file
, "%s", buf
->buf
);
852 _mesa_string_buffer_destroy(buf
);
856 radv_GetShaderInfoAMD(VkDevice _device
,
857 VkPipeline _pipeline
,
858 VkShaderStageFlagBits shaderStage
,
859 VkShaderInfoTypeAMD infoType
,
863 RADV_FROM_HANDLE(radv_device
, device
, _device
);
864 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
865 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
866 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
867 struct _mesa_string_buffer
*buf
;
868 VkResult result
= VK_SUCCESS
;
870 /* Spec doesn't indicate what to do if the stage is invalid, so just
871 * return no info for this. */
873 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
876 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
878 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
880 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
881 struct ac_shader_config
*conf
= &variant
->config
;
883 VkShaderStatisticsInfoAMD statistics
= {};
884 statistics
.shaderStageMask
= shaderStage
;
885 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
886 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
887 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
889 if (stage
== MESA_SHADER_COMPUTE
) {
890 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
891 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
893 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
894 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
896 statistics
.computeWorkGroupSize
[0] = local_size
[0];
897 statistics
.computeWorkGroupSize
[1] = local_size
[1];
898 statistics
.computeWorkGroupSize
[2] = local_size
[2];
900 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
903 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
904 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
905 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
906 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
907 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
909 size_t size
= *pInfoSize
;
910 *pInfoSize
= sizeof(statistics
);
912 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
914 if (size
< *pInfoSize
)
915 result
= VK_INCOMPLETE
;
919 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
920 buf
= _mesa_string_buffer_create(NULL
, 1024);
922 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
923 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
924 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
925 generate_shader_stats(device
, variant
, stage
, buf
);
927 /* Need to include the null terminator. */
928 size_t length
= buf
->length
+ 1;
933 size_t size
= *pInfoSize
;
936 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
939 result
= VK_INCOMPLETE
;
942 _mesa_string_buffer_destroy(buf
);
945 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
946 result
= VK_ERROR_FEATURE_NOT_PRESENT
;