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radv: Replace supports_spill with explict_scratch_args
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 unsigned shader_io_get_unique_index(gl_varying_slot slot)
156 {
157 /* handle patch indices separate */
158 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
159 return 0;
160 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
161 return 1;
162 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
163 return 2 + (slot - VARYING_SLOT_PATCH0);
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 if (slot == VARYING_SLOT_CLIP_DIST1)
171 return 3;
172 /* 3 is reserved for clip dist as well */
173 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
174 return 4 + (slot - VARYING_SLOT_VAR0);
175 unreachable("illegal slot in get unique index\n");
176 }
177
178 VkResult radv_CreateShaderModule(
179 VkDevice _device,
180 const VkShaderModuleCreateInfo* pCreateInfo,
181 const VkAllocationCallbacks* pAllocator,
182 VkShaderModule* pShaderModule)
183 {
184 RADV_FROM_HANDLE(radv_device, device, _device);
185 struct radv_shader_module *module;
186
187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
188 assert(pCreateInfo->flags == 0);
189
190 module = vk_alloc2(&device->alloc, pAllocator,
191 sizeof(*module) + pCreateInfo->codeSize, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (module == NULL)
194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 module->nir = NULL;
197 module->size = pCreateInfo->codeSize;
198 memcpy(module->data, pCreateInfo->pCode, module->size);
199
200 _mesa_sha1_compute(module->data, module->size, module->sha1);
201
202 *pShaderModule = radv_shader_module_to_handle(module);
203
204 return VK_SUCCESS;
205 }
206
207 void radv_DestroyShaderModule(
208 VkDevice _device,
209 VkShaderModule _module,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 RADV_FROM_HANDLE(radv_device, device, _device);
213 RADV_FROM_HANDLE(radv_shader_module, module, _module);
214
215 if (!module)
216 return;
217
218 vk_free2(&device->alloc, pAllocator, module);
219 }
220
221 void
222 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
223 bool allow_copies)
224 {
225 bool progress;
226 unsigned lower_flrp =
227 (shader->options->lower_flrp16 ? 16 : 0) |
228 (shader->options->lower_flrp32 ? 32 : 0) |
229 (shader->options->lower_flrp64 ? 64 : 0);
230
231 do {
232 progress = false;
233
234 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
235 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
236
237 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
238 NIR_PASS_V(shader, nir_lower_pack);
239
240 if (allow_copies) {
241 /* Only run this pass in the first call to
242 * radv_optimize_nir. Later calls assume that we've
243 * lowered away any copy_deref instructions and we
244 * don't want to introduce any more.
245 */
246 NIR_PASS(progress, shader, nir_opt_find_array_copies);
247 }
248
249 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
250 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
251 NIR_PASS(progress, shader, nir_remove_dead_variables,
252 nir_var_function_temp);
253
254 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
255 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
256
257 NIR_PASS(progress, shader, nir_copy_prop);
258 NIR_PASS(progress, shader, nir_opt_remove_phis);
259 NIR_PASS(progress, shader, nir_opt_dce);
260 if (nir_opt_trivial_continues(shader)) {
261 progress = true;
262 NIR_PASS(progress, shader, nir_copy_prop);
263 NIR_PASS(progress, shader, nir_opt_remove_phis);
264 NIR_PASS(progress, shader, nir_opt_dce);
265 }
266 NIR_PASS(progress, shader, nir_opt_if, true);
267 NIR_PASS(progress, shader, nir_opt_dead_cf);
268 NIR_PASS(progress, shader, nir_opt_cse);
269 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
270 NIR_PASS(progress, shader, nir_opt_constant_folding);
271 NIR_PASS(progress, shader, nir_opt_algebraic);
272
273 if (lower_flrp != 0) {
274 bool lower_flrp_progress = false;
275 NIR_PASS(lower_flrp_progress,
276 shader,
277 nir_lower_flrp,
278 lower_flrp,
279 false /* always_precise */,
280 shader->options->lower_ffma);
281 if (lower_flrp_progress) {
282 NIR_PASS(progress, shader,
283 nir_opt_constant_folding);
284 progress = true;
285 }
286
287 /* Nothing should rematerialize any flrps, so we only
288 * need to do this lowering once.
289 */
290 lower_flrp = 0;
291 }
292
293 NIR_PASS(progress, shader, nir_opt_undef);
294 if (shader->options->max_unroll_iterations) {
295 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
296 }
297 } while (progress && !optimize_conservatively);
298
299 NIR_PASS(progress, shader, nir_opt_conditional_discard);
300 NIR_PASS(progress, shader, nir_opt_shrink_load);
301 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
302 }
303
304 nir_shader *
305 radv_shader_compile_to_nir(struct radv_device *device,
306 struct radv_shader_module *module,
307 const char *entrypoint_name,
308 gl_shader_stage stage,
309 const VkSpecializationInfo *spec_info,
310 const VkPipelineCreateFlags flags,
311 const struct radv_pipeline_layout *layout,
312 bool use_aco)
313 {
314 nir_shader *nir;
315 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
316 &nir_options_llvm;
317 if (module->nir) {
318 /* Some things such as our meta clear/blit code will give us a NIR
319 * shader directly. In that case, we just ignore the SPIR-V entirely
320 * and just use the NIR shader */
321 nir = module->nir;
322 nir->options = nir_options;
323 nir_validate_shader(nir, "in internal shader");
324
325 assert(exec_list_length(&nir->functions) == 1);
326 } else {
327 uint32_t *spirv = (uint32_t *) module->data;
328 assert(module->size % 4 == 0);
329
330 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
331 radv_print_spirv(module->data, module->size, stderr);
332
333 uint32_t num_spec_entries = 0;
334 struct nir_spirv_specialization *spec_entries = NULL;
335 if (spec_info && spec_info->mapEntryCount > 0) {
336 num_spec_entries = spec_info->mapEntryCount;
337 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
338 for (uint32_t i = 0; i < num_spec_entries; i++) {
339 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
340 const void *data = spec_info->pData + entry.offset;
341 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
342
343 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
344 if (spec_info->dataSize == 8)
345 spec_entries[i].data64 = *(const uint64_t *)data;
346 else
347 spec_entries[i].data32 = *(const uint32_t *)data;
348 }
349 }
350 const struct spirv_to_nir_options spirv_options = {
351 .lower_ubo_ssbo_access_to_offsets = true,
352 .caps = {
353 .amd_gcn_shader = true,
354 .amd_shader_ballot = device->physical_device->use_shader_ballot,
355 .amd_trinary_minmax = true,
356 .demote_to_helper_invocation = device->physical_device->use_aco,
357 .derivative_group = true,
358 .descriptor_array_dynamic_indexing = true,
359 .descriptor_array_non_uniform_indexing = true,
360 .descriptor_indexing = true,
361 .device_group = true,
362 .draw_parameters = true,
363 .float_controls = true,
364 .float16 = !device->physical_device->use_aco,
365 .float64 = true,
366 .geometry_streams = true,
367 .image_read_without_format = true,
368 .image_write_without_format = true,
369 .int8 = !device->physical_device->use_aco,
370 .int16 = !device->physical_device->use_aco,
371 .int64 = true,
372 .int64_atomics = true,
373 .multiview = true,
374 .physical_storage_buffer_address = true,
375 .post_depth_coverage = true,
376 .runtime_descriptor_array = true,
377 .shader_clock = true,
378 .shader_viewport_index_layer = true,
379 .stencil_export = true,
380 .storage_8bit = !device->physical_device->use_aco,
381 .storage_16bit = !device->physical_device->use_aco,
382 .storage_image_ms = true,
383 .subgroup_arithmetic = true,
384 .subgroup_ballot = true,
385 .subgroup_basic = true,
386 .subgroup_quad = true,
387 .subgroup_shuffle = true,
388 .subgroup_vote = true,
389 .tessellation = true,
390 .transform_feedback = true,
391 .variable_pointers = true,
392 },
393 .ubo_addr_format = nir_address_format_32bit_index_offset,
394 .ssbo_addr_format = nir_address_format_32bit_index_offset,
395 .phys_ssbo_addr_format = nir_address_format_64bit_global,
396 .push_const_addr_format = nir_address_format_logical,
397 .shared_addr_format = nir_address_format_32bit_offset,
398 .frag_coord_is_sysval = true,
399 };
400 nir = spirv_to_nir(spirv, module->size / 4,
401 spec_entries, num_spec_entries,
402 stage, entrypoint_name,
403 &spirv_options, nir_options);
404 assert(nir->info.stage == stage);
405 nir_validate_shader(nir, "after spirv_to_nir");
406
407 free(spec_entries);
408
409 /* We have to lower away local constant initializers right before we
410 * inline functions. That way they get properly initialized at the top
411 * of the function and not at the top of its caller.
412 */
413 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
414 NIR_PASS_V(nir, nir_lower_returns);
415 NIR_PASS_V(nir, nir_inline_functions);
416 NIR_PASS_V(nir, nir_opt_deref);
417
418 /* Pick off the single entrypoint that we want */
419 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
420 if (func->is_entrypoint)
421 func->name = ralloc_strdup(func, "main");
422 else
423 exec_node_remove(&func->node);
424 }
425 assert(exec_list_length(&nir->functions) == 1);
426
427 /* Make sure we lower constant initializers on output variables so that
428 * nir_remove_dead_variables below sees the corresponding stores
429 */
430 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
431
432 /* Now that we've deleted all but the main function, we can go ahead and
433 * lower the rest of the constant initializers.
434 */
435 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
436
437 /* Split member structs. We do this before lower_io_to_temporaries so that
438 * it doesn't lower system values to temporaries by accident.
439 */
440 NIR_PASS_V(nir, nir_split_var_copies);
441 NIR_PASS_V(nir, nir_split_per_member_structs);
442
443 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
444 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
445 if (nir->info.stage == MESA_SHADER_FRAGMENT)
446 NIR_PASS_V(nir, nir_lower_input_attachments, true);
447
448 NIR_PASS_V(nir, nir_remove_dead_variables,
449 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
450
451 NIR_PASS_V(nir, nir_propagate_invariant);
452
453 NIR_PASS_V(nir, nir_lower_system_values);
454 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
455 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
456 }
457
458 /* Vulkan uses the separate-shader linking model */
459 nir->info.separate_shader = true;
460
461 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
462
463 static const nir_lower_tex_options tex_options = {
464 .lower_txp = ~0,
465 .lower_tg4_offsets = true,
466 };
467
468 nir_lower_tex(nir, &tex_options);
469
470 nir_lower_vars_to_ssa(nir);
471
472 if (nir->info.stage == MESA_SHADER_VERTEX ||
473 nir->info.stage == MESA_SHADER_GEOMETRY ||
474 nir->info.stage == MESA_SHADER_FRAGMENT) {
475 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
476 nir_shader_get_entrypoint(nir), true, true);
477 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
478 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
479 nir_shader_get_entrypoint(nir), true, false);
480 }
481
482 nir_split_var_copies(nir);
483
484 nir_lower_global_vars_to_local(nir);
485 nir_remove_dead_variables(nir, nir_var_function_temp);
486 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
487 .subgroup_size = 64,
488 .ballot_bit_size = 64,
489 .lower_to_scalar = 1,
490 .lower_subgroup_masks = 1,
491 .lower_shuffle = 1,
492 .lower_shuffle_to_32bit = 1,
493 .lower_vote_eq_to_ballot = 1,
494 });
495
496 nir_lower_load_const_to_scalar(nir);
497
498 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
499 radv_optimize_nir(nir, false, true);
500
501 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
502 * to remove any copies introduced by nir_opt_find_array_copies().
503 */
504 nir_lower_var_copies(nir);
505
506 /* Lower large variables that are always constant with load_constant
507 * intrinsics, which get turned into PC-relative loads from a data
508 * section next to the shader.
509 */
510 NIR_PASS_V(nir, nir_opt_large_constants,
511 glsl_get_natural_size_align_bytes, 16);
512
513 /* Indirect lowering must be called after the radv_optimize_nir() loop
514 * has been called at least once. Otherwise indirect lowering can
515 * bloat the instruction count of the loop and cause it to be
516 * considered too large for unrolling.
517 */
518 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
519 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
520
521 return nir;
522 }
523
524 static int
525 type_size_vec4(const struct glsl_type *type, bool bindless)
526 {
527 return glsl_count_attribute_slots(type, false);
528 }
529
530 static nir_variable *
531 find_layer_in_var(nir_shader *nir)
532 {
533 nir_foreach_variable(var, &nir->inputs) {
534 if (var->data.location == VARYING_SLOT_LAYER) {
535 return var;
536 }
537 }
538
539 nir_variable *var =
540 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
541 var->data.location = VARYING_SLOT_LAYER;
542 var->data.interpolation = INTERP_MODE_FLAT;
543 return var;
544 }
545
546 /* We use layered rendering to implement multiview, which means we need to map
547 * view_index to gl_Layer. The attachment lowering also uses needs to know the
548 * layer so that it can sample from the correct layer. The code generates a
549 * load from the layer_id sysval, but since we don't have a way to get at this
550 * information from the fragment shader, we also need to lower this to the
551 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
552 * slot, before lowering io, so that nir_assign_var_locations() will give the
553 * LAYER varying the correct driver_location.
554 */
555
556 static bool
557 lower_view_index(nir_shader *nir)
558 {
559 bool progress = false;
560 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
561 nir_builder b;
562 nir_builder_init(&b, entry);
563
564 nir_variable *layer = NULL;
565 nir_foreach_block(block, entry) {
566 nir_foreach_instr_safe(instr, block) {
567 if (instr->type != nir_instr_type_intrinsic)
568 continue;
569
570 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
571 if (load->intrinsic != nir_intrinsic_load_view_index &&
572 load->intrinsic != nir_intrinsic_load_layer_id)
573 continue;
574
575 if (!layer)
576 layer = find_layer_in_var(nir);
577
578 b.cursor = nir_before_instr(instr);
579 nir_ssa_def *def = nir_load_var(&b, layer);
580 nir_ssa_def_rewrite_uses(&load->dest.ssa,
581 nir_src_for_ssa(def));
582
583 nir_instr_remove(instr);
584 progress = true;
585 }
586 }
587
588 return progress;
589 }
590
591 void
592 radv_lower_fs_io(nir_shader *nir)
593 {
594 NIR_PASS_V(nir, lower_view_index);
595 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
596 MESA_SHADER_FRAGMENT);
597
598 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
599
600 /* This pass needs actual constants */
601 nir_opt_constant_folding(nir);
602
603 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
604 }
605
606
607 void *
608 radv_alloc_shader_memory(struct radv_device *device,
609 struct radv_shader_variant *shader)
610 {
611 mtx_lock(&device->shader_slab_mutex);
612 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
613 uint64_t offset = 0;
614 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
615 if (s->bo_offset - offset >= shader->code_size) {
616 shader->bo = slab->bo;
617 shader->bo_offset = offset;
618 list_addtail(&shader->slab_list, &s->slab_list);
619 mtx_unlock(&device->shader_slab_mutex);
620 return slab->ptr + offset;
621 }
622 offset = align_u64(s->bo_offset + s->code_size, 256);
623 }
624 if (slab->size - offset >= shader->code_size) {
625 shader->bo = slab->bo;
626 shader->bo_offset = offset;
627 list_addtail(&shader->slab_list, &slab->shaders);
628 mtx_unlock(&device->shader_slab_mutex);
629 return slab->ptr + offset;
630 }
631 }
632
633 mtx_unlock(&device->shader_slab_mutex);
634 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
635
636 slab->size = 256 * 1024;
637 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
638 RADEON_DOMAIN_VRAM,
639 RADEON_FLAG_NO_INTERPROCESS_SHARING |
640 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
641 0 : RADEON_FLAG_READ_ONLY),
642 RADV_BO_PRIORITY_SHADER);
643 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
644 list_inithead(&slab->shaders);
645
646 mtx_lock(&device->shader_slab_mutex);
647 list_add(&slab->slabs, &device->shader_slabs);
648
649 shader->bo = slab->bo;
650 shader->bo_offset = 0;
651 list_add(&shader->slab_list, &slab->shaders);
652 mtx_unlock(&device->shader_slab_mutex);
653 return slab->ptr;
654 }
655
656 void
657 radv_destroy_shader_slabs(struct radv_device *device)
658 {
659 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
660 device->ws->buffer_destroy(slab->bo);
661 free(slab);
662 }
663 mtx_destroy(&device->shader_slab_mutex);
664 }
665
666 /* For the UMR disassembler. */
667 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
668 #define DEBUGGER_NUM_MARKERS 5
669
670 static unsigned
671 radv_get_shader_binary_size(size_t code_size)
672 {
673 return code_size + DEBUGGER_NUM_MARKERS * 4;
674 }
675
676 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
677 const struct ac_shader_config *config_in,
678 const struct radv_shader_info *info,
679 gl_shader_stage stage,
680 struct ac_shader_config *config_out)
681 {
682 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
683 unsigned vgpr_comp_cnt = 0;
684 unsigned num_input_vgprs = info->num_input_vgprs;
685
686 if (stage == MESA_SHADER_FRAGMENT) {
687 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
688 }
689
690 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
691 /* +3 for scratch wave offset and VCC */
692 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
693 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
694 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
695 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
696 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
697 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
698
699 *config_out = *config_in;
700 config_out->num_vgprs = num_vgprs;
701 config_out->num_sgprs = num_sgprs;
702 config_out->num_shared_vgprs = num_shared_vgprs;
703
704 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
705 S_00B12C_SCRATCH_EN(scratch_enabled);
706
707 if (!pdevice->use_ngg_streamout) {
708 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
709 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
710 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
711 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
712 S_00B12C_SO_EN(!!info->so.num_outputs);
713 }
714
715 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
716 (info->wave_size == 32 ? 8 : 4)) |
717 S_00B848_DX10_CLAMP(1) |
718 S_00B848_FLOAT_MODE(config_out->float_mode);
719
720 if (pdevice->rad_info.chip_class >= GFX10) {
721 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
722 } else {
723 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
724 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
725 }
726
727 switch (stage) {
728 case MESA_SHADER_TESS_EVAL:
729 if (info->is_ngg) {
730 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
731 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
732 } else if (info->tes.as_es) {
733 assert(pdevice->rad_info.chip_class <= GFX8);
734 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
735
736 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
737 } else {
738 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
739 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
740
741 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
742 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
743 }
744 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
745 break;
746 case MESA_SHADER_TESS_CTRL:
747 if (pdevice->rad_info.chip_class >= GFX9) {
748 /* We need at least 2 components for LS.
749 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
750 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
751 */
752 if (pdevice->rad_info.chip_class >= GFX10) {
753 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
754 } else {
755 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
756 }
757 } else {
758 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
759 }
760 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
761 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
762 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
763 break;
764 case MESA_SHADER_VERTEX:
765 if (info->is_ngg) {
766 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
767 } else if (info->vs.as_ls) {
768 assert(pdevice->rad_info.chip_class <= GFX8);
769 /* We need at least 2 components for LS.
770 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
771 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
772 */
773 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
774 } else if (info->vs.as_es) {
775 assert(pdevice->rad_info.chip_class <= GFX8);
776 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
777 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
778 } else {
779 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
780 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
781 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
782 */
783 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
784 vgpr_comp_cnt = 3;
785 } else if (info->vs.export_prim_id) {
786 vgpr_comp_cnt = 2;
787 } else if (info->vs.needs_instance_id) {
788 vgpr_comp_cnt = 1;
789 } else {
790 vgpr_comp_cnt = 0;
791 }
792
793 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
794 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
795 }
796 break;
797 case MESA_SHADER_FRAGMENT:
798 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
799 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
800 break;
801 case MESA_SHADER_GEOMETRY:
802 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
803 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
804 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
805 break;
806 case MESA_SHADER_COMPUTE:
807 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
808 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
809 config_out->rsrc2 |=
810 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
811 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
812 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
813 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
814 info->cs.uses_thread_id[1] ? 1 : 0) |
815 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
816 S_00B84C_LDS_SIZE(config_in->lds_size);
817 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
818
819 break;
820 default:
821 unreachable("unsupported shader type");
822 break;
823 }
824
825 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
826 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
827 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
828 gl_shader_stage es_stage = stage;
829 if (stage == MESA_SHADER_GEOMETRY)
830 es_stage = info->gs.es_type;
831
832 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
833 if (es_stage == MESA_SHADER_VERTEX) {
834 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
835 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
836 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
837 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
838 } else
839 unreachable("Unexpected ES shader stage");
840
841 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
842 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
843 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
844 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
845 } else if (info->uses_prim_id) {
846 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
847 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
848 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
849 } else {
850 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
851 }
852
853 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
854 S_00B228_WGP_MODE(1);
855 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
856 S_00B22C_LDS_SIZE(config_in->lds_size) |
857 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
858 } else if (pdevice->rad_info.chip_class >= GFX9 &&
859 stage == MESA_SHADER_GEOMETRY) {
860 unsigned es_type = info->gs.es_type;
861 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
862
863 if (es_type == MESA_SHADER_VERTEX) {
864 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
865 if (info->vs.needs_instance_id) {
866 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
867 } else {
868 es_vgpr_comp_cnt = 0;
869 }
870 } else if (es_type == MESA_SHADER_TESS_EVAL) {
871 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
872 } else {
873 unreachable("invalid shader ES type");
874 }
875
876 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
877 * VGPR[0:4] are always loaded.
878 */
879 if (info->uses_invocation_id) {
880 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
881 } else if (info->uses_prim_id) {
882 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
883 } else if (info->gs.vertices_in >= 3) {
884 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
885 } else {
886 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
887 }
888
889 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
890 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
891 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
892 } else if (pdevice->rad_info.chip_class >= GFX9 &&
893 stage == MESA_SHADER_TESS_CTRL) {
894 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
895 } else {
896 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
897 }
898 }
899
900 struct radv_shader_variant *
901 radv_shader_variant_create(struct radv_device *device,
902 const struct radv_shader_binary *binary,
903 bool keep_shader_info)
904 {
905 struct ac_shader_config config = {0};
906 struct ac_rtld_binary rtld_binary = {0};
907 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
908 if (!variant)
909 return NULL;
910
911 variant->ref_count = 1;
912
913 if (binary->type == RADV_BINARY_TYPE_RTLD) {
914 struct ac_rtld_symbol lds_symbols[2];
915 unsigned num_lds_symbols = 0;
916 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
917 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
918
919 if (device->physical_device->rad_info.chip_class >= GFX9 &&
920 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
921 !binary->is_gs_copy_shader) {
922 /* We add this symbol even on LLVM <= 8 to ensure that
923 * shader->config.lds_size is set correctly below.
924 */
925 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
926 sym->name = "esgs_ring";
927 sym->size = binary->info.ngg_info.esgs_ring_size;
928 sym->align = 64 * 1024;
929 }
930
931 if (binary->info.is_ngg &&
932 binary->stage == MESA_SHADER_GEOMETRY) {
933 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
934 sym->name = "ngg_emit";
935 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
936 sym->align = 4;
937 }
938
939 struct ac_rtld_open_info open_info = {
940 .info = &device->physical_device->rad_info,
941 .shader_type = binary->stage,
942 .wave_size = binary->info.wave_size,
943 .num_parts = 1,
944 .elf_ptrs = &elf_data,
945 .elf_sizes = &elf_size,
946 .num_shared_lds_symbols = num_lds_symbols,
947 .shared_lds_symbols = lds_symbols,
948 };
949
950 if (!ac_rtld_open(&rtld_binary, open_info)) {
951 free(variant);
952 return NULL;
953 }
954
955 if (!ac_rtld_read_config(&rtld_binary, &config)) {
956 ac_rtld_close(&rtld_binary);
957 free(variant);
958 return NULL;
959 }
960
961 /* Enable 64-bit and 16-bit denormals, because there is no performance
962 * cost.
963 *
964 * If denormals are enabled, all floating-point output modifiers are
965 * ignored.
966 *
967 * Don't enable denormals for 32-bit floats, because:
968 * - Floating-point output modifiers would be ignored by the hw.
969 * - Some opcodes don't support denormals, such as v_mad_f32. We would
970 * have to stop using those.
971 * - GFX6 & GFX7 would be very slow.
972 */
973 config.float_mode |= V_00B028_FP_64_DENORMS;
974
975 if (rtld_binary.lds_size > 0) {
976 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
977 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
978 }
979
980 variant->code_size = rtld_binary.rx_size;
981 variant->exec_size = rtld_binary.exec_size;
982 } else {
983 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
984 config = ((struct radv_shader_binary_legacy *)binary)->config;
985 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
986 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
987 }
988
989 variant->info = binary->info;
990 radv_postprocess_config(device->physical_device, &config, &binary->info,
991 binary->stage, &variant->config);
992
993 if (radv_device_use_secure_compile(device->instance)) {
994 if (binary->type == RADV_BINARY_TYPE_RTLD)
995 ac_rtld_close(&rtld_binary);
996
997 return variant;
998 }
999
1000 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1001
1002 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1003 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1004 struct ac_rtld_upload_info info = {
1005 .binary = &rtld_binary,
1006 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1007 .rx_ptr = dest_ptr,
1008 };
1009
1010 if (!ac_rtld_upload(&info)) {
1011 radv_shader_variant_destroy(device, variant);
1012 ac_rtld_close(&rtld_binary);
1013 return NULL;
1014 }
1015
1016 if (keep_shader_info ||
1017 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1018 const char *disasm_data;
1019 size_t disasm_size;
1020 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1021 radv_shader_variant_destroy(device, variant);
1022 ac_rtld_close(&rtld_binary);
1023 return NULL;
1024 }
1025
1026 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1027 variant->disasm_string = malloc(disasm_size + 1);
1028 memcpy(variant->disasm_string, disasm_data, disasm_size);
1029 variant->disasm_string[disasm_size] = 0;
1030 }
1031
1032 ac_rtld_close(&rtld_binary);
1033 } else {
1034 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1035 memcpy(dest_ptr, bin->data, bin->code_size);
1036
1037 /* Add end-of-code markers for the UMR disassembler. */
1038 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1039 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1040 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1041
1042 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1043 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1044 }
1045 return variant;
1046 }
1047
1048 static char *
1049 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1050 int shader_count)
1051 {
1052 char *data = NULL;
1053 char *ret = NULL;
1054 size_t size = 0;
1055 FILE *f = open_memstream(&data, &size);
1056 if (f) {
1057 for (int i = 0; i < shader_count; ++i)
1058 nir_print_shader(shaders[i], f);
1059 fclose(f);
1060 }
1061
1062 ret = malloc(size + 1);
1063 if (ret) {
1064 memcpy(ret, data, size);
1065 ret[size] = 0;
1066 }
1067 free(data);
1068 return ret;
1069 }
1070
1071 static struct radv_shader_variant *
1072 shader_variant_compile(struct radv_device *device,
1073 struct radv_shader_module *module,
1074 struct nir_shader * const *shaders,
1075 int shader_count,
1076 gl_shader_stage stage,
1077 struct radv_shader_info *info,
1078 struct radv_nir_compiler_options *options,
1079 bool gs_copy_shader,
1080 bool keep_shader_info,
1081 bool use_aco,
1082 struct radv_shader_binary **binary_out)
1083 {
1084 enum radeon_family chip_family = device->physical_device->rad_info.family;
1085 struct radv_shader_binary *binary = NULL;
1086
1087 options->family = chip_family;
1088 options->chip_class = device->physical_device->rad_info.chip_class;
1089 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1090 options->dump_preoptir = options->dump_shader &&
1091 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1092 options->record_ir = keep_shader_info;
1093 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1094 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1095 options->address32_hi = device->physical_device->rad_info.address32_hi;
1096 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1097 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1098
1099 struct radv_shader_args args = {};
1100 args.options = options;
1101 args.shader_info = info;
1102 args.is_gs_copy_shader = gs_copy_shader;
1103 radv_declare_shader_args(&args,
1104 gs_copy_shader ? MESA_SHADER_VERTEX
1105 : shaders[shader_count - 1]->info.stage,
1106 shader_count >= 2,
1107 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1108 : MESA_SHADER_VERTEX);
1109
1110 if (!use_aco || options->dump_shader || options->record_ir)
1111 ac_init_llvm_once();
1112
1113 if (use_aco) {
1114 aco_compile_shader(shader_count, shaders, &binary, &args);
1115 binary->info = *info;
1116 } else {
1117 enum ac_target_machine_options tm_options = 0;
1118 struct ac_llvm_compiler ac_llvm;
1119 bool thread_compiler;
1120
1121 tm_options |= AC_TM_SUPPORTS_SPILL;
1122 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1123 tm_options |= AC_TM_SISCHED;
1124 if (options->check_ir)
1125 tm_options |= AC_TM_CHECK_IR;
1126 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1127 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1128
1129 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1130 radv_init_llvm_compiler(&ac_llvm,
1131 thread_compiler,
1132 chip_family, tm_options,
1133 info->wave_size);
1134
1135 if (gs_copy_shader) {
1136 assert(shader_count == 1);
1137 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1138 &args);
1139 } else {
1140 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1141 shaders, shader_count);
1142 }
1143
1144 binary->info = *info;
1145 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1146 }
1147
1148 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1149 keep_shader_info);
1150 if (!variant) {
1151 free(binary);
1152 return NULL;
1153 }
1154 variant->aco_used = use_aco;
1155
1156 if (options->dump_shader) {
1157 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1158 }
1159
1160
1161 if (keep_shader_info) {
1162 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1163 if (!gs_copy_shader && !module->nir) {
1164 variant->spirv = malloc(module->size);
1165 if (!variant->spirv) {
1166 free(variant);
1167 free(binary);
1168 return NULL;
1169 }
1170
1171 memcpy(variant->spirv, module->data, module->size);
1172 variant->spirv_size = module->size;
1173 }
1174 }
1175
1176 if (binary_out)
1177 *binary_out = binary;
1178 else
1179 free(binary);
1180
1181 return variant;
1182 }
1183
1184 struct radv_shader_variant *
1185 radv_shader_variant_compile(struct radv_device *device,
1186 struct radv_shader_module *module,
1187 struct nir_shader *const *shaders,
1188 int shader_count,
1189 struct radv_pipeline_layout *layout,
1190 const struct radv_shader_variant_key *key,
1191 struct radv_shader_info *info,
1192 bool keep_shader_info,
1193 bool use_aco,
1194 struct radv_shader_binary **binary_out)
1195 {
1196 struct radv_nir_compiler_options options = {0};
1197
1198 options.layout = layout;
1199 if (key)
1200 options.key = *key;
1201
1202 options.explicit_scratch_args = use_aco;
1203 options.robust_buffer_access = device->robust_buffer_access;
1204
1205 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1206 &options, false, keep_shader_info, use_aco, binary_out);
1207 }
1208
1209 struct radv_shader_variant *
1210 radv_create_gs_copy_shader(struct radv_device *device,
1211 struct nir_shader *shader,
1212 struct radv_shader_info *info,
1213 struct radv_shader_binary **binary_out,
1214 bool keep_shader_info,
1215 bool multiview)
1216 {
1217 struct radv_nir_compiler_options options = {0};
1218
1219 options.key.has_multiview_view_index = multiview;
1220
1221 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1222 info, &options, true, keep_shader_info, false, binary_out);
1223 }
1224
1225 void
1226 radv_shader_variant_destroy(struct radv_device *device,
1227 struct radv_shader_variant *variant)
1228 {
1229 if (!p_atomic_dec_zero(&variant->ref_count))
1230 return;
1231
1232 mtx_lock(&device->shader_slab_mutex);
1233 list_del(&variant->slab_list);
1234 mtx_unlock(&device->shader_slab_mutex);
1235
1236 free(variant->spirv);
1237 free(variant->nir_string);
1238 free(variant->disasm_string);
1239 free(variant->ir_string);
1240 free(variant);
1241 }
1242
1243 const char *
1244 radv_get_shader_name(struct radv_shader_info *info,
1245 gl_shader_stage stage)
1246 {
1247 switch (stage) {
1248 case MESA_SHADER_VERTEX:
1249 if (info->vs.as_ls)
1250 return "Vertex Shader as LS";
1251 else if (info->vs.as_es)
1252 return "Vertex Shader as ES";
1253 else if (info->is_ngg)
1254 return "Vertex Shader as ESGS";
1255 else
1256 return "Vertex Shader as VS";
1257 case MESA_SHADER_TESS_CTRL:
1258 return "Tessellation Control Shader";
1259 case MESA_SHADER_TESS_EVAL:
1260 if (info->tes.as_es)
1261 return "Tessellation Evaluation Shader as ES";
1262 else if (info->is_ngg)
1263 return "Tessellation Evaluation Shader as ESGS";
1264 else
1265 return "Tessellation Evaluation Shader as VS";
1266 case MESA_SHADER_GEOMETRY:
1267 return "Geometry Shader";
1268 case MESA_SHADER_FRAGMENT:
1269 return "Pixel Shader";
1270 case MESA_SHADER_COMPUTE:
1271 return "Compute Shader";
1272 default:
1273 return "Unknown shader";
1274 };
1275 }
1276
1277 unsigned
1278 radv_get_max_workgroup_size(enum chip_class chip_class,
1279 gl_shader_stage stage,
1280 const unsigned *sizes)
1281 {
1282 switch (stage) {
1283 case MESA_SHADER_TESS_CTRL:
1284 return chip_class >= GFX7 ? 128 : 64;
1285 case MESA_SHADER_GEOMETRY:
1286 return chip_class >= GFX9 ? 128 : 64;
1287 case MESA_SHADER_COMPUTE:
1288 break;
1289 default:
1290 return 0;
1291 }
1292
1293 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1294 return max_workgroup_size;
1295 }
1296
1297 unsigned
1298 radv_get_max_waves(struct radv_device *device,
1299 struct radv_shader_variant *variant,
1300 gl_shader_stage stage)
1301 {
1302 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1303 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1304 uint8_t wave_size = variant->info.wave_size;
1305 struct ac_shader_config *conf = &variant->config;
1306 unsigned max_simd_waves;
1307 unsigned lds_per_wave = 0;
1308
1309 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1310
1311 if (stage == MESA_SHADER_FRAGMENT) {
1312 lds_per_wave = conf->lds_size * lds_increment +
1313 align(variant->info.ps.num_interp * 48,
1314 lds_increment);
1315 } else if (stage == MESA_SHADER_COMPUTE) {
1316 unsigned max_workgroup_size =
1317 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1318 lds_per_wave = (conf->lds_size * lds_increment) /
1319 DIV_ROUND_UP(max_workgroup_size, wave_size);
1320 }
1321
1322 if (conf->num_sgprs) {
1323 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1324 max_simd_waves =
1325 MIN2(max_simd_waves,
1326 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1327 sgprs);
1328 }
1329
1330 if (conf->num_vgprs) {
1331 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1332 max_simd_waves =
1333 MIN2(max_simd_waves,
1334 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1335 }
1336
1337 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1338 * that PS can use.
1339 */
1340 if (lds_per_wave)
1341 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1342
1343 return max_simd_waves;
1344 }
1345
1346 static void
1347 generate_shader_stats(struct radv_device *device,
1348 struct radv_shader_variant *variant,
1349 gl_shader_stage stage,
1350 struct _mesa_string_buffer *buf)
1351 {
1352 struct ac_shader_config *conf = &variant->config;
1353 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1354
1355 if (stage == MESA_SHADER_FRAGMENT) {
1356 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1357 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1358 "SPI_PS_INPUT_ENA = 0x%04x\n",
1359 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1360 }
1361
1362 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1363 "SGPRS: %d\n"
1364 "VGPRS: %d\n"
1365 "Spilled SGPRs: %d\n"
1366 "Spilled VGPRs: %d\n"
1367 "PrivMem VGPRS: %d\n"
1368 "Code Size: %d bytes\n"
1369 "LDS: %d blocks\n"
1370 "Scratch: %d bytes per wave\n"
1371 "Max Waves: %d\n"
1372 "********************\n\n\n",
1373 conf->num_sgprs, conf->num_vgprs,
1374 conf->spilled_sgprs, conf->spilled_vgprs,
1375 variant->info.private_mem_vgprs, variant->exec_size,
1376 conf->lds_size, conf->scratch_bytes_per_wave,
1377 max_simd_waves);
1378 }
1379
1380 void
1381 radv_shader_dump_stats(struct radv_device *device,
1382 struct radv_shader_variant *variant,
1383 gl_shader_stage stage,
1384 FILE *file)
1385 {
1386 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1387
1388 generate_shader_stats(device, variant, stage, buf);
1389
1390 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1391 fprintf(file, "%s", buf->buf);
1392
1393 _mesa_string_buffer_destroy(buf);
1394 }
1395
1396 VkResult
1397 radv_GetShaderInfoAMD(VkDevice _device,
1398 VkPipeline _pipeline,
1399 VkShaderStageFlagBits shaderStage,
1400 VkShaderInfoTypeAMD infoType,
1401 size_t* pInfoSize,
1402 void* pInfo)
1403 {
1404 RADV_FROM_HANDLE(radv_device, device, _device);
1405 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1406 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1407 struct radv_shader_variant *variant = pipeline->shaders[stage];
1408 struct _mesa_string_buffer *buf;
1409 VkResult result = VK_SUCCESS;
1410
1411 /* Spec doesn't indicate what to do if the stage is invalid, so just
1412 * return no info for this. */
1413 if (!variant)
1414 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1415
1416 switch (infoType) {
1417 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1418 if (!pInfo) {
1419 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1420 } else {
1421 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1422 struct ac_shader_config *conf = &variant->config;
1423
1424 VkShaderStatisticsInfoAMD statistics = {};
1425 statistics.shaderStageMask = shaderStage;
1426 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1427 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1428 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1429
1430 if (stage == MESA_SHADER_COMPUTE) {
1431 unsigned *local_size = variant->info.cs.block_size;
1432 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1433
1434 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1435 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1436
1437 statistics.computeWorkGroupSize[0] = local_size[0];
1438 statistics.computeWorkGroupSize[1] = local_size[1];
1439 statistics.computeWorkGroupSize[2] = local_size[2];
1440 } else {
1441 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1442 }
1443
1444 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1445 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1446 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1447 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1448 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1449
1450 size_t size = *pInfoSize;
1451 *pInfoSize = sizeof(statistics);
1452
1453 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1454
1455 if (size < *pInfoSize)
1456 result = VK_INCOMPLETE;
1457 }
1458
1459 break;
1460 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1461 buf = _mesa_string_buffer_create(NULL, 1024);
1462
1463 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1464 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1465 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1466 generate_shader_stats(device, variant, stage, buf);
1467
1468 /* Need to include the null terminator. */
1469 size_t length = buf->length + 1;
1470
1471 if (!pInfo) {
1472 *pInfoSize = length;
1473 } else {
1474 size_t size = *pInfoSize;
1475 *pInfoSize = length;
1476
1477 memcpy(pInfo, buf->buf, MIN2(size, length));
1478
1479 if (size < length)
1480 result = VK_INCOMPLETE;
1481 }
1482
1483 _mesa_string_buffer_destroy(buf);
1484 break;
1485 default:
1486 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1487 result = VK_ERROR_FEATURE_NOT_PRESENT;
1488 break;
1489 }
1490
1491 return result;
1492 }