src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 #include "util/string_buffer.h"
  50
  51 static const struct nir_shader_compiler_options nir_options = {
  52         .vertex_id_zero_based = true,
  53         .lower_scmp = true,
  54         .lower_flrp32 = true,
  55         .lower_flrp64 = true,
  56         .lower_fsat = true,
  57         .lower_fdiv = true,
  58         .lower_sub = true,
  59         .lower_pack_snorm_2x16 = true,
  60         .lower_pack_snorm_4x8 = true,
  61         .lower_pack_unorm_2x16 = true,
  62         .lower_pack_unorm_4x8 = true,
  63         .lower_unpack_snorm_2x16 = true,
  64         .lower_unpack_snorm_4x8 = true,
  65         .lower_unpack_unorm_2x16 = true,
  66         .lower_unpack_unorm_4x8 = true,
  67         .lower_extract_byte = true,
  68         .lower_extract_word = true,
  69         .lower_ffma = true,
  70         .max_unroll_iterations = 32
  71 };
  72
  73 VkResult radv_CreateShaderModule(
  74         VkDevice                                    _device,
  75         const VkShaderModuleCreateInfo*             pCreateInfo,
  76         const VkAllocationCallbacks*                pAllocator,
  77         VkShaderModule*                             pShaderModule)
  78 {
  79         RADV_FROM_HANDLE(radv_device, device, _device);
  80         struct radv_shader_module *module;
  81
  82         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  83         assert(pCreateInfo->flags == 0);
  84
  85         module = vk_alloc2(&device->alloc, pAllocator,
  86                              sizeof(*module) + pCreateInfo->codeSize, 8,
  87                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  88         if (module == NULL)
  89                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  90
  91         module->nir = NULL;
  92         module->size = pCreateInfo->codeSize;
  93         memcpy(module->data, pCreateInfo->pCode, module->size);
  94
  95         _mesa_sha1_compute(module->data, module->size, module->sha1);
  96
  97         *pShaderModule = radv_shader_module_to_handle(module);
  98
  99         return VK_SUCCESS;
 100 }
 101
 102 void radv_DestroyShaderModule(
 103         VkDevice                                    _device,
 104         VkShaderModule                              _module,
 105         const VkAllocationCallbacks*                pAllocator)
 106 {
 107         RADV_FROM_HANDLE(radv_device, device, _device);
 108         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 109
 110         if (!module)
 111                 return;
 112
 113         vk_free2(&device->alloc, pAllocator, module);
 114 }
 115
 116 void
 117 radv_optimize_nir(struct nir_shader *shader)
 118 {
 119         bool progress;
 120
 121         do {
 122                 progress = false;
 123
 124                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 125                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 126                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 127                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 128
 129                 NIR_PASS(progress, shader, nir_copy_prop);
 130                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 131                 NIR_PASS(progress, shader, nir_opt_dce);
 132                 if (nir_opt_trivial_continues(shader)) {
 133                         progress = true;
 134                         NIR_PASS(progress, shader, nir_copy_prop);
 135                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 136                         NIR_PASS(progress, shader, nir_opt_dce);
 137                 }
 138                 NIR_PASS(progress, shader, nir_opt_if);
 139                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 140                 NIR_PASS(progress, shader, nir_opt_cse);
 141                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 142                 NIR_PASS(progress, shader, nir_opt_algebraic);
 143                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 144                 NIR_PASS(progress, shader, nir_opt_undef);
 145                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 146                 if (shader->options->max_unroll_iterations) {
 147                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 148                 }
 149         } while (progress);
 150 }
 151
 152 nir_shader *
 153 radv_shader_compile_to_nir(struct radv_device *device,
 154                            struct radv_shader_module *module,
 155                            const char *entrypoint_name,
 156                            gl_shader_stage stage,
 157                            const VkSpecializationInfo *spec_info)
 158 {
 159         if (strcmp(entrypoint_name, "main") != 0) {
 160                 radv_finishme("Multiple shaders per module not really supported");
 161         }
 162
 163         nir_shader *nir;
 164         nir_function *entry_point;
 165         if (module->nir) {
 166                 /* Some things such as our meta clear/blit code will give us a NIR
 167                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 168                  * and just use the NIR shader */
 169                 nir = module->nir;
 170                 nir->options = &nir_options;
 171                 nir_validate_shader(nir);
 172
 173                 assert(exec_list_length(&nir->functions) == 1);
 174                 struct exec_node *node = exec_list_get_head(&nir->functions);
 175                 entry_point = exec_node_data(nir_function, node, node);
 176         } else {
 177                 uint32_t *spirv = (uint32_t *) module->data;
 178                 assert(module->size % 4 == 0);
 179
 180                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 181                         radv_print_spirv(spirv, module->size, stderr);
 182
 183                 uint32_t num_spec_entries = 0;
 184                 struct nir_spirv_specialization *spec_entries = NULL;
 185                 if (spec_info && spec_info->mapEntryCount > 0) {
 186                         num_spec_entries = spec_info->mapEntryCount;
 187                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 188                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 189                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 190                                 const void *data = spec_info->pData + entry.offset;
 191                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 192
 193                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 194                                 if (spec_info->dataSize == 8)
 195                                         spec_entries[i].data64 = *(const uint64_t *)data;
 196                                 else
 197                                         spec_entries[i].data32 = *(const uint32_t *)data;
 198                         }
 199                 }
 200                 const struct spirv_to_nir_options spirv_options = {
 201                         .caps = {
 202                                 .draw_parameters = true,
 203                                 .float64 = true,
 204                                 .image_read_without_format = true,
 205                                 .image_write_without_format = true,
 206                                 .tessellation = true,
 207                                 .int64 = true,
 208                                 .multiview = true,
 209                                 .variable_pointers = true,
 210                         },
 211                 };
 212                 entry_point = spirv_to_nir(spirv, module->size / 4,
 213                                            spec_entries, num_spec_entries,
 214                                            stage, entrypoint_name,
 215                                            &spirv_options, &nir_options);
 216                 nir = entry_point->shader;
 217                 assert(nir->info.stage == stage);
 218                 nir_validate_shader(nir);
 219
 220                 free(spec_entries);
 221
 222                 /* We have to lower away local constant initializers right before we
 223                  * inline functions.  That way they get properly initialized at the top
 224                  * of the function and not at the top of its caller.
 225                  */
 226                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 227                 NIR_PASS_V(nir, nir_lower_returns);
 228                 NIR_PASS_V(nir, nir_inline_functions);
 229
 230                 /* Pick off the single entrypoint that we want */
 231                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 232                         if (func != entry_point)
 233                                 exec_node_remove(&func->node);
 234                 }
 235                 assert(exec_list_length(&nir->functions) == 1);
 236                 entry_point->name = ralloc_strdup(entry_point, "main");
 237
 238                 NIR_PASS_V(nir, nir_remove_dead_variables,
 239                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 240
 241                 /* Now that we've deleted all but the main function, we can go ahead and
 242                  * lower the rest of the constant initializers.
 243                  */
 244                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 245                 NIR_PASS_V(nir, nir_lower_system_values);
 246                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 247         }
 248
 249         /* Vulkan uses the separate-shader linking model */
 250         nir->info.separate_shader = true;
 251
 252         nir_shader_gather_info(nir, entry_point->impl);
 253
 254         /* While it would be nice not to have this flag, we are constrained
 255          * by the reality that LLVM 5.0 doesn't have working VGPR indexing
 256          * on GFX9.
 257          */
 258         bool llvm_has_working_vgpr_indexing =
 259                 device->physical_device->rad_info.chip_class <= VI;
 260
 261         /* TODO: Indirect indexing of GS inputs is unimplemented.
 262          *
 263          * TCS and TES load inputs directly from LDS or offchip memory, so
 264          * indirect indexing is trivial.
 265          */
 266         nir_variable_mode indirect_mask = 0;
 267         if (nir->info.stage == MESA_SHADER_GEOMETRY ||
 268             (nir->info.stage != MESA_SHADER_TESS_CTRL &&
 269              nir->info.stage != MESA_SHADER_TESS_EVAL &&
 270              !llvm_has_working_vgpr_indexing)) {
 271                 indirect_mask |= nir_var_shader_in;
 272         }
 273         if (!llvm_has_working_vgpr_indexing &&
 274             nir->info.stage != MESA_SHADER_TESS_CTRL)
 275                 indirect_mask |= nir_var_shader_out;
 276
 277         /* TODO: We shouldn't need to do this, however LLVM isn't currently
 278          * smart enough to handle indirects without causing excess spilling
 279          * causing the gpu to hang.
 280          *
 281          * See the following thread for more details of the problem:
 282          * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
 283          */
 284         indirect_mask |= nir_var_local;
 285
 286         nir_lower_indirect_derefs(nir, indirect_mask);
 287
 288         static const nir_lower_tex_options tex_options = {
 289           .lower_txp = ~0,
 290         };
 291
 292         nir_lower_tex(nir, &tex_options);
 293
 294         nir_lower_vars_to_ssa(nir);
 295         nir_lower_var_copies(nir);
 296         nir_lower_global_vars_to_local(nir);
 297         nir_remove_dead_variables(nir, nir_var_local);
 298         radv_optimize_nir(nir);
 299
 300         return nir;
 301 }
 302
 303 void *
 304 radv_alloc_shader_memory(struct radv_device *device,
 305                          struct radv_shader_variant *shader)
 306 {
 307         mtx_lock(&device->shader_slab_mutex);
 308         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 309                 uint64_t offset = 0;
 310                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 311                         if (s->bo_offset - offset >= shader->code_size) {
 312                                 shader->bo = slab->bo;
 313                                 shader->bo_offset = offset;
 314                                 list_addtail(&shader->slab_list, &s->slab_list);
 315                                 mtx_unlock(&device->shader_slab_mutex);
 316                                 return slab->ptr + offset;
 317                         }
 318                         offset = align_u64(s->bo_offset + s->code_size, 256);
 319                 }
 320                 if (slab->size - offset >= shader->code_size) {
 321                         shader->bo = slab->bo;
 322                         shader->bo_offset = offset;
 323                         list_addtail(&shader->slab_list, &slab->shaders);
 324                         mtx_unlock(&device->shader_slab_mutex);
 325                         return slab->ptr + offset;
 326                 }
 327         }
 328
 329         mtx_unlock(&device->shader_slab_mutex);
 330         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 331
 332         slab->size = 256 * 1024;
 333         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 334                                              RADEON_DOMAIN_VRAM,
 335                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 336                                              device->physical_device->cpdma_prefetch_writes_memory ?
 337                                                      0 : RADEON_FLAG_READ_ONLY);
 338         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 339         list_inithead(&slab->shaders);
 340
 341         mtx_lock(&device->shader_slab_mutex);
 342         list_add(&slab->slabs, &device->shader_slabs);
 343
 344         shader->bo = slab->bo;
 345         shader->bo_offset = 0;
 346         list_add(&shader->slab_list, &slab->shaders);
 347         mtx_unlock(&device->shader_slab_mutex);
 348         return slab->ptr;
 349 }
 350
 351 void
 352 radv_destroy_shader_slabs(struct radv_device *device)
 353 {
 354         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 355                 device->ws->buffer_destroy(slab->bo);
 356                 free(slab);
 357         }
 358         mtx_destroy(&device->shader_slab_mutex);
 359 }
 360
 361 static void
 362 radv_fill_shader_variant(struct radv_device *device,
 363                          struct radv_shader_variant *variant,
 364                          struct ac_shader_binary *binary,
 365                          gl_shader_stage stage)
 366 {
 367         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 368         unsigned vgpr_comp_cnt = 0;
 369
 370         if (scratch_enabled && !device->llvm_supports_spill)
 371                 radv_finishme("shader scratch support only available with LLVM 4.0");
 372
 373         variant->code_size = binary->code_size;
 374         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 375                         S_00B12C_SCRATCH_EN(scratch_enabled);
 376
 377         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 378                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 379                 S_00B848_DX10_CLAMP(1) |
 380                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 381
 382         switch (stage) {
 383         case MESA_SHADER_TESS_EVAL:
 384                 vgpr_comp_cnt = 3;
 385                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 386                 break;
 387         case MESA_SHADER_TESS_CTRL:
 388                 if (device->physical_device->rad_info.chip_class >= GFX9)
 389                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 390                 else
 391                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 392                 break;
 393         case MESA_SHADER_VERTEX:
 394         case MESA_SHADER_GEOMETRY:
 395                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 396                 break;
 397         case MESA_SHADER_FRAGMENT:
 398                 break;
 399         case MESA_SHADER_COMPUTE: {
 400                 struct ac_shader_info *info = &variant->info.info;
 401                 variant->rsrc2 |=
 402                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 403                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 404                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 405                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 406                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 407                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 408                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 409                 break;
 410         }
 411         default:
 412                 unreachable("unsupported shader type");
 413                 break;
 414         }
 415
 416         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 417             stage == MESA_SHADER_GEOMETRY) {
 418                 struct ac_shader_info *info = &variant->info.info;
 419                 unsigned es_type = variant->info.gs.es_type;
 420                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 421
 422                 if (es_type == MESA_SHADER_VERTEX) {
 423                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 424                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 425                         es_vgpr_comp_cnt = 3;
 426                 } else {
 427                         assert(!"invalid shader ES type");
 428                 }
 429
 430                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 431                  * VGPR[0:4] are always loaded.
 432                  */
 433                 if (info->uses_invocation_id)
 434                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 435                 else if (info->uses_prim_id)
 436                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 437                 else if (variant->info.gs.vertices_in >= 3)
 438                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 439                 else
 440                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 441
 442                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 443                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 444                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 445         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 446             stage == MESA_SHADER_TESS_CTRL)
 447                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 448         else
 449                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 450
 451         void *ptr = radv_alloc_shader_memory(device, variant);
 452         memcpy(ptr, binary->code, binary->code_size);
 453 }
 454
 455 static struct radv_shader_variant *
 456 shader_variant_create(struct radv_device *device,
 457                       struct radv_shader_module *module,
 458                       struct nir_shader * const *shaders,
 459                       int shader_count,
 460                       gl_shader_stage stage,
 461                       struct ac_nir_compiler_options *options,
 462                       bool gs_copy_shader,
 463                       void **code_out,
 464                       unsigned *code_size_out)
 465 {
 466         enum radeon_family chip_family = device->physical_device->rad_info.family;
 467         bool dump_shaders = radv_can_dump_shader(device, module);
 468         enum ac_target_machine_options tm_options = 0;
 469         struct radv_shader_variant *variant;
 470         struct ac_shader_binary binary;
 471         LLVMTargetMachineRef tm;
 472
 473         variant = calloc(1, sizeof(struct radv_shader_variant));
 474         if (!variant)
 475                 return NULL;
 476
 477         options->family = chip_family;
 478         options->chip_class = device->physical_device->rad_info.chip_class;
 479
 480         if (options->supports_spill)
 481                 tm_options |= AC_TM_SUPPORTS_SPILL;
 482         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 483                 tm_options |= AC_TM_SISCHED;
 484         tm = ac_create_target_machine(chip_family, tm_options);
 485
 486         if (gs_copy_shader) {
 487                 assert(shader_count == 1);
 488                 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
 489                                          &variant->info, options, dump_shaders);
 490         } else {
 491                 ac_compile_nir_shader(tm, &binary, &variant->config,
 492                                       &variant->info, shaders, shader_count, options,
 493                                       dump_shaders);
 494         }
 495
 496         LLVMDisposeTargetMachine(tm);
 497
 498         radv_fill_shader_variant(device, variant, &binary, stage);
 499
 500         if (code_out) {
 501                 *code_out = binary.code;
 502                 *code_size_out = binary.code_size;
 503         } else
 504                 free(binary.code);
 505         free(binary.config);
 506         free(binary.rodata);
 507         free(binary.global_symbol_offsets);
 508         free(binary.relocs);
 509         variant->ref_count = 1;
 510
 511         if (device->keep_shader_info) {
 512                 variant->disasm_string = binary.disasm_string;
 513                 if (!gs_copy_shader && !module->nir) {
 514                         variant->nir = *shaders;
 515                         variant->spirv = (uint32_t *)module->data;
 516                         variant->spirv_size = module->size;
 517                 }
 518         } else {
 519                 free(binary.disasm_string);
 520         }
 521
 522         return variant;
 523 }
 524
 525 struct radv_shader_variant *
 526 radv_shader_variant_create(struct radv_device *device,
 527                            struct radv_shader_module *module,
 528                            struct nir_shader *const *shaders,
 529                            int shader_count,
 530                            struct radv_pipeline_layout *layout,
 531                            const struct ac_shader_variant_key *key,
 532                            void **code_out,
 533                            unsigned *code_size_out)
 534 {
 535         struct ac_nir_compiler_options options = {0};
 536
 537         options.layout = layout;
 538         if (key)
 539                 options.key = *key;
 540
 541         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 542         options.supports_spill = device->llvm_supports_spill;
 543
 544         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 545                                      &options, false, code_out, code_size_out);
 546 }
 547
 548 struct radv_shader_variant *
 549 radv_create_gs_copy_shader(struct radv_device *device,
 550                            struct nir_shader *shader,
 551                            void **code_out,
 552                            unsigned *code_size_out,
 553                            bool multiview)
 554 {
 555         struct ac_nir_compiler_options options = {0};
 556
 557         options.key.has_multiview_view_index = multiview;
 558
 559         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 560                                      &options, true, code_out, code_size_out);
 561 }
 562
 563 void
 564 radv_shader_variant_destroy(struct radv_device *device,
 565                             struct radv_shader_variant *variant)
 566 {
 567         if (!p_atomic_dec_zero(&variant->ref_count))
 568                 return;
 569
 570         mtx_lock(&device->shader_slab_mutex);
 571         list_del(&variant->slab_list);
 572         mtx_unlock(&device->shader_slab_mutex);
 573
 574         ralloc_free(variant->nir);
 575         free(variant->disasm_string);
 576         free(variant);
 577 }
 578
 579 const char *
 580 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 581 {
 582         switch (stage) {
 583         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 584         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 585         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 586         case MESA_SHADER_COMPUTE: return "Compute Shader";
 587         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 588         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 589         default:
 590                 return "Unknown shader";
 591         };
 592 }
 593
 594 static uint32_t
 595 get_total_sgprs(struct radv_device *device)
 596 {
 597         if (device->physical_device->rad_info.chip_class >= VI)
 598                 return 800;
 599         else
 600                 return 512;
 601 }
 602
 603 static void
 604 generate_shader_stats(struct radv_device *device,
 605                       struct radv_shader_variant *variant,
 606                       gl_shader_stage stage,
 607                       struct _mesa_string_buffer *buf)
 608 {
 609         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 610         struct ac_shader_config *conf;
 611         unsigned max_simd_waves;
 612         unsigned lds_per_wave = 0;
 613
 614         switch (device->physical_device->rad_info.family) {
 615         /* These always have 8 waves: */
 616         case CHIP_POLARIS10:
 617         case CHIP_POLARIS11:
 618         case CHIP_POLARIS12:
 619                 max_simd_waves = 8;
 620                 break;
 621         default:
 622                 max_simd_waves = 10;
 623         }
 624
 625         conf = &variant->config;
 626
 627         if (stage == MESA_SHADER_FRAGMENT) {
 628                 lds_per_wave = conf->lds_size * lds_increment +
 629                                align(variant->info.fs.num_interp * 48,
 630                                      lds_increment);
 631         }
 632
 633         if (conf->num_sgprs)
 634                 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
 635
 636         if (conf->num_vgprs)
 637                 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 638
 639         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 640          * that PS can use.
 641          */
 642         if (lds_per_wave)
 643                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 644
 645         if (stage == MESA_SHADER_FRAGMENT) {
 646                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 647                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 648                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 649                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 650         }
 651
 652         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 653                                    "SGPRS: %d\n"
 654                                    "VGPRS: %d\n"
 655                                    "Spilled SGPRs: %d\n"
 656                                    "Spilled VGPRs: %d\n"
 657                                    "Code Size: %d bytes\n"
 658                                    "LDS: %d blocks\n"
 659                                    "Scratch: %d bytes per wave\n"
 660                                    "Max Waves: %d\n"
 661                                    "********************\n\n\n",
 662                                    conf->num_sgprs, conf->num_vgprs,
 663                                    conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
 664                                    conf->lds_size, conf->scratch_bytes_per_wave,
 665                                    max_simd_waves);
 666 }
 667
 668 void
 669 radv_shader_dump_stats(struct radv_device *device,
 670                        struct radv_shader_variant *variant,
 671                        gl_shader_stage stage,
 672                        FILE *file)
 673 {
 674         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 675
 676         generate_shader_stats(device, variant, stage, buf);
 677
 678         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 679         fprintf(file, "%s", buf->buf);
 680
 681         _mesa_string_buffer_destroy(buf);
 682 }
 683
 684 VkResult
 685 radv_GetShaderInfoAMD(VkDevice _device,
 686                       VkPipeline _pipeline,
 687                       VkShaderStageFlagBits shaderStage,
 688                       VkShaderInfoTypeAMD infoType,
 689                       size_t* pInfoSize,
 690                       void* pInfo)
 691 {
 692         RADV_FROM_HANDLE(radv_device, device, _device);
 693         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 694         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 695         struct radv_shader_variant *variant = pipeline->shaders[stage];
 696         struct _mesa_string_buffer *buf;
 697         VkResult result = VK_SUCCESS;
 698
 699         /* Spec doesn't indicate what to do if the stage is invalid, so just
 700          * return no info for this. */
 701         if (!variant)
 702                 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
 703
 704         switch (infoType) {
 705         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 706                 if (!pInfo) {
 707                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 708                 } else {
 709                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 710                         struct ac_shader_config *conf = &variant->config;
 711
 712                         VkShaderStatisticsInfoAMD statistics = {};
 713                         statistics.shaderStageMask = shaderStage;
 714                         statistics.numPhysicalVgprs = 256;
 715                         statistics.numPhysicalSgprs = get_total_sgprs(device);
 716                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 717
 718                         if (stage == MESA_SHADER_COMPUTE) {
 719                                 unsigned *local_size = variant->nir->info.cs.local_size;
 720                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 721
 722                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 723                                                                ceil(workgroup_size / statistics.numPhysicalVgprs);
 724
 725                                 statistics.computeWorkGroupSize[0] = local_size[0];
 726                                 statistics.computeWorkGroupSize[1] = local_size[1];
 727                                 statistics.computeWorkGroupSize[2] = local_size[2];
 728                         } else {
 729                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 730                         }
 731
 732                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 733                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 734                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 735                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 736                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 737
 738                         size_t size = *pInfoSize;
 739                         *pInfoSize = sizeof(statistics);
 740
 741                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 742
 743                         if (size < *pInfoSize)
 744                                 result = VK_INCOMPLETE;
 745                 }
 746
 747                 break;
 748         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 749                 buf = _mesa_string_buffer_create(NULL, 1024);
 750
 751                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 752                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 753                 generate_shader_stats(device, variant, stage, buf);
 754
 755                 /* Need to include the null terminator. */
 756                 size_t length = buf->length + 1;
 757
 758                 if (!pInfo) {
 759                         *pInfoSize = length;
 760                 } else {
 761                         size_t size = *pInfoSize;
 762                         *pInfoSize = length;
 763
 764                         memcpy(pInfo, buf->buf, MIN2(size, length));
 765
 766                         if (size < length)
 767                                 result = VK_INCOMPLETE;
 768                 }
 769
 770                 _mesa_string_buffer_destroy(buf);
 771                 break;
 772         default:
 773                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 774                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 775                 break;
 776         }
 777
 778         return result;
 779 }