2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_debug.h"
32 #include "radv_private.h"
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
49 struct radv_shader_module
{
50 struct nir_shader
*nir
;
51 unsigned char sha1
[20];
56 struct radv_vs_variant_key
{
57 uint32_t instance_rate_inputs
;
60 uint32_t export_prim_id
:1;
63 struct radv_tes_variant_key
{
65 uint32_t export_prim_id
:1;
68 struct radv_tcs_variant_key
{
69 struct radv_vs_variant_key vs_key
;
70 unsigned primitive_mode
;
71 unsigned input_vertices
;
72 uint32_t tes_reads_tess_factors
:1;
75 struct radv_fs_variant_key
{
77 uint8_t log2_ps_iter_samples
;
78 uint8_t log2_num_samples
;
81 uint32_t multisample
: 1;
84 struct radv_shader_variant_key
{
86 struct radv_vs_variant_key vs
;
87 struct radv_fs_variant_key fs
;
88 struct radv_tes_variant_key tes
;
89 struct radv_tcs_variant_key tcs
;
91 bool has_multiview_view_index
;
94 struct radv_nir_compiler_options
{
95 struct radv_pipeline_layout
*layout
;
96 struct radv_shader_variant_key key
;
99 bool clamp_shadow_reference
;
103 enum radeon_family family
;
104 enum chip_class chip_class
;
108 AC_UD_SCRATCH_RING_OFFSETS
= 0,
109 AC_UD_PUSH_CONSTANTS
= 1,
110 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 2,
111 AC_UD_VIEW_INDEX
= 3,
112 AC_UD_SHADER_START
= 4,
113 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
114 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
115 AC_UD_VS_LS_TCS_IN_LAYOUT
,
117 AC_UD_PS_SAMPLE_POS_OFFSET
= AC_UD_SHADER_START
,
119 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
121 AC_UD_GS_VS_RING_STRIDE_ENTRIES
= AC_UD_VS_MAX_UD
,
123 AC_UD_TCS_OFFCHIP_LAYOUT
= AC_UD_VS_MAX_UD
,
125 AC_UD_TES_OFFCHIP_LAYOUT
= AC_UD_SHADER_START
,
127 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
129 struct radv_shader_info
{
130 bool loads_push_constants
;
131 uint32_t desc_set_used_mask
;
132 bool needs_multiview_view_index
;
133 bool uses_invocation_id
;
136 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
137 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
138 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
140 bool needs_instance_id
;
143 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
146 bool force_persample
;
147 bool needs_sample_positions
;
148 bool uses_input_attachments
;
152 bool writes_sample_mask
;
159 bool uses_block_id
[3];
160 bool uses_thread_id
[3];
161 bool uses_local_invocation_idx
;
165 struct radv_userdata_info
{
169 uint32_t indirect_offset
;
172 struct radv_userdata_locations
{
173 struct radv_userdata_info descriptor_sets
[RADV_UD_MAX_SETS
];
174 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
177 struct radv_vs_output_info
{
178 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
179 uint8_t clip_dist_mask
;
180 uint8_t cull_dist_mask
;
181 uint8_t param_exports
;
182 bool writes_pointsize
;
184 bool writes_viewport_index
;
186 unsigned pos_exports
;
189 struct radv_es_output_info
{
190 uint32_t esgs_itemsize
;
193 struct radv_shader_variant_info
{
194 struct radv_userdata_locations user_sgprs_locs
;
195 struct radv_shader_info info
;
196 unsigned num_user_sgprs
;
197 unsigned num_input_sgprs
;
198 unsigned num_input_vgprs
;
199 unsigned private_mem_vgprs
;
200 bool need_indirect_descriptor_sets
;
203 struct radv_vs_output_info outinfo
;
204 struct radv_es_output_info es_info
;
205 unsigned vgpr_comp_cnt
;
208 uint64_t outputs_written
;
213 uint32_t flat_shaded_mask
;
215 bool early_fragment_test
;
218 unsigned block_size
[3];
221 unsigned vertices_in
;
222 unsigned vertices_out
;
223 unsigned output_prim
;
224 unsigned invocations
;
225 unsigned gsvs_vertex_size
;
226 unsigned max_gsvs_emit_size
;
227 unsigned es_type
; /* GFX9: VS or TES */
230 unsigned tcs_vertices_out
;
231 /* Which outputs are actually written */
232 uint64_t outputs_written
;
233 /* Which patch outputs are actually written */
234 uint32_t patch_outputs_written
;
238 struct radv_vs_output_info outinfo
;
239 struct radv_es_output_info es_info
;
241 unsigned primitive_mode
;
242 enum gl_tess_spacing spacing
;
249 struct radv_shader_variant
{
252 struct radeon_winsys_bo
*bo
;
254 struct ac_shader_config config
;
256 struct radv_shader_variant_info info
;
263 struct nir_shader
*nir
;
265 char *llvm_ir_string
;
267 struct list_head slab_list
;
270 struct radv_shader_slab
{
271 struct list_head slabs
;
272 struct list_head shaders
;
273 struct radeon_winsys_bo
*bo
;
279 radv_optimize_nir(struct nir_shader
*shader
);
282 radv_shader_compile_to_nir(struct radv_device
*device
,
283 struct radv_shader_module
*module
,
284 const char *entrypoint_name
,
285 gl_shader_stage stage
,
286 const VkSpecializationInfo
*spec_info
);
289 radv_alloc_shader_memory(struct radv_device
*device
,
290 struct radv_shader_variant
*shader
);
293 radv_destroy_shader_slabs(struct radv_device
*device
);
295 struct radv_shader_variant
*
296 radv_shader_variant_create(struct radv_device
*device
,
297 struct radv_shader_module
*module
,
298 struct nir_shader
*const *shaders
,
300 struct radv_pipeline_layout
*layout
,
301 const struct radv_shader_variant_key
*key
,
303 unsigned *code_size_out
);
305 struct radv_shader_variant
*
306 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
307 void **code_out
, unsigned *code_size_out
,
311 radv_shader_variant_destroy(struct radv_device
*device
,
312 struct radv_shader_variant
*variant
);
315 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
);
318 radv_shader_dump_stats(struct radv_device
*device
,
319 struct radv_shader_variant
*variant
,
320 gl_shader_stage stage
,
324 radv_can_dump_shader(struct radv_device
*device
,
325 struct radv_shader_module
*module
)
327 /* Only dump non-meta shaders, useful for debugging purposes. */
328 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
&&
329 module
&& !module
->nir
;
333 radv_can_dump_shader_stats(struct radv_device
*device
,
334 struct radv_shader_module
*module
)
336 /* Only dump non-meta shader stats. */
337 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
338 module
&& !module
->nir
;
341 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot
)
343 /* handle patch indices separate */
344 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
346 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
348 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
349 return 2 + (slot
- VARYING_SLOT_PATCH0
);
350 if (slot
== VARYING_SLOT_POS
)
352 if (slot
== VARYING_SLOT_PSIZ
)
354 if (slot
== VARYING_SLOT_CLIP_DIST0
)
356 /* 3 is reserved for clip dist as well */
357 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
358 return 4 + (slot
- VARYING_SLOT_VAR0
);
359 unreachable("illegal slot in get unique index\n");