2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
40 struct radv_shader_module
{
41 struct nir_shader
*nir
;
42 unsigned char sha1
[20];
48 RADV_ALPHA_ADJUST_NONE
= 0,
49 RADV_ALPHA_ADJUST_SNORM
= 1,
50 RADV_ALPHA_ADJUST_SINT
= 2,
51 RADV_ALPHA_ADJUST_SSCALED
= 3,
54 struct radv_vs_out_key
{
58 uint32_t as_ngg_passthrough
:1;
59 uint32_t export_prim_id
:1;
60 uint32_t export_layer_id
:1;
61 uint32_t export_clip_dists
:1;
64 struct radv_vs_variant_key
{
65 struct radv_vs_out_key out
;
67 uint32_t instance_rate_inputs
;
68 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
69 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
70 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
72 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
74 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
75 * so we may need to fix it up. */
76 uint64_t alpha_adjust
;
78 /* For some formats the channels have to be shuffled. */
79 uint32_t post_shuffle
;
81 /* Output primitive type. */
85 struct radv_tes_variant_key
{
86 struct radv_vs_out_key out
;
89 uint8_t tcs_num_outputs
;
92 struct radv_tcs_variant_key
{
93 struct radv_vs_variant_key vs_key
;
94 unsigned primitive_mode
;
95 unsigned input_vertices
;
97 uint32_t tes_reads_tess_factors
:1;
100 struct radv_fs_variant_key
{
102 uint8_t log2_ps_iter_samples
;
108 struct radv_cs_variant_key
{
109 uint8_t subgroup_size
;
112 struct radv_shader_variant_key
{
114 struct radv_vs_variant_key vs
;
115 struct radv_fs_variant_key fs
;
116 struct radv_tes_variant_key tes
;
117 struct radv_tcs_variant_key tcs
;
118 struct radv_cs_variant_key cs
;
120 /* A common prefix of the vs and tes keys. */
121 struct radv_vs_out_key vs_common_out
;
123 bool has_multiview_view_index
;
126 struct radv_nir_compiler_options
{
127 struct radv_pipeline_layout
*layout
;
128 struct radv_shader_variant_key key
;
129 bool explicit_scratch_args
;
130 bool clamp_shadow_reference
;
131 bool robust_buffer_access
;
136 bool has_ls_vgpr_init_bug
;
137 bool use_ngg_streamout
;
138 enum radeon_family family
;
139 enum chip_class chip_class
;
140 uint32_t tess_offchip_block_dw_size
;
141 uint32_t address32_hi
;
145 AC_UD_SCRATCH_RING_OFFSETS
= 0,
146 AC_UD_PUSH_CONSTANTS
= 1,
147 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
148 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
149 AC_UD_VIEW_INDEX
= 4,
150 AC_UD_STREAMOUT_BUFFERS
= 5,
151 AC_UD_NGG_GS_STATE
= 6,
152 AC_UD_SHADER_START
= 7,
153 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
154 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
157 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
162 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
165 struct radv_stream_output
{
169 uint8_t component_mask
;
173 struct radv_streamout_info
{
174 uint16_t num_outputs
;
175 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
176 uint16_t strides
[MAX_SO_BUFFERS
];
177 uint32_t enabled_stream_buffers_mask
;
180 struct radv_userdata_info
{
185 struct radv_userdata_locations
{
186 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
187 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
188 uint32_t descriptor_sets_enabled
;
191 struct radv_vs_output_info
{
192 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
193 uint8_t clip_dist_mask
;
194 uint8_t cull_dist_mask
;
195 uint8_t param_exports
;
196 bool writes_pointsize
;
198 bool writes_viewport_index
;
200 unsigned pos_exports
;
203 struct radv_es_output_info
{
204 uint32_t esgs_itemsize
;
207 struct gfx9_gs_info
{
208 uint32_t vgt_gs_onchip_cntl
;
209 uint32_t vgt_gs_max_prims_per_subgroup
;
210 uint32_t vgt_esgs_ring_itemsize
;
214 struct gfx10_ngg_info
{
215 uint16_t ngg_emit_size
; /* in dwords */
216 uint32_t hw_max_esverts
;
217 uint32_t max_gsprims
;
218 uint32_t max_out_verts
;
219 uint32_t prim_amp_factor
;
220 uint32_t vgt_esgs_ring_itemsize
;
221 uint32_t esgs_ring_size
;
222 bool max_vert_out_per_gs_instance
;
225 struct radv_shader_info
{
226 bool loads_push_constants
;
227 bool loads_dynamic_offsets
;
228 uint8_t min_push_constant_used
;
229 uint8_t max_push_constant_used
;
230 bool has_only_32bit_push_constants
;
231 bool has_indirect_push_constants
;
232 uint8_t num_inline_push_consts
;
233 uint8_t base_inline_push_consts
;
234 uint32_t desc_set_used_mask
;
235 bool needs_multiview_view_index
;
236 bool uses_invocation_id
;
239 struct radv_userdata_locations user_sgprs_locs
;
240 unsigned num_user_sgprs
;
241 unsigned num_input_sgprs
;
242 unsigned num_input_vgprs
;
243 unsigned private_mem_vgprs
;
244 bool need_indirect_descriptor_sets
;
246 bool is_ngg_passthrough
;
248 uint64_t ls_outputs_written
;
249 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
250 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
251 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
253 bool needs_instance_id
;
254 struct radv_vs_output_info outinfo
;
255 struct radv_es_output_info es_info
;
261 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
262 uint8_t num_stream_output_components
[4];
263 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
266 unsigned gsvs_vertex_size
;
267 unsigned max_gsvs_emit_size
;
268 unsigned vertices_in
;
269 unsigned vertices_out
;
270 unsigned output_prim
;
271 unsigned invocations
;
272 unsigned es_type
; /* GFX9: VS or TES */
275 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
276 struct radv_vs_output_info outinfo
;
277 struct radv_es_output_info es_info
;
279 unsigned primitive_mode
;
280 enum gl_tess_spacing spacing
;
286 bool force_persample
;
287 bool needs_sample_positions
;
291 bool writes_sample_mask
;
295 uint8_t num_input_clips_culls
;
297 uint32_t flat_shaded_mask
;
298 uint32_t explicit_shaded_mask
;
299 uint32_t float16_shaded_mask
;
302 bool early_fragment_test
;
303 bool post_depth_coverage
;
307 bool uses_block_id
[3];
308 bool uses_thread_id
[3];
309 bool uses_local_invocation_idx
;
310 unsigned block_size
[3];
313 uint64_t outputs_written
;
314 uint64_t patch_outputs_written
;
315 unsigned tcs_vertices_out
;
316 uint32_t num_patches
;
320 struct radv_streamout_info so
;
322 struct gfx9_gs_info gs_ring_info
;
323 struct gfx10_ngg_info ngg_info
;
325 unsigned float_controls_mode
;
328 enum radv_shader_binary_type
{
329 RADV_BINARY_TYPE_LEGACY
,
330 RADV_BINARY_TYPE_RTLD
333 struct radv_shader_binary
{
334 enum radv_shader_binary_type type
;
335 gl_shader_stage stage
;
336 bool is_gs_copy_shader
;
338 struct radv_shader_info info
;
340 /* Self-referential size so we avoid consistency issues. */
344 struct radv_shader_binary_legacy
{
345 struct radv_shader_binary base
;
346 struct ac_shader_config config
;
350 unsigned disasm_size
;
352 /* data has size of code_size + ir_size + disasm_size + 2, where
353 * the +2 is for 0 of the ir strings. */
357 struct radv_shader_binary_rtld
{
358 struct radv_shader_binary base
;
360 unsigned llvm_ir_size
;
364 struct radv_shader_variant
{
367 struct radeon_winsys_bo
*bo
;
369 struct ac_shader_config config
;
372 struct radv_shader_info info
;
382 struct list_head slab_list
;
385 struct radv_shader_slab
{
386 struct list_head slabs
;
387 struct list_head shaders
;
388 struct radeon_winsys_bo
*bo
;
394 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
397 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
398 const struct radv_pipeline_layout
*layout
);
401 radv_shader_compile_to_nir(struct radv_device
*device
,
402 struct radv_shader_module
*module
,
403 const char *entrypoint_name
,
404 gl_shader_stage stage
,
405 const VkSpecializationInfo
*spec_info
,
406 const VkPipelineCreateFlags flags
,
407 const struct radv_pipeline_layout
*layout
,
411 radv_alloc_shader_memory(struct radv_device
*device
,
412 struct radv_shader_variant
*shader
);
415 radv_destroy_shader_slabs(struct radv_device
*device
);
418 radv_create_shaders(struct radv_pipeline
*pipeline
,
419 struct radv_device
*device
,
420 struct radv_pipeline_cache
*cache
,
421 const struct radv_pipeline_key
*key
,
422 const VkPipelineShaderStageCreateInfo
**pStages
,
423 const VkPipelineCreateFlags flags
,
424 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
425 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
427 struct radv_shader_variant
*
428 radv_shader_variant_create(struct radv_device
*device
,
429 const struct radv_shader_binary
*binary
,
430 bool keep_shader_info
);
431 struct radv_shader_variant
*
432 radv_shader_variant_compile(struct radv_device
*device
,
433 struct radv_shader_module
*module
,
434 struct nir_shader
*const *shaders
,
436 struct radv_pipeline_layout
*layout
,
437 const struct radv_shader_variant_key
*key
,
438 struct radv_shader_info
*info
,
439 bool keep_shader_info
,
441 struct radv_shader_binary
**binary_out
);
443 struct radv_shader_variant
*
444 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
445 struct radv_shader_info
*info
,
446 struct radv_shader_binary
**binary_out
,
447 bool multiview
, bool keep_shader_info
,
451 radv_shader_variant_destroy(struct radv_device
*device
,
452 struct radv_shader_variant
*variant
);
456 radv_get_max_waves(struct radv_device
*device
,
457 struct radv_shader_variant
*variant
,
458 gl_shader_stage stage
);
461 radv_get_max_workgroup_size(enum chip_class chip_class
,
462 gl_shader_stage stage
,
463 const unsigned *sizes
);
466 radv_get_shader_name(struct radv_shader_info
*info
,
467 gl_shader_stage stage
);
470 radv_shader_dump_stats(struct radv_device
*device
,
471 struct radv_shader_variant
*variant
,
472 gl_shader_stage stage
,
476 radv_can_dump_shader(struct radv_device
*device
,
477 struct radv_shader_module
*module
,
478 bool is_gs_copy_shader
);
481 radv_can_dump_shader_stats(struct radv_device
*device
,
482 struct radv_shader_module
*module
);
484 static inline unsigned
485 shader_io_get_unique_index(gl_varying_slot slot
)
487 /* handle patch indices separate */
488 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
490 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
492 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
493 return 2 + (slot
- VARYING_SLOT_PATCH0
);
494 if (slot
== VARYING_SLOT_POS
)
496 if (slot
== VARYING_SLOT_PSIZ
)
498 if (slot
== VARYING_SLOT_CLIP_DIST0
)
500 if (slot
== VARYING_SLOT_CLIP_DIST1
)
502 /* 3 is reserved for clip dist as well */
503 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
504 return 4 + (slot
- VARYING_SLOT_VAR0
);
505 unreachable("illegal slot in get unique index\n");
509 radv_lower_fs_io(nir_shader
*nir
);