src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 struct radv_shader_module {
  50         struct nir_shader *nir;
  51         unsigned char sha1[20];
  52         uint32_t size;
  53         char data[0];
  54 };
  55
  56 struct radv_vs_variant_key {
  57         uint32_t instance_rate_inputs;
  58         uint32_t as_es:1;
  59         uint32_t as_ls:1;
  60         uint32_t export_prim_id:1;
  61 };
  62
  63 struct radv_tes_variant_key {
  64         uint32_t as_es:1;
  65         uint32_t export_prim_id:1;
  66 };
  67
  68 struct radv_tcs_variant_key {
  69         struct radv_vs_variant_key vs_key;
  70         unsigned primitive_mode;
  71         unsigned input_vertices;
  72         unsigned num_inputs;
  73         uint32_t tes_reads_tess_factors:1;
  74 };
  75
  76 struct radv_fs_variant_key {
  77         uint32_t col_format;
  78         uint8_t log2_ps_iter_samples;
  79         uint8_t log2_num_samples;
  80         uint32_t is_int8;
  81         uint32_t is_int10;
  82         uint32_t multisample : 1;
  83 };
  84
  85 struct radv_shader_variant_key {
  86         union {
  87                 struct radv_vs_variant_key vs;
  88                 struct radv_fs_variant_key fs;
  89                 struct radv_tes_variant_key tes;
  90                 struct radv_tcs_variant_key tcs;
  91         };
  92         bool has_multiview_view_index;
  93 };
  94
  95 struct radv_nir_compiler_options {
  96         struct radv_pipeline_layout *layout;
  97         struct radv_shader_variant_key key;
  98         bool unsafe_math;
  99         bool supports_spill;
 100         bool clamp_shadow_reference;
 101         bool dump_shader;
 102         bool dump_preoptir;
 103         bool record_llvm_ir;
 104         enum radeon_family family;
 105         enum chip_class chip_class;
 106 };
 107
 108 enum radv_ud_index {
 109         AC_UD_SCRATCH_RING_OFFSETS = 0,
 110         AC_UD_PUSH_CONSTANTS = 1,
 111         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
 112         AC_UD_VIEW_INDEX = 3,
 113         AC_UD_SHADER_START = 4,
 114         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 115         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 116         AC_UD_VS_MAX_UD,
 117         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 118         AC_UD_PS_MAX_UD,
 119         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 120         AC_UD_CS_MAX_UD,
 121         AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
 122         AC_UD_GS_MAX_UD,
 123         AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
 124         AC_UD_TCS_MAX_UD,
 125         AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
 126         AC_UD_TES_MAX_UD,
 127         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 128 };
 129 struct radv_shader_info {
 130         bool loads_push_constants;
 131         uint32_t desc_set_used_mask;
 132         bool needs_multiview_view_index;
 133         bool uses_invocation_id;
 134         bool uses_prim_id;
 135         struct {
 136                 uint64_t ls_outputs_written;
 137                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 138                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 139                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 140                 bool needs_draw_id;
 141                 bool needs_instance_id;
 142         } vs;
 143         struct {
 144                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 145         } tes;
 146         struct {
 147                 bool force_persample;
 148                 bool needs_sample_positions;
 149                 bool uses_input_attachments;
 150                 bool writes_memory;
 151                 bool writes_z;
 152                 bool writes_stencil;
 153                 bool writes_sample_mask;
 154                 bool has_pcoord;
 155                 bool prim_id_input;
 156                 bool layer_input;
 157         } ps;
 158         struct {
 159                 bool uses_grid_size;
 160                 bool uses_block_id[3];
 161                 bool uses_thread_id[3];
 162                 bool uses_local_invocation_idx;
 163         } cs;
 164         struct {
 165                 uint64_t outputs_written;
 166                 uint64_t patch_outputs_written;
 167         } tcs;
 168 };
 169
 170 struct radv_userdata_info {
 171         int8_t sgpr_idx;
 172         uint8_t num_sgprs;
 173         bool indirect;
 174         uint32_t indirect_offset;
 175 };
 176
 177 struct radv_userdata_locations {
 178         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 179         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 180 };
 181
 182 struct radv_vs_output_info {
 183         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 184         uint8_t clip_dist_mask;
 185         uint8_t cull_dist_mask;
 186         uint8_t param_exports;
 187         bool writes_pointsize;
 188         bool writes_layer;
 189         bool writes_viewport_index;
 190         bool export_prim_id;
 191         unsigned pos_exports;
 192 };
 193
 194 struct radv_es_output_info {
 195         uint32_t esgs_itemsize;
 196 };
 197
 198 struct radv_shader_variant_info {
 199         struct radv_userdata_locations user_sgprs_locs;
 200         struct radv_shader_info info;
 201         unsigned num_user_sgprs;
 202         unsigned num_input_sgprs;
 203         unsigned num_input_vgprs;
 204         unsigned private_mem_vgprs;
 205         bool need_indirect_descriptor_sets;
 206         struct {
 207                 struct {
 208                         struct radv_vs_output_info outinfo;
 209                         struct radv_es_output_info es_info;
 210                         unsigned vgpr_comp_cnt;
 211                         bool as_es;
 212                         bool as_ls;
 213                         uint64_t outputs_written;
 214                 } vs;
 215                 struct {
 216                         unsigned num_interp;
 217                         uint32_t input_mask;
 218                         uint32_t flat_shaded_mask;
 219                         bool can_discard;
 220                         bool early_fragment_test;
 221                 } fs;
 222                 struct {
 223                         unsigned block_size[3];
 224                 } cs;
 225                 struct {
 226                         unsigned vertices_in;
 227                         unsigned vertices_out;
 228                         unsigned output_prim;
 229                         unsigned invocations;
 230                         unsigned gsvs_vertex_size;
 231                         unsigned max_gsvs_emit_size;
 232                         unsigned es_type; /* GFX9: VS or TES */
 233                 } gs;
 234                 struct {
 235                         unsigned tcs_vertices_out;
 236                         /* Which outputs are actually written */
 237                         uint64_t outputs_written;
 238                         /* Which patch outputs are actually written */
 239                         uint32_t patch_outputs_written;
 240
 241                 } tcs;
 242                 struct {
 243                         struct radv_vs_output_info outinfo;
 244                         struct radv_es_output_info es_info;
 245                         bool as_es;
 246                         unsigned primitive_mode;
 247                         enum gl_tess_spacing spacing;
 248                         bool ccw;
 249                         bool point_mode;
 250                 } tes;
 251         };
 252 };
 253
 254 struct radv_shader_variant {
 255         uint32_t ref_count;
 256
 257         struct radeon_winsys_bo *bo;
 258         uint64_t bo_offset;
 259         struct ac_shader_config config;
 260         uint32_t code_size;
 261         struct radv_shader_variant_info info;
 262         unsigned rsrc1;
 263         unsigned rsrc2;
 264
 265         /* debug only */
 266         uint32_t *spirv;
 267         uint32_t spirv_size;
 268         struct nir_shader *nir;
 269         char *disasm_string;
 270         char *llvm_ir_string;
 271
 272         struct list_head slab_list;
 273 };
 274
 275 struct radv_shader_slab {
 276         struct list_head slabs;
 277         struct list_head shaders;
 278         struct radeon_winsys_bo *bo;
 279         uint64_t size;
 280         char *ptr;
 281 };
 282
 283 void
 284 radv_optimize_nir(struct nir_shader *shader);
 285
 286 nir_shader *
 287 radv_shader_compile_to_nir(struct radv_device *device,
 288                            struct radv_shader_module *module,
 289                            const char *entrypoint_name,
 290                            gl_shader_stage stage,
 291                            const VkSpecializationInfo *spec_info);
 292
 293 void *
 294 radv_alloc_shader_memory(struct radv_device *device,
 295                           struct radv_shader_variant *shader);
 296
 297 void
 298 radv_destroy_shader_slabs(struct radv_device *device);
 299
 300 struct radv_shader_variant *
 301 radv_shader_variant_create(struct radv_device *device,
 302                            struct radv_shader_module *module,
 303                            struct nir_shader *const *shaders,
 304                            int shader_count,
 305                            struct radv_pipeline_layout *layout,
 306                            const struct radv_shader_variant_key *key,
 307                            void **code_out,
 308                            unsigned *code_size_out);
 309
 310 struct radv_shader_variant *
 311 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 312                            void **code_out, unsigned *code_size_out,
 313                            bool multiview);
 314
 315 void
 316 radv_shader_variant_destroy(struct radv_device *device,
 317                             struct radv_shader_variant *variant);
 318
 319 const char *
 320 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 321
 322 void
 323 radv_shader_dump_stats(struct radv_device *device,
 324                        struct radv_shader_variant *variant,
 325                        gl_shader_stage stage,
 326                        FILE *file);
 327
 328 static inline bool
 329 radv_can_dump_shader(struct radv_device *device,
 330                      struct radv_shader_module *module)
 331 {
 332         /* Only dump non-meta shaders, useful for debugging purposes. */
 333         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
 334                module && !module->nir;
 335 }
 336
 337 static inline bool
 338 radv_can_dump_shader_stats(struct radv_device *device,
 339                            struct radv_shader_module *module)
 340 {
 341         /* Only dump non-meta shader stats. */
 342         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 343                module && !module->nir;
 344 }
 345
 346 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 347 {
 348         /* handle patch indices separate */
 349         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 350                 return 0;
 351         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 352                 return 1;
 353         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 354                 return 2 + (slot - VARYING_SLOT_PATCH0);
 355         if (slot == VARYING_SLOT_POS)
 356                 return 0;
 357         if (slot == VARYING_SLOT_PSIZ)
 358                 return 1;
 359         if (slot == VARYING_SLOT_CLIP_DIST0)
 360                 return 2;
 361         /* 3 is reserved for clip dist as well */
 362         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 363                 return 4 + (slot - VARYING_SLOT_VAR0);
 364         unreachable("illegal slot in get unique index\n");
 365 }
 366
 367 #endif