src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 struct radv_shader_module {
  50         struct nir_shader *nir;
  51         unsigned char sha1[20];
  52         uint32_t size;
  53         char data[0];
  54 };
  55
  56 struct radv_vs_variant_key {
  57         uint32_t instance_rate_inputs;
  58         uint32_t as_es:1;
  59         uint32_t as_ls:1;
  60         uint32_t export_prim_id:1;
  61 };
  62
  63 struct radv_tes_variant_key {
  64         uint32_t as_es:1;
  65         uint32_t export_prim_id:1;
  66         uint32_t num_patches;
  67 };
  68
  69 struct radv_tcs_variant_key {
  70         struct radv_vs_variant_key vs_key;
  71         unsigned primitive_mode;
  72         unsigned input_vertices;
  73         unsigned num_inputs;
  74         uint32_t tes_reads_tess_factors:1;
  75 };
  76
  77 struct radv_fs_variant_key {
  78         uint32_t col_format;
  79         uint8_t log2_ps_iter_samples;
  80         uint8_t log2_num_samples;
  81         uint32_t is_int8;
  82         uint32_t is_int10;
  83         uint32_t multisample : 1;
  84 };
  85
  86 struct radv_shader_variant_key {
  87         union {
  88                 struct radv_vs_variant_key vs;
  89                 struct radv_fs_variant_key fs;
  90                 struct radv_tes_variant_key tes;
  91                 struct radv_tcs_variant_key tcs;
  92         };
  93         bool has_multiview_view_index;
  94 };
  95
  96 struct radv_nir_compiler_options {
  97         struct radv_pipeline_layout *layout;
  98         struct radv_shader_variant_key key;
  99         bool unsafe_math;
 100         bool supports_spill;
 101         bool clamp_shadow_reference;
 102         bool dump_shader;
 103         bool dump_preoptir;
 104         bool record_llvm_ir;
 105         enum radeon_family family;
 106         enum chip_class chip_class;
 107         uint32_t tess_offchip_block_dw_size;
 108 };
 109
 110 enum radv_ud_index {
 111         AC_UD_SCRATCH_RING_OFFSETS = 0,
 112         AC_UD_PUSH_CONSTANTS = 1,
 113         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
 114         AC_UD_VIEW_INDEX = 3,
 115         AC_UD_SHADER_START = 4,
 116         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 117         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 118         AC_UD_VS_MAX_UD,
 119         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 120         AC_UD_PS_MAX_UD,
 121         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 122         AC_UD_CS_MAX_UD,
 123         AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
 124         AC_UD_GS_MAX_UD,
 125         AC_UD_TCS_MAX_UD,
 126         AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
 127         AC_UD_TES_MAX_UD,
 128         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 129 };
 130 struct radv_shader_info {
 131         bool loads_push_constants;
 132         uint32_t desc_set_used_mask;
 133         bool needs_multiview_view_index;
 134         bool uses_invocation_id;
 135         bool uses_prim_id;
 136         struct {
 137                 uint64_t ls_outputs_written;
 138                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 139                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 140                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 141                 bool needs_draw_id;
 142                 bool needs_instance_id;
 143         } vs;
 144         struct {
 145                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 146         } tes;
 147         struct {
 148                 bool force_persample;
 149                 bool needs_sample_positions;
 150                 bool uses_input_attachments;
 151                 bool writes_memory;
 152                 bool writes_z;
 153                 bool writes_stencil;
 154                 bool writes_sample_mask;
 155                 bool has_pcoord;
 156                 bool prim_id_input;
 157                 bool layer_input;
 158         } ps;
 159         struct {
 160                 bool uses_grid_size;
 161                 bool uses_block_id[3];
 162                 bool uses_thread_id[3];
 163                 bool uses_local_invocation_idx;
 164         } cs;
 165         struct {
 166                 uint64_t outputs_written;
 167                 uint64_t patch_outputs_written;
 168         } tcs;
 169 };
 170
 171 struct radv_userdata_info {
 172         int8_t sgpr_idx;
 173         uint8_t num_sgprs;
 174         bool indirect;
 175         uint32_t indirect_offset;
 176 };
 177
 178 struct radv_userdata_locations {
 179         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 180         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 181 };
 182
 183 struct radv_vs_output_info {
 184         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 185         uint8_t clip_dist_mask;
 186         uint8_t cull_dist_mask;
 187         uint8_t param_exports;
 188         bool writes_pointsize;
 189         bool writes_layer;
 190         bool writes_viewport_index;
 191         bool export_prim_id;
 192         unsigned pos_exports;
 193 };
 194
 195 struct radv_es_output_info {
 196         uint32_t esgs_itemsize;
 197 };
 198
 199 struct radv_shader_variant_info {
 200         struct radv_userdata_locations user_sgprs_locs;
 201         struct radv_shader_info info;
 202         unsigned num_user_sgprs;
 203         unsigned num_input_sgprs;
 204         unsigned num_input_vgprs;
 205         unsigned private_mem_vgprs;
 206         bool need_indirect_descriptor_sets;
 207         struct {
 208                 struct {
 209                         struct radv_vs_output_info outinfo;
 210                         struct radv_es_output_info es_info;
 211                         unsigned vgpr_comp_cnt;
 212                         bool as_es;
 213                         bool as_ls;
 214                         uint64_t outputs_written;
 215                 } vs;
 216                 struct {
 217                         unsigned num_interp;
 218                         uint32_t input_mask;
 219                         uint32_t flat_shaded_mask;
 220                         bool can_discard;
 221                         bool early_fragment_test;
 222                 } fs;
 223                 struct {
 224                         unsigned block_size[3];
 225                 } cs;
 226                 struct {
 227                         unsigned vertices_in;
 228                         unsigned vertices_out;
 229                         unsigned output_prim;
 230                         unsigned invocations;
 231                         unsigned gsvs_vertex_size;
 232                         unsigned max_gsvs_emit_size;
 233                         unsigned es_type; /* GFX9: VS or TES */
 234                 } gs;
 235                 struct {
 236                         unsigned tcs_vertices_out;
 237                         /* Which outputs are actually written */
 238                         uint64_t outputs_written;
 239                         /* Which patch outputs are actually written */
 240                         uint32_t patch_outputs_written;
 241                         uint32_t num_patches;
 242                 } tcs;
 243                 struct {
 244                         struct radv_vs_output_info outinfo;
 245                         struct radv_es_output_info es_info;
 246                         bool as_es;
 247                         unsigned primitive_mode;
 248                         enum gl_tess_spacing spacing;
 249                         bool ccw;
 250                         bool point_mode;
 251                 } tes;
 252         };
 253 };
 254
 255 struct radv_shader_variant {
 256         uint32_t ref_count;
 257
 258         struct radeon_winsys_bo *bo;
 259         uint64_t bo_offset;
 260         struct ac_shader_config config;
 261         uint32_t code_size;
 262         struct radv_shader_variant_info info;
 263         unsigned rsrc1;
 264         unsigned rsrc2;
 265
 266         /* debug only */
 267         uint32_t *spirv;
 268         uint32_t spirv_size;
 269         struct nir_shader *nir;
 270         char *disasm_string;
 271         char *llvm_ir_string;
 272
 273         struct list_head slab_list;
 274 };
 275
 276 struct radv_shader_slab {
 277         struct list_head slabs;
 278         struct list_head shaders;
 279         struct radeon_winsys_bo *bo;
 280         uint64_t size;
 281         char *ptr;
 282 };
 283
 284 void
 285 radv_optimize_nir(struct nir_shader *shader);
 286
 287 nir_shader *
 288 radv_shader_compile_to_nir(struct radv_device *device,
 289                            struct radv_shader_module *module,
 290                            const char *entrypoint_name,
 291                            gl_shader_stage stage,
 292                            const VkSpecializationInfo *spec_info);
 293
 294 void *
 295 radv_alloc_shader_memory(struct radv_device *device,
 296                           struct radv_shader_variant *shader);
 297
 298 void
 299 radv_destroy_shader_slabs(struct radv_device *device);
 300
 301 struct radv_shader_variant *
 302 radv_shader_variant_create(struct radv_device *device,
 303                            struct radv_shader_module *module,
 304                            struct nir_shader *const *shaders,
 305                            int shader_count,
 306                            struct radv_pipeline_layout *layout,
 307                            const struct radv_shader_variant_key *key,
 308                            void **code_out,
 309                            unsigned *code_size_out);
 310
 311 struct radv_shader_variant *
 312 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 313                            void **code_out, unsigned *code_size_out,
 314                            bool multiview);
 315
 316 void
 317 radv_shader_variant_destroy(struct radv_device *device,
 318                             struct radv_shader_variant *variant);
 319
 320 const char *
 321 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 322
 323 void
 324 radv_shader_dump_stats(struct radv_device *device,
 325                        struct radv_shader_variant *variant,
 326                        gl_shader_stage stage,
 327                        FILE *file);
 328
 329 static inline bool
 330 radv_can_dump_shader(struct radv_device *device,
 331                      struct radv_shader_module *module)
 332 {
 333         /* Only dump non-meta shaders, useful for debugging purposes. */
 334         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
 335                module && !module->nir;
 336 }
 337
 338 static inline bool
 339 radv_can_dump_shader_stats(struct radv_device *device,
 340                            struct radv_shader_module *module)
 341 {
 342         /* Only dump non-meta shader stats. */
 343         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 344                module && !module->nir;
 345 }
 346
 347 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 348 {
 349         /* handle patch indices separate */
 350         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 351                 return 0;
 352         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 353                 return 1;
 354         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 355                 return 2 + (slot - VARYING_SLOT_PATCH0);
 356         if (slot == VARYING_SLOT_POS)
 357                 return 0;
 358         if (slot == VARYING_SLOT_PSIZ)
 359                 return 1;
 360         if (slot == VARYING_SLOT_CLIP_DIST0)
 361                 return 2;
 362         /* 3 is reserved for clip dist as well */
 363         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 364                 return 4 + (slot - VARYING_SLOT_VAR0);
 365         unreachable("illegal slot in get unique index\n");
 366 }
 367
 368 #endif