2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_debug.h"
32 #include "radv_private.h"
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
49 #define RADV_NUM_PHYSICAL_VGPRS 256
51 struct radv_shader_module
{
52 struct nir_shader
*nir
;
53 unsigned char sha1
[20];
58 struct radv_vs_variant_key
{
59 uint32_t instance_rate_inputs
;
60 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
63 uint32_t export_prim_id
:1;
64 uint32_t export_layer_id
:1;
67 struct radv_tes_variant_key
{
69 uint32_t export_prim_id
:1;
70 uint32_t export_layer_id
:1;
72 uint8_t tcs_num_outputs
;
75 struct radv_tcs_variant_key
{
76 struct radv_vs_variant_key vs_key
;
77 unsigned primitive_mode
;
78 unsigned input_vertices
;
80 uint32_t tes_reads_tess_factors
:1;
83 struct radv_fs_variant_key
{
85 uint8_t log2_ps_iter_samples
;
86 uint8_t log2_num_samples
;
89 uint32_t multisample
: 1;
92 struct radv_shader_variant_key
{
94 struct radv_vs_variant_key vs
;
95 struct radv_fs_variant_key fs
;
96 struct radv_tes_variant_key tes
;
97 struct radv_tcs_variant_key tcs
;
99 bool has_multiview_view_index
;
102 struct radv_nir_compiler_options
{
103 struct radv_pipeline_layout
*layout
;
104 struct radv_shader_variant_key key
;
107 bool clamp_shadow_reference
;
111 enum radeon_family family
;
112 enum chip_class chip_class
;
113 uint32_t tess_offchip_block_dw_size
;
117 AC_UD_SCRATCH_RING_OFFSETS
= 0,
118 AC_UD_PUSH_CONSTANTS
= 1,
119 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 2,
120 AC_UD_VIEW_INDEX
= 3,
121 AC_UD_SHADER_START
= 4,
122 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
123 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
125 AC_UD_PS_SAMPLE_POS_OFFSET
= AC_UD_SHADER_START
,
127 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
132 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
134 struct radv_shader_info
{
135 bool loads_push_constants
;
136 uint32_t desc_set_used_mask
;
137 bool needs_multiview_view_index
;
138 bool uses_invocation_id
;
141 uint64_t ls_outputs_written
;
142 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
143 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
144 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
146 bool needs_instance_id
;
149 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
152 bool force_persample
;
153 bool needs_sample_positions
;
154 bool uses_input_attachments
;
158 bool writes_sample_mask
;
165 bool uses_block_id
[3];
166 bool uses_thread_id
[3];
167 bool uses_local_invocation_idx
;
170 uint64_t outputs_written
;
171 uint64_t patch_outputs_written
;
175 struct radv_userdata_info
{
179 uint32_t indirect_offset
;
182 struct radv_userdata_locations
{
183 struct radv_userdata_info descriptor_sets
[RADV_UD_MAX_SETS
];
184 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
187 struct radv_vs_output_info
{
188 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
189 uint8_t clip_dist_mask
;
190 uint8_t cull_dist_mask
;
191 uint8_t param_exports
;
192 bool writes_pointsize
;
194 bool writes_viewport_index
;
196 unsigned pos_exports
;
199 struct radv_es_output_info
{
200 uint32_t esgs_itemsize
;
203 struct radv_shader_variant_info
{
204 struct radv_userdata_locations user_sgprs_locs
;
205 struct radv_shader_info info
;
206 unsigned num_user_sgprs
;
207 unsigned num_input_sgprs
;
208 unsigned num_input_vgprs
;
209 unsigned private_mem_vgprs
;
210 bool need_indirect_descriptor_sets
;
213 struct radv_vs_output_info outinfo
;
214 struct radv_es_output_info es_info
;
215 unsigned vgpr_comp_cnt
;
222 uint32_t flat_shaded_mask
;
224 bool early_fragment_test
;
227 unsigned block_size
[3];
230 unsigned vertices_in
;
231 unsigned vertices_out
;
232 unsigned output_prim
;
233 unsigned invocations
;
234 unsigned gsvs_vertex_size
;
235 unsigned max_gsvs_emit_size
;
236 unsigned es_type
; /* GFX9: VS or TES */
239 unsigned tcs_vertices_out
;
240 uint32_t num_patches
;
244 struct radv_vs_output_info outinfo
;
245 struct radv_es_output_info es_info
;
247 unsigned primitive_mode
;
248 enum gl_tess_spacing spacing
;
255 struct radv_shader_variant
{
258 struct radeon_winsys_bo
*bo
;
260 struct ac_shader_config config
;
262 struct radv_shader_variant_info info
;
269 struct nir_shader
*nir
;
271 char *llvm_ir_string
;
273 struct list_head slab_list
;
276 struct radv_shader_slab
{
277 struct list_head slabs
;
278 struct list_head shaders
;
279 struct radeon_winsys_bo
*bo
;
285 radv_optimize_nir(struct nir_shader
*shader
);
288 radv_shader_compile_to_nir(struct radv_device
*device
,
289 struct radv_shader_module
*module
,
290 const char *entrypoint_name
,
291 gl_shader_stage stage
,
292 const VkSpecializationInfo
*spec_info
);
295 radv_alloc_shader_memory(struct radv_device
*device
,
296 struct radv_shader_variant
*shader
);
299 radv_destroy_shader_slabs(struct radv_device
*device
);
301 struct radv_shader_variant
*
302 radv_shader_variant_create(struct radv_device
*device
,
303 struct radv_shader_module
*module
,
304 struct nir_shader
*const *shaders
,
306 struct radv_pipeline_layout
*layout
,
307 const struct radv_shader_variant_key
*key
,
309 unsigned *code_size_out
);
311 struct radv_shader_variant
*
312 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
313 void **code_out
, unsigned *code_size_out
,
317 radv_shader_variant_destroy(struct radv_device
*device
,
318 struct radv_shader_variant
*variant
);
321 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
);
324 radv_shader_dump_stats(struct radv_device
*device
,
325 struct radv_shader_variant
*variant
,
326 gl_shader_stage stage
,
330 radv_can_dump_shader(struct radv_device
*device
,
331 struct radv_shader_module
*module
)
333 /* Only dump non-meta shaders, useful for debugging purposes. */
334 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
&&
335 module
&& !module
->nir
;
339 radv_can_dump_shader_stats(struct radv_device
*device
,
340 struct radv_shader_module
*module
)
342 /* Only dump non-meta shader stats. */
343 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
344 module
&& !module
->nir
;
347 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot
)
349 /* handle patch indices separate */
350 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
352 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
354 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
355 return 2 + (slot
- VARYING_SLOT_PATCH0
);
356 if (slot
== VARYING_SLOT_POS
)
358 if (slot
== VARYING_SLOT_PSIZ
)
360 if (slot
== VARYING_SLOT_CLIP_DIST0
)
362 /* 3 is reserved for clip dist as well */
363 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
364 return 4 + (slot
- VARYING_SLOT_VAR0
);
365 unreachable("illegal slot in get unique index\n");
368 static inline uint32_t
369 radv_get_num_physical_sgprs(struct radv_physical_device
*physical_device
)
371 return physical_device
->rad_info
.chip_class
>= VI
? 800 : 512;