2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_debug.h"
32 #include "radv_private.h"
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
49 struct radv_shader_module
{
50 struct nir_shader
*nir
;
51 unsigned char sha1
[20];
56 struct radv_vs_variant_key
{
57 uint32_t instance_rate_inputs
;
60 uint32_t export_prim_id
:1;
63 struct radv_tes_variant_key
{
65 uint32_t export_prim_id
:1;
67 uint8_t tcs_num_outputs
;
70 struct radv_tcs_variant_key
{
71 struct radv_vs_variant_key vs_key
;
72 unsigned primitive_mode
;
73 unsigned input_vertices
;
75 uint32_t tes_reads_tess_factors
:1;
78 struct radv_fs_variant_key
{
80 uint8_t log2_ps_iter_samples
;
81 uint8_t log2_num_samples
;
84 uint32_t multisample
: 1;
87 struct radv_shader_variant_key
{
89 struct radv_vs_variant_key vs
;
90 struct radv_fs_variant_key fs
;
91 struct radv_tes_variant_key tes
;
92 struct radv_tcs_variant_key tcs
;
94 bool has_multiview_view_index
;
97 struct radv_nir_compiler_options
{
98 struct radv_pipeline_layout
*layout
;
99 struct radv_shader_variant_key key
;
102 bool clamp_shadow_reference
;
106 enum radeon_family family
;
107 enum chip_class chip_class
;
108 uint32_t tess_offchip_block_dw_size
;
112 AC_UD_SCRATCH_RING_OFFSETS
= 0,
113 AC_UD_PUSH_CONSTANTS
= 1,
114 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 2,
115 AC_UD_VIEW_INDEX
= 3,
116 AC_UD_SHADER_START
= 4,
117 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
118 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
120 AC_UD_PS_SAMPLE_POS_OFFSET
= AC_UD_SHADER_START
,
122 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
124 AC_UD_GS_VS_RING_STRIDE_ENTRIES
= AC_UD_VS_MAX_UD
,
128 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
130 struct radv_shader_info
{
131 bool loads_push_constants
;
132 uint32_t desc_set_used_mask
;
133 bool needs_multiview_view_index
;
134 bool uses_invocation_id
;
137 uint64_t ls_outputs_written
;
138 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
139 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
140 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
142 bool needs_instance_id
;
145 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
148 bool force_persample
;
149 bool needs_sample_positions
;
150 bool uses_input_attachments
;
154 bool writes_sample_mask
;
161 bool uses_block_id
[3];
162 bool uses_thread_id
[3];
163 bool uses_local_invocation_idx
;
166 uint64_t outputs_written
;
167 uint64_t patch_outputs_written
;
171 struct radv_userdata_info
{
175 uint32_t indirect_offset
;
178 struct radv_userdata_locations
{
179 struct radv_userdata_info descriptor_sets
[RADV_UD_MAX_SETS
];
180 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
183 struct radv_vs_output_info
{
184 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
185 uint8_t clip_dist_mask
;
186 uint8_t cull_dist_mask
;
187 uint8_t param_exports
;
188 bool writes_pointsize
;
190 bool writes_viewport_index
;
192 unsigned pos_exports
;
195 struct radv_es_output_info
{
196 uint32_t esgs_itemsize
;
199 struct radv_shader_variant_info
{
200 struct radv_userdata_locations user_sgprs_locs
;
201 struct radv_shader_info info
;
202 unsigned num_user_sgprs
;
203 unsigned num_input_sgprs
;
204 unsigned num_input_vgprs
;
205 unsigned private_mem_vgprs
;
206 bool need_indirect_descriptor_sets
;
209 struct radv_vs_output_info outinfo
;
210 struct radv_es_output_info es_info
;
211 unsigned vgpr_comp_cnt
;
218 uint32_t flat_shaded_mask
;
220 bool early_fragment_test
;
223 unsigned block_size
[3];
226 unsigned vertices_in
;
227 unsigned vertices_out
;
228 unsigned output_prim
;
229 unsigned invocations
;
230 unsigned gsvs_vertex_size
;
231 unsigned max_gsvs_emit_size
;
232 unsigned es_type
; /* GFX9: VS or TES */
235 unsigned tcs_vertices_out
;
236 uint32_t num_patches
;
240 struct radv_vs_output_info outinfo
;
241 struct radv_es_output_info es_info
;
243 unsigned primitive_mode
;
244 enum gl_tess_spacing spacing
;
251 struct radv_shader_variant
{
254 struct radeon_winsys_bo
*bo
;
256 struct ac_shader_config config
;
258 struct radv_shader_variant_info info
;
265 struct nir_shader
*nir
;
267 char *llvm_ir_string
;
269 struct list_head slab_list
;
272 struct radv_shader_slab
{
273 struct list_head slabs
;
274 struct list_head shaders
;
275 struct radeon_winsys_bo
*bo
;
281 radv_optimize_nir(struct nir_shader
*shader
);
284 radv_shader_compile_to_nir(struct radv_device
*device
,
285 struct radv_shader_module
*module
,
286 const char *entrypoint_name
,
287 gl_shader_stage stage
,
288 const VkSpecializationInfo
*spec_info
);
291 radv_alloc_shader_memory(struct radv_device
*device
,
292 struct radv_shader_variant
*shader
);
295 radv_destroy_shader_slabs(struct radv_device
*device
);
297 struct radv_shader_variant
*
298 radv_shader_variant_create(struct radv_device
*device
,
299 struct radv_shader_module
*module
,
300 struct nir_shader
*const *shaders
,
302 struct radv_pipeline_layout
*layout
,
303 const struct radv_shader_variant_key
*key
,
305 unsigned *code_size_out
);
307 struct radv_shader_variant
*
308 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
309 void **code_out
, unsigned *code_size_out
,
313 radv_shader_variant_destroy(struct radv_device
*device
,
314 struct radv_shader_variant
*variant
);
317 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
);
320 radv_shader_dump_stats(struct radv_device
*device
,
321 struct radv_shader_variant
*variant
,
322 gl_shader_stage stage
,
326 radv_can_dump_shader(struct radv_device
*device
,
327 struct radv_shader_module
*module
)
329 /* Only dump non-meta shaders, useful for debugging purposes. */
330 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
&&
331 module
&& !module
->nir
;
335 radv_can_dump_shader_stats(struct radv_device
*device
,
336 struct radv_shader_module
*module
)
338 /* Only dump non-meta shader stats. */
339 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
340 module
&& !module
->nir
;
343 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot
)
345 /* handle patch indices separate */
346 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
348 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
350 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
351 return 2 + (slot
- VARYING_SLOT_PATCH0
);
352 if (slot
== VARYING_SLOT_POS
)
354 if (slot
== VARYING_SLOT_PSIZ
)
356 if (slot
== VARYING_SLOT_CLIP_DIST0
)
358 /* 3 is reserved for clip dist as well */
359 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
360 return 4 + (slot
- VARYING_SLOT_VAR0
);
361 unreachable("illegal slot in get unique index\n");