src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t as_ngg_passthrough:1;
  59         uint32_t export_prim_id:1;
  60         uint32_t export_layer_id:1;
  61         uint32_t export_clip_dists:1;
  62         uint32_t export_viewport_index:1;
  63 };
  64
  65 struct radv_vs_variant_key {
  66         struct radv_vs_out_key out;
  67
  68         uint32_t instance_rate_inputs;
  69         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  70         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  72         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  73         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  74
  75         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  76          * so we may need to fix it up. */
  77         uint64_t alpha_adjust;
  78
  79         /* For some formats the channels have to be shuffled. */
  80         uint32_t post_shuffle;
  81
  82         /* Output primitive type. */
  83         uint8_t outprim;
  84 };
  85
  86 struct radv_tes_variant_key {
  87         struct radv_vs_out_key out;
  88
  89         uint8_t num_patches;
  90         uint8_t tcs_num_outputs;
  91 };
  92
  93 struct radv_tcs_variant_key {
  94         struct radv_vs_variant_key vs_key;
  95         unsigned primitive_mode;
  96         unsigned input_vertices;
  97         unsigned num_inputs;
  98         uint32_t tes_reads_tess_factors:1;
  99 };
 100
 101 struct radv_fs_variant_key {
 102         uint32_t col_format;
 103         uint8_t log2_ps_iter_samples;
 104         uint8_t num_samples;
 105         uint32_t is_int8;
 106         uint32_t is_int10;
 107 };
 108
 109 struct radv_cs_variant_key {
 110         uint8_t subgroup_size;
 111 };
 112
 113 struct radv_shader_variant_key {
 114         union {
 115                 struct radv_vs_variant_key vs;
 116                 struct radv_fs_variant_key fs;
 117                 struct radv_tes_variant_key tes;
 118                 struct radv_tcs_variant_key tcs;
 119                 struct radv_cs_variant_key cs;
 120
 121                 /* A common prefix of the vs and tes keys. */
 122                 struct radv_vs_out_key vs_common_out;
 123         };
 124         bool has_multiview_view_index;
 125 };
 126
 127 struct radv_nir_compiler_options {
 128         struct radv_pipeline_layout *layout;
 129         struct radv_shader_variant_key key;
 130         bool explicit_scratch_args;
 131         bool clamp_shadow_reference;
 132         bool robust_buffer_access;
 133         bool dump_shader;
 134         bool dump_preoptir;
 135         bool record_ir;
 136         bool record_stats;
 137         bool check_ir;
 138         bool has_ls_vgpr_init_bug;
 139         bool use_ngg_streamout;
 140         enum radeon_family family;
 141         enum chip_class chip_class;
 142         uint32_t tess_offchip_block_dw_size;
 143         uint32_t address32_hi;
 144 };
 145
 146 enum radv_ud_index {
 147         AC_UD_SCRATCH_RING_OFFSETS = 0,
 148         AC_UD_PUSH_CONSTANTS = 1,
 149         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 150         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 151         AC_UD_VIEW_INDEX = 4,
 152         AC_UD_STREAMOUT_BUFFERS = 5,
 153         AC_UD_NGG_GS_STATE = 6,
 154         AC_UD_SHADER_START = 7,
 155         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 156         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 157         AC_UD_VS_MAX_UD,
 158         AC_UD_PS_MAX_UD,
 159         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 160         AC_UD_CS_MAX_UD,
 161         AC_UD_GS_MAX_UD,
 162         AC_UD_TCS_MAX_UD,
 163         AC_UD_TES_MAX_UD,
 164         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 165 };
 166
 167 struct radv_stream_output {
 168         uint8_t location;
 169         uint8_t buffer;
 170         uint16_t offset;
 171         uint8_t component_mask;
 172         uint8_t stream;
 173 };
 174
 175 struct radv_streamout_info {
 176         uint16_t num_outputs;
 177         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 178         uint16_t strides[MAX_SO_BUFFERS];
 179         uint32_t enabled_stream_buffers_mask;
 180 };
 181
 182 struct radv_userdata_info {
 183         int8_t sgpr_idx;
 184         uint8_t num_sgprs;
 185 };
 186
 187 struct radv_userdata_locations {
 188         struct radv_userdata_info descriptor_sets[MAX_SETS];
 189         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 190         uint32_t descriptor_sets_enabled;
 191 };
 192
 193 struct radv_vs_output_info {
 194         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 195         uint8_t clip_dist_mask;
 196         uint8_t cull_dist_mask;
 197         uint8_t param_exports;
 198         bool writes_pointsize;
 199         bool writes_layer;
 200         bool writes_viewport_index;
 201         bool export_prim_id;
 202         unsigned pos_exports;
 203 };
 204
 205 struct radv_es_output_info {
 206        uint32_t esgs_itemsize;
 207 };
 208
 209 struct gfx9_gs_info {
 210         uint32_t vgt_gs_onchip_cntl;
 211         uint32_t vgt_gs_max_prims_per_subgroup;
 212         uint32_t vgt_esgs_ring_itemsize;
 213         uint32_t lds_size;
 214 };
 215
 216 struct gfx10_ngg_info {
 217         uint16_t ngg_emit_size; /* in dwords */
 218         uint32_t hw_max_esverts;
 219         uint32_t max_gsprims;
 220         uint32_t max_out_verts;
 221         uint32_t prim_amp_factor;
 222         uint32_t vgt_esgs_ring_itemsize;
 223         uint32_t esgs_ring_size;
 224         bool max_vert_out_per_gs_instance;
 225 };
 226
 227 struct radv_shader_info {
 228         bool loads_push_constants;
 229         bool loads_dynamic_offsets;
 230         uint8_t min_push_constant_used;
 231         uint8_t max_push_constant_used;
 232         bool has_only_32bit_push_constants;
 233         bool has_indirect_push_constants;
 234         uint8_t num_inline_push_consts;
 235         uint8_t base_inline_push_consts;
 236         uint32_t desc_set_used_mask;
 237         bool needs_multiview_view_index;
 238         bool uses_invocation_id;
 239         bool uses_prim_id;
 240         uint8_t wave_size;
 241         uint8_t ballot_bit_size;
 242         struct radv_userdata_locations user_sgprs_locs;
 243         unsigned num_user_sgprs;
 244         unsigned num_input_sgprs;
 245         unsigned num_input_vgprs;
 246         unsigned private_mem_vgprs;
 247         bool need_indirect_descriptor_sets;
 248         bool is_ngg;
 249         bool is_ngg_passthrough;
 250         struct {
 251                 uint64_t ls_outputs_written;
 252                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 253                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 254                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 255                 bool needs_draw_id;
 256                 bool needs_instance_id;
 257                 struct radv_vs_output_info outinfo;
 258                 struct radv_es_output_info es_info;
 259                 bool as_es;
 260                 bool as_ls;
 261                 bool export_prim_id;
 262         } vs;
 263         struct {
 264                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 265                 uint8_t num_stream_output_components[4];
 266                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 267                 uint8_t max_stream;
 268                 bool writes_memory;
 269                 unsigned gsvs_vertex_size;
 270                 unsigned max_gsvs_emit_size;
 271                 unsigned vertices_in;
 272                 unsigned vertices_out;
 273                 unsigned output_prim;
 274                 unsigned invocations;
 275                 unsigned es_type; /* GFX9: VS or TES */
 276         } gs;
 277         struct {
 278                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 279                 struct radv_vs_output_info outinfo;
 280                 struct radv_es_output_info es_info;
 281                 bool as_es;
 282                 unsigned primitive_mode;
 283                 enum gl_tess_spacing spacing;
 284                 bool ccw;
 285                 bool point_mode;
 286                 bool export_prim_id;
 287         } tes;
 288         struct {
 289                 bool force_persample;
 290                 bool needs_sample_positions;
 291                 bool writes_memory;
 292                 bool writes_z;
 293                 bool writes_stencil;
 294                 bool writes_sample_mask;
 295                 bool has_pcoord;
 296                 bool prim_id_input;
 297                 bool layer_input;
 298                 bool viewport_index_input;
 299                 uint8_t num_input_clips_culls;
 300                 uint32_t input_mask;
 301                 uint32_t flat_shaded_mask;
 302                 uint32_t explicit_shaded_mask;
 303                 uint32_t float16_shaded_mask;
 304                 uint32_t num_interp;
 305                 bool can_discard;
 306                 bool early_fragment_test;
 307                 bool post_depth_coverage;
 308         } ps;
 309         struct {
 310                 bool uses_grid_size;
 311                 bool uses_block_id[3];
 312                 bool uses_thread_id[3];
 313                 bool uses_local_invocation_idx;
 314                 unsigned block_size[3];
 315         } cs;
 316         struct {
 317                 uint64_t outputs_written;
 318                 uint64_t patch_outputs_written;
 319                 uint64_t tes_inputs_read;
 320                 uint64_t tes_patch_inputs_read;
 321                 unsigned tcs_vertices_out;
 322                 uint32_t num_patches;
 323                 uint32_t lds_size;
 324         } tcs;
 325
 326         struct radv_streamout_info so;
 327
 328         struct gfx9_gs_info gs_ring_info;
 329         struct gfx10_ngg_info ngg_info;
 330
 331         unsigned float_controls_mode;
 332 };
 333
 334 enum radv_shader_binary_type {
 335         RADV_BINARY_TYPE_LEGACY,
 336         RADV_BINARY_TYPE_RTLD
 337 };
 338
 339 struct radv_shader_binary {
 340         enum radv_shader_binary_type type;
 341         gl_shader_stage stage;
 342         bool is_gs_copy_shader;
 343
 344         struct radv_shader_info info;
 345
 346         /* Self-referential size so we avoid consistency issues. */
 347         uint32_t total_size;
 348 };
 349
 350 struct radv_shader_binary_legacy {
 351         struct radv_shader_binary base;
 352         struct ac_shader_config config;
 353         unsigned code_size;
 354         unsigned exec_size;
 355         unsigned ir_size;
 356         unsigned disasm_size;
 357         unsigned stats_size;
 358
 359         /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
 360          * where the +2 is for 0 of the ir strings. */
 361         uint8_t data[0];
 362 };
 363
 364 struct radv_shader_binary_rtld {
 365         struct radv_shader_binary base;
 366         unsigned elf_size;
 367         unsigned llvm_ir_size;
 368         uint8_t data[0];
 369 };
 370
 371 struct radv_compiler_statistic_info {
 372         char name[32];
 373         char desc[64];
 374 };
 375
 376 struct radv_compiler_statistics {
 377         unsigned count;
 378         struct radv_compiler_statistic_info *infos;
 379         uint32_t values[];
 380 };
 381
 382 struct radv_shader_variant {
 383         uint32_t ref_count;
 384
 385         struct radeon_winsys_bo *bo;
 386         uint64_t bo_offset;
 387         struct ac_shader_config config;
 388         uint32_t code_size;
 389         uint32_t exec_size;
 390         struct radv_shader_info info;
 391
 392         /* debug only */
 393         char *spirv;
 394         uint32_t spirv_size;
 395         char *nir_string;
 396         char *disasm_string;
 397         char *ir_string;
 398         struct radv_compiler_statistics *statistics;
 399
 400         struct list_head slab_list;
 401 };
 402
 403 struct radv_shader_slab {
 404         struct list_head slabs;
 405         struct list_head shaders;
 406         struct radeon_winsys_bo *bo;
 407         uint64_t size;
 408         char *ptr;
 409 };
 410
 411 void
 412 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 413                   bool allow_copies);
 414 bool
 415 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 416                              const struct radv_pipeline_layout *layout);
 417
 418 nir_shader *
 419 radv_shader_compile_to_nir(struct radv_device *device,
 420                            struct radv_shader_module *module,
 421                            const char *entrypoint_name,
 422                            gl_shader_stage stage,
 423                            const VkSpecializationInfo *spec_info,
 424                            const VkPipelineCreateFlags flags,
 425                            const struct radv_pipeline_layout *layout,
 426                            unsigned subgroup_size, unsigned ballot_bit_size);
 427
 428 void *
 429 radv_alloc_shader_memory(struct radv_device *device,
 430                           struct radv_shader_variant *shader);
 431
 432 void
 433 radv_destroy_shader_slabs(struct radv_device *device);
 434
 435 void
 436 radv_create_shaders(struct radv_pipeline *pipeline,
 437                     struct radv_device *device,
 438                     struct radv_pipeline_cache *cache,
 439                     const struct radv_pipeline_key *key,
 440                     const VkPipelineShaderStageCreateInfo **pStages,
 441                     const VkPipelineCreateFlags flags,
 442                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 443                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 444
 445 struct radv_shader_variant *
 446 radv_shader_variant_create(struct radv_device *device,
 447                            const struct radv_shader_binary *binary,
 448                            bool keep_shader_info);
 449 struct radv_shader_variant *
 450 radv_shader_variant_compile(struct radv_device *device,
 451                             struct radv_shader_module *module,
 452                             struct nir_shader *const *shaders,
 453                             int shader_count,
 454                             struct radv_pipeline_layout *layout,
 455                             const struct radv_shader_variant_key *key,
 456                             struct radv_shader_info *info,
 457                             bool keep_shader_info, bool keep_statistic_info,
 458                             struct radv_shader_binary **binary_out);
 459
 460 struct radv_shader_variant *
 461 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 462                            struct radv_shader_info *info,
 463                            struct radv_shader_binary **binary_out,
 464                            bool multiview,  bool keep_shader_info,
 465                            bool keep_statistic_info);
 466
 467 void
 468 radv_shader_variant_destroy(struct radv_device *device,
 469                             struct radv_shader_variant *variant);
 470
 471
 472 unsigned
 473 radv_get_max_waves(struct radv_device *device,
 474                    struct radv_shader_variant *variant,
 475                    gl_shader_stage stage);
 476
 477 unsigned
 478 radv_get_max_workgroup_size(enum chip_class chip_class,
 479                             gl_shader_stage stage,
 480                             const unsigned *sizes);
 481
 482 const char *
 483 radv_get_shader_name(struct radv_shader_info *info,
 484                      gl_shader_stage stage);
 485
 486 void
 487 radv_shader_dump_stats(struct radv_device *device,
 488                        struct radv_shader_variant *variant,
 489                        gl_shader_stage stage,
 490                        FILE *file);
 491
 492 bool
 493 radv_can_dump_shader(struct radv_device *device,
 494                      struct radv_shader_module *module,
 495                      bool is_gs_copy_shader);
 496
 497 bool
 498 radv_can_dump_shader_stats(struct radv_device *device,
 499                            struct radv_shader_module *module);
 500
 501 static inline unsigned
 502 shader_io_get_unique_index(gl_varying_slot slot)
 503 {
 504         /* handle patch indices separate */
 505         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 506                 return 0;
 507         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 508                 return 1;
 509         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 510                 return 2 + (slot - VARYING_SLOT_PATCH0);
 511         if (slot == VARYING_SLOT_POS)
 512                 return 0;
 513         if (slot == VARYING_SLOT_PSIZ)
 514                 return 1;
 515         if (slot == VARYING_SLOT_CLIP_DIST0)
 516                 return 2;
 517         if (slot == VARYING_SLOT_CLIP_DIST1)
 518                 return 3;
 519         /* 3 is reserved for clip dist as well */
 520         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 521                 return 4 + (slot - VARYING_SLOT_VAR0);
 522         unreachable("illegal slot in get unique index\n");
 523 }
 524
 525 static inline unsigned
 526 calculate_tess_lds_size(unsigned tcs_num_input_vertices,
 527                         unsigned tcs_num_output_vertices,
 528                         unsigned tcs_num_inputs,
 529                         unsigned tcs_num_patches,
 530                         unsigned tcs_outputs_written,
 531                         unsigned tcs_per_patch_outputs_written)
 532 {
 533         unsigned num_tcs_outputs = util_last_bit64(tcs_outputs_written);
 534         unsigned num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
 535
 536         unsigned input_vertex_size = tcs_num_inputs * 16;
 537         unsigned output_vertex_size = num_tcs_outputs * 16;
 538
 539         unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
 540
 541         unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 542         unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
 543
 544         unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 545
 546         return output_patch0_offset + output_patch_size * tcs_num_patches;
 547 }
 548
 549 static inline unsigned
 550 get_tcs_num_patches(unsigned tcs_num_input_vertices,
 551                         unsigned tcs_num_output_vertices,
 552                         unsigned tcs_num_inputs,
 553                         unsigned tcs_outputs_written,
 554                         unsigned tcs_per_patch_outputs_written,
 555                         unsigned tess_offchip_block_dw_size,
 556                         enum chip_class chip_class,
 557                         enum radeon_family family)
 558 {
 559         uint32_t input_vertex_size = tcs_num_inputs * 16;
 560         uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
 561         uint32_t num_tcs_outputs = util_last_bit64(tcs_outputs_written);
 562         uint32_t num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
 563         uint32_t output_vertex_size = num_tcs_outputs * 16;
 564         uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 565         uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
 566
 567         /* Ensure that we only need one wave per SIMD so we don't need to check
 568          * resource usage. Also ensures that the number of tcs in and out
 569          * vertices per threadgroup are at most 256.
 570          */
 571         unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
 572         /* Make sure that the data fits in LDS. This assumes the shaders only
 573          * use LDS for the inputs and outputs.
 574          */
 575         unsigned hardware_lds_size = 32768;
 576
 577         /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
 578          * threadgroup, even though there is more than 32 KiB LDS.
 579          *
 580          * Test: dEQP-VK.tessellation.shader_input_output.barrier
 581          */
 582         if (chip_class >= GFX7 && family != CHIP_STONEY)
 583                 hardware_lds_size = 65536;
 584
 585         num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
 586         /* Make sure the output data fits in the offchip buffer */
 587         num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
 588         /* Not necessary for correctness, but improves performance. The
 589          * specific value is taken from the proprietary driver.
 590          */
 591         num_patches = MIN2(num_patches, 40);
 592
 593         /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
 594         if (chip_class == GFX6) {
 595                 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
 596                 num_patches = MIN2(num_patches, one_wave);
 597         }
 598         return num_patches;
 599 }
 600
 601 void
 602 radv_lower_fs_io(nir_shader *nir);
 603
 604 #endif