src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 enum {
  59         RADV_ALPHA_ADJUST_NONE = 0,
  60         RADV_ALPHA_ADJUST_SNORM = 1,
  61         RADV_ALPHA_ADJUST_SINT = 2,
  62         RADV_ALPHA_ADJUST_SSCALED = 3,
  63 };
  64
  65 struct radv_vs_variant_key {
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68
  69         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  70          * so we may need to fix it up. */
  71         uint64_t alpha_adjust;
  72
  73         uint32_t as_es:1;
  74         uint32_t as_ls:1;
  75         uint32_t export_prim_id:1;
  76         uint32_t export_layer_id:1;
  77 };
  78
  79 struct radv_tes_variant_key {
  80         uint32_t as_es:1;
  81         uint32_t export_prim_id:1;
  82         uint32_t export_layer_id:1;
  83         uint8_t num_patches;
  84         uint8_t tcs_num_outputs;
  85 };
  86
  87 struct radv_tcs_variant_key {
  88         struct radv_vs_variant_key vs_key;
  89         unsigned primitive_mode;
  90         unsigned input_vertices;
  91         unsigned num_inputs;
  92         uint32_t tes_reads_tess_factors:1;
  93 };
  94
  95 struct radv_fs_variant_key {
  96         uint32_t col_format;
  97         uint8_t log2_ps_iter_samples;
  98         uint8_t num_samples;
  99         uint32_t is_int8;
 100         uint32_t is_int10;
 101 };
 102
 103 struct radv_shader_variant_key {
 104         union {
 105                 struct radv_vs_variant_key vs;
 106                 struct radv_fs_variant_key fs;
 107                 struct radv_tes_variant_key tes;
 108                 struct radv_tcs_variant_key tcs;
 109         };
 110         bool has_multiview_view_index;
 111 };
 112
 113 struct radv_nir_compiler_options {
 114         struct radv_pipeline_layout *layout;
 115         struct radv_shader_variant_key key;
 116         bool unsafe_math;
 117         bool supports_spill;
 118         bool clamp_shadow_reference;
 119         bool dump_shader;
 120         bool dump_preoptir;
 121         bool record_llvm_ir;
 122         bool check_ir;
 123         enum radeon_family family;
 124         enum chip_class chip_class;
 125         uint32_t tess_offchip_block_dw_size;
 126         uint32_t address32_hi;
 127 };
 128
 129 enum radv_ud_index {
 130         AC_UD_SCRATCH_RING_OFFSETS = 0,
 131         AC_UD_PUSH_CONSTANTS = 1,
 132         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 133         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 134         AC_UD_VIEW_INDEX = 4,
 135         AC_UD_STREAMOUT_BUFFERS = 5,
 136         AC_UD_SHADER_START = 6,
 137         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 138         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 139         AC_UD_VS_MAX_UD,
 140         AC_UD_PS_MAX_UD,
 141         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 142         AC_UD_CS_MAX_UD,
 143         AC_UD_GS_MAX_UD,
 144         AC_UD_TCS_MAX_UD,
 145         AC_UD_TES_MAX_UD,
 146         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 147 };
 148
 149 struct radv_stream_output {
 150         uint8_t location;
 151         uint8_t buffer;
 152         uint16_t offset;
 153         uint8_t component_mask;
 154         uint8_t stream;
 155 };
 156
 157 struct radv_streamout_info {
 158         uint16_t num_outputs;
 159         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 160         uint16_t strides[MAX_SO_BUFFERS];
 161         uint32_t enabled_stream_buffers_mask;
 162 };
 163
 164 struct radv_shader_info {
 165         bool loads_push_constants;
 166         bool loads_dynamic_offsets;
 167         uint8_t min_push_constant_used;
 168         uint8_t max_push_constant_used;
 169         bool has_only_32bit_push_constants;
 170         bool has_indirect_push_constants;
 171         uint8_t num_inline_push_consts;
 172         uint8_t base_inline_push_consts;
 173         uint32_t desc_set_used_mask;
 174         bool needs_multiview_view_index;
 175         bool uses_invocation_id;
 176         bool uses_prim_id;
 177         struct {
 178                 uint64_t ls_outputs_written;
 179                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 180                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 181                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 182                 bool needs_draw_id;
 183                 bool needs_instance_id;
 184         } vs;
 185         struct {
 186                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 187                 uint8_t num_stream_output_components[4];
 188                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 189                 uint8_t max_stream;
 190         } gs;
 191         struct {
 192                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 193         } tes;
 194         struct {
 195                 bool force_persample;
 196                 bool needs_sample_positions;
 197                 bool uses_input_attachments;
 198                 bool writes_memory;
 199                 bool writes_z;
 200                 bool writes_stencil;
 201                 bool writes_sample_mask;
 202                 bool has_pcoord;
 203                 bool prim_id_input;
 204                 bool layer_input;
 205                 uint8_t num_input_clips_culls;
 206         } ps;
 207         struct {
 208                 bool uses_grid_size;
 209                 bool uses_block_id[3];
 210                 bool uses_thread_id[3];
 211                 bool uses_local_invocation_idx;
 212         } cs;
 213         struct {
 214                 uint64_t outputs_written;
 215                 uint64_t patch_outputs_written;
 216         } tcs;
 217
 218         struct radv_streamout_info so;
 219 };
 220
 221 struct radv_userdata_info {
 222         int8_t sgpr_idx;
 223         uint8_t num_sgprs;
 224 };
 225
 226 struct radv_userdata_locations {
 227         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 228         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 229         uint32_t descriptor_sets_enabled;
 230 };
 231
 232 struct radv_vs_output_info {
 233         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 234         uint8_t clip_dist_mask;
 235         uint8_t cull_dist_mask;
 236         uint8_t param_exports;
 237         bool writes_pointsize;
 238         bool writes_layer;
 239         bool writes_viewport_index;
 240         bool export_prim_id;
 241         unsigned pos_exports;
 242 };
 243
 244 struct radv_es_output_info {
 245         uint32_t esgs_itemsize;
 246 };
 247
 248 struct radv_shader_variant_info {
 249         struct radv_userdata_locations user_sgprs_locs;
 250         struct radv_shader_info info;
 251         unsigned num_user_sgprs;
 252         unsigned num_input_sgprs;
 253         unsigned num_input_vgprs;
 254         unsigned private_mem_vgprs;
 255         bool need_indirect_descriptor_sets;
 256         struct {
 257                 struct {
 258                         struct radv_vs_output_info outinfo;
 259                         struct radv_es_output_info es_info;
 260                         unsigned vgpr_comp_cnt;
 261                         bool as_es;
 262                         bool as_ls;
 263                 } vs;
 264                 struct {
 265                         unsigned num_interp;
 266                         uint32_t input_mask;
 267                         uint32_t flat_shaded_mask;
 268                         bool can_discard;
 269                         bool early_fragment_test;
 270                 } fs;
 271                 struct {
 272                         unsigned block_size[3];
 273                 } cs;
 274                 struct {
 275                         unsigned vertices_in;
 276                         unsigned vertices_out;
 277                         unsigned output_prim;
 278                         unsigned invocations;
 279                         unsigned gsvs_vertex_size;
 280                         unsigned max_gsvs_emit_size;
 281                         unsigned es_type; /* GFX9: VS or TES */
 282                 } gs;
 283                 struct {
 284                         unsigned tcs_vertices_out;
 285                         uint32_t num_patches;
 286                         uint32_t lds_size;
 287                 } tcs;
 288                 struct {
 289                         struct radv_vs_output_info outinfo;
 290                         struct radv_es_output_info es_info;
 291                         bool as_es;
 292                         unsigned primitive_mode;
 293                         enum gl_tess_spacing spacing;
 294                         bool ccw;
 295                         bool point_mode;
 296                 } tes;
 297         };
 298 };
 299
 300 struct radv_shader_variant {
 301         uint32_t ref_count;
 302
 303         struct radeon_winsys_bo *bo;
 304         uint64_t bo_offset;
 305         struct ac_shader_config config;
 306         uint32_t code_size;
 307         struct radv_shader_variant_info info;
 308         unsigned rsrc1;
 309         unsigned rsrc2;
 310
 311         /* debug only */
 312         uint32_t *spirv;
 313         uint32_t spirv_size;
 314         struct nir_shader *nir;
 315         char *disasm_string;
 316         char *llvm_ir_string;
 317
 318         struct list_head slab_list;
 319 };
 320
 321 struct radv_shader_slab {
 322         struct list_head slabs;
 323         struct list_head shaders;
 324         struct radeon_winsys_bo *bo;
 325         uint64_t size;
 326         char *ptr;
 327 };
 328
 329 void
 330 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 331                   bool allow_copies);
 332
 333 nir_shader *
 334 radv_shader_compile_to_nir(struct radv_device *device,
 335                            struct radv_shader_module *module,
 336                            const char *entrypoint_name,
 337                            gl_shader_stage stage,
 338                            const VkSpecializationInfo *spec_info,
 339                            const VkPipelineCreateFlags flags);
 340
 341 void *
 342 radv_alloc_shader_memory(struct radv_device *device,
 343                           struct radv_shader_variant *shader);
 344
 345 void
 346 radv_destroy_shader_slabs(struct radv_device *device);
 347
 348 struct radv_shader_variant *
 349 radv_shader_variant_create(struct radv_device *device,
 350                            struct radv_shader_module *module,
 351                            struct nir_shader *const *shaders,
 352                            int shader_count,
 353                            struct radv_pipeline_layout *layout,
 354                            const struct radv_shader_variant_key *key,
 355                            void **code_out,
 356                            unsigned *code_size_out);
 357
 358 struct radv_shader_variant *
 359 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 360                            void **code_out, unsigned *code_size_out,
 361                            bool multiview);
 362
 363 void
 364 radv_shader_variant_destroy(struct radv_device *device,
 365                             struct radv_shader_variant *variant);
 366
 367 const char *
 368 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 369
 370 void
 371 radv_shader_dump_stats(struct radv_device *device,
 372                        struct radv_shader_variant *variant,
 373                        gl_shader_stage stage,
 374                        FILE *file);
 375
 376 static inline bool
 377 radv_can_dump_shader(struct radv_device *device,
 378                      struct radv_shader_module *module,
 379                      bool is_gs_copy_shader)
 380 {
 381         if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
 382                 return false;
 383
 384         /* Only dump non-meta shaders, useful for debugging purposes. */
 385         return (module && !module->nir) || is_gs_copy_shader;
 386 }
 387
 388 static inline bool
 389 radv_can_dump_shader_stats(struct radv_device *device,
 390                            struct radv_shader_module *module)
 391 {
 392         /* Only dump non-meta shader stats. */
 393         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 394                module && !module->nir;
 395 }
 396
 397 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 398 {
 399         /* handle patch indices separate */
 400         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 401                 return 0;
 402         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 403                 return 1;
 404         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 405                 return 2 + (slot - VARYING_SLOT_PATCH0);
 406         if (slot == VARYING_SLOT_POS)
 407                 return 0;
 408         if (slot == VARYING_SLOT_PSIZ)
 409                 return 1;
 410         if (slot == VARYING_SLOT_CLIP_DIST0)
 411                 return 2;
 412         /* 3 is reserved for clip dist as well */
 413         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 414                 return 4 + (slot - VARYING_SLOT_VAR0);
 415         unreachable("illegal slot in get unique index\n");
 416 }
 417
 418 #endif