src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 struct radv_vs_variant_key {
  59         uint32_t instance_rate_inputs;
  60         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  61         uint32_t as_es:1;
  62         uint32_t as_ls:1;
  63         uint32_t export_prim_id:1;
  64         uint32_t export_layer_id:1;
  65 };
  66
  67 struct radv_tes_variant_key {
  68         uint32_t as_es:1;
  69         uint32_t export_prim_id:1;
  70         uint32_t export_layer_id:1;
  71         uint8_t num_patches;
  72         uint8_t tcs_num_outputs;
  73 };
  74
  75 struct radv_tcs_variant_key {
  76         struct radv_vs_variant_key vs_key;
  77         unsigned primitive_mode;
  78         unsigned input_vertices;
  79         unsigned num_inputs;
  80         uint32_t tes_reads_tess_factors:1;
  81 };
  82
  83 struct radv_fs_variant_key {
  84         uint32_t col_format;
  85         uint8_t log2_ps_iter_samples;
  86         uint8_t log2_num_samples;
  87         uint32_t is_int8;
  88         uint32_t is_int10;
  89         uint32_t multisample : 1;
  90 };
  91
  92 struct radv_shader_variant_key {
  93         union {
  94                 struct radv_vs_variant_key vs;
  95                 struct radv_fs_variant_key fs;
  96                 struct radv_tes_variant_key tes;
  97                 struct radv_tcs_variant_key tcs;
  98         };
  99         bool has_multiview_view_index;
 100 };
 101
 102 struct radv_nir_compiler_options {
 103         struct radv_pipeline_layout *layout;
 104         struct radv_shader_variant_key key;
 105         bool unsafe_math;
 106         bool supports_spill;
 107         bool clamp_shadow_reference;
 108         bool dump_shader;
 109         bool dump_preoptir;
 110         bool record_llvm_ir;
 111         enum radeon_family family;
 112         enum chip_class chip_class;
 113         uint32_t tess_offchip_block_dw_size;
 114 };
 115
 116 enum radv_ud_index {
 117         AC_UD_SCRATCH_RING_OFFSETS = 0,
 118         AC_UD_PUSH_CONSTANTS = 1,
 119         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
 120         AC_UD_VIEW_INDEX = 3,
 121         AC_UD_SHADER_START = 4,
 122         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 123         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 124         AC_UD_VS_MAX_UD,
 125         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 126         AC_UD_PS_MAX_UD,
 127         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 128         AC_UD_CS_MAX_UD,
 129         AC_UD_GS_MAX_UD,
 130         AC_UD_TCS_MAX_UD,
 131         AC_UD_TES_MAX_UD,
 132         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 133 };
 134 struct radv_shader_info {
 135         bool loads_push_constants;
 136         uint32_t desc_set_used_mask;
 137         bool needs_multiview_view_index;
 138         bool uses_invocation_id;
 139         bool uses_prim_id;
 140         struct {
 141                 uint64_t ls_outputs_written;
 142                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 143                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 144                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 145                 bool needs_draw_id;
 146                 bool needs_instance_id;
 147         } vs;
 148         struct {
 149                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 150         } tes;
 151         struct {
 152                 bool force_persample;
 153                 bool needs_sample_positions;
 154                 bool uses_input_attachments;
 155                 bool writes_memory;
 156                 bool writes_z;
 157                 bool writes_stencil;
 158                 bool writes_sample_mask;
 159                 bool has_pcoord;
 160                 bool prim_id_input;
 161                 bool layer_input;
 162         } ps;
 163         struct {
 164                 bool uses_grid_size;
 165                 bool uses_block_id[3];
 166                 bool uses_thread_id[3];
 167                 bool uses_local_invocation_idx;
 168         } cs;
 169         struct {
 170                 uint64_t outputs_written;
 171                 uint64_t patch_outputs_written;
 172         } tcs;
 173 };
 174
 175 struct radv_userdata_info {
 176         int8_t sgpr_idx;
 177         uint8_t num_sgprs;
 178         bool indirect;
 179         uint32_t indirect_offset;
 180 };
 181
 182 struct radv_userdata_locations {
 183         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 184         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 185 };
 186
 187 struct radv_vs_output_info {
 188         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 189         uint8_t clip_dist_mask;
 190         uint8_t cull_dist_mask;
 191         uint8_t param_exports;
 192         bool writes_pointsize;
 193         bool writes_layer;
 194         bool writes_viewport_index;
 195         bool export_prim_id;
 196         unsigned pos_exports;
 197 };
 198
 199 struct radv_es_output_info {
 200         uint32_t esgs_itemsize;
 201 };
 202
 203 struct radv_shader_variant_info {
 204         struct radv_userdata_locations user_sgprs_locs;
 205         struct radv_shader_info info;
 206         unsigned num_user_sgprs;
 207         unsigned num_input_sgprs;
 208         unsigned num_input_vgprs;
 209         unsigned private_mem_vgprs;
 210         bool need_indirect_descriptor_sets;
 211         struct {
 212                 struct {
 213                         struct radv_vs_output_info outinfo;
 214                         struct radv_es_output_info es_info;
 215                         unsigned vgpr_comp_cnt;
 216                         bool as_es;
 217                         bool as_ls;
 218                 } vs;
 219                 struct {
 220                         unsigned num_interp;
 221                         uint32_t input_mask;
 222                         uint32_t flat_shaded_mask;
 223                         bool can_discard;
 224                         bool early_fragment_test;
 225                 } fs;
 226                 struct {
 227                         unsigned block_size[3];
 228                 } cs;
 229                 struct {
 230                         unsigned vertices_in;
 231                         unsigned vertices_out;
 232                         unsigned output_prim;
 233                         unsigned invocations;
 234                         unsigned gsvs_vertex_size;
 235                         unsigned max_gsvs_emit_size;
 236                         unsigned es_type; /* GFX9: VS or TES */
 237                 } gs;
 238                 struct {
 239                         unsigned tcs_vertices_out;
 240                         uint32_t num_patches;
 241                         uint32_t lds_size;
 242                 } tcs;
 243                 struct {
 244                         struct radv_vs_output_info outinfo;
 245                         struct radv_es_output_info es_info;
 246                         bool as_es;
 247                         unsigned primitive_mode;
 248                         enum gl_tess_spacing spacing;
 249                         bool ccw;
 250                         bool point_mode;
 251                 } tes;
 252         };
 253 };
 254
 255 struct radv_shader_variant {
 256         uint32_t ref_count;
 257
 258         struct radeon_winsys_bo *bo;
 259         uint64_t bo_offset;
 260         struct ac_shader_config config;
 261         uint32_t code_size;
 262         struct radv_shader_variant_info info;
 263         unsigned rsrc1;
 264         unsigned rsrc2;
 265
 266         /* debug only */
 267         uint32_t *spirv;
 268         uint32_t spirv_size;
 269         struct nir_shader *nir;
 270         char *disasm_string;
 271         char *llvm_ir_string;
 272
 273         struct list_head slab_list;
 274 };
 275
 276 struct radv_shader_slab {
 277         struct list_head slabs;
 278         struct list_head shaders;
 279         struct radeon_winsys_bo *bo;
 280         uint64_t size;
 281         char *ptr;
 282 };
 283
 284 void
 285 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
 286
 287 nir_shader *
 288 radv_shader_compile_to_nir(struct radv_device *device,
 289                            struct radv_shader_module *module,
 290                            const char *entrypoint_name,
 291                            gl_shader_stage stage,
 292                            const VkSpecializationInfo *spec_info,
 293                            const VkPipelineCreateFlags flags);
 294
 295 void *
 296 radv_alloc_shader_memory(struct radv_device *device,
 297                           struct radv_shader_variant *shader);
 298
 299 void
 300 radv_destroy_shader_slabs(struct radv_device *device);
 301
 302 struct radv_shader_variant *
 303 radv_shader_variant_create(struct radv_device *device,
 304                            struct radv_shader_module *module,
 305                            struct nir_shader *const *shaders,
 306                            int shader_count,
 307                            struct radv_pipeline_layout *layout,
 308                            const struct radv_shader_variant_key *key,
 309                            void **code_out,
 310                            unsigned *code_size_out);
 311
 312 struct radv_shader_variant *
 313 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 314                            void **code_out, unsigned *code_size_out,
 315                            bool multiview);
 316
 317 void
 318 radv_shader_variant_destroy(struct radv_device *device,
 319                             struct radv_shader_variant *variant);
 320
 321 const char *
 322 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 323
 324 void
 325 radv_shader_dump_stats(struct radv_device *device,
 326                        struct radv_shader_variant *variant,
 327                        gl_shader_stage stage,
 328                        FILE *file);
 329
 330 static inline bool
 331 radv_can_dump_shader(struct radv_device *device,
 332                      struct radv_shader_module *module)
 333 {
 334         /* Only dump non-meta shaders, useful for debugging purposes. */
 335         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
 336                module && !module->nir;
 337 }
 338
 339 static inline bool
 340 radv_can_dump_shader_stats(struct radv_device *device,
 341                            struct radv_shader_module *module)
 342 {
 343         /* Only dump non-meta shader stats. */
 344         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 345                module && !module->nir;
 346 }
 347
 348 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 349 {
 350         /* handle patch indices separate */
 351         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 352                 return 0;
 353         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 354                 return 1;
 355         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 356                 return 2 + (slot - VARYING_SLOT_PATCH0);
 357         if (slot == VARYING_SLOT_POS)
 358                 return 0;
 359         if (slot == VARYING_SLOT_PSIZ)
 360                 return 1;
 361         if (slot == VARYING_SLOT_CLIP_DIST0)
 362                 return 2;
 363         /* 3 is reserved for clip dist as well */
 364         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 365                 return 4 + (slot - VARYING_SLOT_VAR0);
 366         unreachable("illegal slot in get unique index\n");
 367 }
 368
 369 static inline uint32_t
 370 radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
 371 {
 372         return physical_device->rad_info.chip_class >= VI ? 800 : 512;
 373 }
 374
 375 #endif