src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37 #include "vulkan/util/vk_object.h"
  38
  39 #define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
  40
  41 struct radv_device;
  42
  43 struct radv_shader_module {
  44         struct vk_object_base base;
  45         struct nir_shader *nir;
  46         unsigned char sha1[20];
  47         uint32_t size;
  48         char data[0];
  49 };
  50
  51 enum {
  52         RADV_ALPHA_ADJUST_NONE = 0,
  53         RADV_ALPHA_ADJUST_SNORM = 1,
  54         RADV_ALPHA_ADJUST_SINT = 2,
  55         RADV_ALPHA_ADJUST_SSCALED = 3,
  56 };
  57
  58 struct radv_vs_out_key {
  59         uint32_t as_es:1;
  60         uint32_t as_ls:1;
  61         uint32_t as_ngg:1;
  62         uint32_t as_ngg_passthrough:1;
  63         uint32_t export_prim_id:1;
  64         uint32_t export_layer_id:1;
  65         uint32_t export_clip_dists:1;
  66         uint32_t export_viewport_index:1;
  67 };
  68
  69 struct radv_vs_variant_key {
  70         struct radv_vs_out_key out;
  71
  72         uint32_t instance_rate_inputs;
  73         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  74         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  75         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  76         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  77         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  78
  79         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  80          * so we may need to fix it up. */
  81         uint64_t alpha_adjust;
  82
  83         /* For some formats the channels have to be shuffled. */
  84         uint32_t post_shuffle;
  85
  86         /* Output primitive type. */
  87         uint8_t outprim;
  88 };
  89
  90 struct radv_tes_variant_key {
  91         struct radv_vs_out_key out;
  92
  93         uint8_t num_patches;
  94         uint8_t tcs_num_outputs;
  95 };
  96
  97 struct radv_tcs_variant_key {
  98         struct radv_vs_variant_key vs_key;
  99         unsigned primitive_mode;
 100         unsigned input_vertices;
 101         unsigned num_inputs;
 102         uint32_t tes_reads_tess_factors:1;
 103 };
 104
 105 struct radv_fs_variant_key {
 106         uint32_t col_format;
 107         uint8_t log2_ps_iter_samples;
 108         uint8_t num_samples;
 109         uint32_t is_int8;
 110         uint32_t is_int10;
 111         bool is_dual_src;
 112 };
 113
 114 struct radv_cs_variant_key {
 115         uint8_t subgroup_size;
 116 };
 117
 118 struct radv_shader_variant_key {
 119         union {
 120                 struct radv_vs_variant_key vs;
 121                 struct radv_fs_variant_key fs;
 122                 struct radv_tes_variant_key tes;
 123                 struct radv_tcs_variant_key tcs;
 124                 struct radv_cs_variant_key cs;
 125
 126                 /* A common prefix of the vs and tes keys. */
 127                 struct radv_vs_out_key vs_common_out;
 128         };
 129         bool has_multiview_view_index;
 130 };
 131
 132 struct radv_nir_compiler_options {
 133         struct radv_pipeline_layout *layout;
 134         struct radv_shader_variant_key key;
 135         bool explicit_scratch_args;
 136         bool clamp_shadow_reference;
 137         bool robust_buffer_access;
 138         bool dump_shader;
 139         bool dump_preoptir;
 140         bool record_ir;
 141         bool record_stats;
 142         bool check_ir;
 143         bool has_ls_vgpr_init_bug;
 144         bool use_ngg_streamout;
 145         bool enable_mrt_output_nan_fixup;
 146         enum radeon_family family;
 147         enum chip_class chip_class;
 148         uint32_t tess_offchip_block_dw_size;
 149         uint32_t address32_hi;
 150 };
 151
 152 enum radv_ud_index {
 153         AC_UD_SCRATCH_RING_OFFSETS = 0,
 154         AC_UD_PUSH_CONSTANTS = 1,
 155         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 156         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 157         AC_UD_VIEW_INDEX = 4,
 158         AC_UD_STREAMOUT_BUFFERS = 5,
 159         AC_UD_NGG_GS_STATE = 6,
 160         AC_UD_SHADER_START = 7,
 161         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 162         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 163         AC_UD_VS_MAX_UD,
 164         AC_UD_PS_MAX_UD,
 165         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 166         AC_UD_CS_MAX_UD,
 167         AC_UD_GS_MAX_UD,
 168         AC_UD_TCS_MAX_UD,
 169         AC_UD_TES_MAX_UD,
 170         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 171 };
 172
 173 struct radv_stream_output {
 174         uint8_t location;
 175         uint8_t buffer;
 176         uint16_t offset;
 177         uint8_t component_mask;
 178         uint8_t stream;
 179 };
 180
 181 struct radv_streamout_info {
 182         uint16_t num_outputs;
 183         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 184         uint16_t strides[MAX_SO_BUFFERS];
 185         uint32_t enabled_stream_buffers_mask;
 186 };
 187
 188 struct radv_userdata_info {
 189         int8_t sgpr_idx;
 190         uint8_t num_sgprs;
 191 };
 192
 193 struct radv_userdata_locations {
 194         struct radv_userdata_info descriptor_sets[MAX_SETS];
 195         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 196         uint32_t descriptor_sets_enabled;
 197 };
 198
 199 struct radv_vs_output_info {
 200         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 201         uint8_t clip_dist_mask;
 202         uint8_t cull_dist_mask;
 203         uint8_t param_exports;
 204         bool writes_pointsize;
 205         bool writes_layer;
 206         bool writes_viewport_index;
 207         bool export_prim_id;
 208         unsigned pos_exports;
 209 };
 210
 211 struct radv_es_output_info {
 212        uint32_t esgs_itemsize;
 213 };
 214
 215 struct gfx9_gs_info {
 216         uint32_t vgt_gs_onchip_cntl;
 217         uint32_t vgt_gs_max_prims_per_subgroup;
 218         uint32_t vgt_esgs_ring_itemsize;
 219         uint32_t lds_size;
 220 };
 221
 222 struct gfx10_ngg_info {
 223         uint16_t ngg_emit_size; /* in dwords */
 224         uint32_t hw_max_esverts;
 225         uint32_t max_gsprims;
 226         uint32_t max_out_verts;
 227         uint32_t prim_amp_factor;
 228         uint32_t vgt_esgs_ring_itemsize;
 229         uint32_t esgs_ring_size;
 230         bool max_vert_out_per_gs_instance;
 231 };
 232
 233 struct radv_shader_info {
 234         bool loads_push_constants;
 235         bool loads_dynamic_offsets;
 236         uint8_t min_push_constant_used;
 237         uint8_t max_push_constant_used;
 238         bool has_only_32bit_push_constants;
 239         bool has_indirect_push_constants;
 240         uint8_t num_inline_push_consts;
 241         uint8_t base_inline_push_consts;
 242         uint32_t desc_set_used_mask;
 243         bool needs_multiview_view_index;
 244         bool uses_invocation_id;
 245         bool uses_prim_id;
 246         uint8_t wave_size;
 247         uint8_t ballot_bit_size;
 248         struct radv_userdata_locations user_sgprs_locs;
 249         unsigned num_user_sgprs;
 250         unsigned num_input_sgprs;
 251         unsigned num_input_vgprs;
 252         unsigned private_mem_vgprs;
 253         bool need_indirect_descriptor_sets;
 254         bool is_ngg;
 255         bool is_ngg_passthrough;
 256         struct {
 257                 uint64_t ls_outputs_written;
 258                 uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
 259                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 260                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 261                 bool needs_draw_id;
 262                 bool needs_instance_id;
 263                 struct radv_vs_output_info outinfo;
 264                 struct radv_es_output_info es_info;
 265                 bool as_es;
 266                 bool as_ls;
 267                 bool export_prim_id;
 268                 uint8_t num_linked_outputs;
 269         } vs;
 270         struct {
 271                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 272                 uint8_t num_stream_output_components[4];
 273                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 274                 uint8_t max_stream;
 275                 bool writes_memory;
 276                 unsigned gsvs_vertex_size;
 277                 unsigned max_gsvs_emit_size;
 278                 unsigned vertices_in;
 279                 unsigned vertices_out;
 280                 unsigned output_prim;
 281                 unsigned invocations;
 282                 unsigned es_type; /* GFX9: VS or TES */
 283                 uint8_t num_linked_inputs;
 284         } gs;
 285         struct {
 286                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 287                 struct radv_vs_output_info outinfo;
 288                 struct radv_es_output_info es_info;
 289                 bool as_es;
 290                 unsigned primitive_mode;
 291                 enum gl_tess_spacing spacing;
 292                 bool ccw;
 293                 bool point_mode;
 294                 bool export_prim_id;
 295                 uint8_t num_linked_inputs;
 296                 uint8_t num_linked_patch_inputs;
 297                 uint8_t num_linked_outputs;
 298         } tes;
 299         struct {
 300                 bool force_persample;
 301                 bool needs_sample_positions;
 302                 bool writes_memory;
 303                 bool writes_z;
 304                 bool writes_stencil;
 305                 bool writes_sample_mask;
 306                 bool has_pcoord;
 307                 bool prim_id_input;
 308                 bool layer_input;
 309                 bool viewport_index_input;
 310                 uint8_t num_input_clips_culls;
 311                 uint32_t input_mask;
 312                 uint32_t flat_shaded_mask;
 313                 uint32_t explicit_shaded_mask;
 314                 uint32_t float16_shaded_mask;
 315                 uint32_t num_interp;
 316                 uint32_t cb_shader_mask;
 317                 bool can_discard;
 318                 bool early_fragment_test;
 319                 bool post_depth_coverage;
 320                 uint8_t depth_layout;
 321         } ps;
 322         struct {
 323                 bool uses_grid_size;
 324                 bool uses_block_id[3];
 325                 bool uses_thread_id[3];
 326                 bool uses_local_invocation_idx;
 327                 unsigned block_size[3];
 328         } cs;
 329         struct {
 330                 uint64_t outputs_written;
 331                 uint64_t patch_outputs_written;
 332                 uint64_t tes_inputs_read;
 333                 uint64_t tes_patch_inputs_read;
 334                 unsigned tcs_vertices_out;
 335                 uint32_t num_patches;
 336                 uint32_t num_lds_blocks;
 337                 uint8_t num_linked_inputs;
 338                 uint8_t num_linked_outputs;
 339                 uint8_t num_linked_patch_outputs;
 340         } tcs;
 341
 342         struct radv_streamout_info so;
 343
 344         struct gfx9_gs_info gs_ring_info;
 345         struct gfx10_ngg_info ngg_info;
 346
 347         unsigned float_controls_mode;
 348 };
 349
 350 enum radv_shader_binary_type {
 351         RADV_BINARY_TYPE_LEGACY,
 352         RADV_BINARY_TYPE_RTLD
 353 };
 354
 355 struct radv_shader_binary {
 356         enum radv_shader_binary_type type;
 357         gl_shader_stage stage;
 358         bool is_gs_copy_shader;
 359
 360         struct radv_shader_info info;
 361
 362         /* Self-referential size so we avoid consistency issues. */
 363         uint32_t total_size;
 364 };
 365
 366 struct radv_shader_binary_legacy {
 367         struct radv_shader_binary base;
 368         struct ac_shader_config config;
 369         unsigned code_size;
 370         unsigned exec_size;
 371         unsigned ir_size;
 372         unsigned disasm_size;
 373         unsigned stats_size;
 374
 375         /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
 376          * where the +2 is for 0 of the ir strings. */
 377         uint8_t data[0];
 378 };
 379
 380 struct radv_shader_binary_rtld {
 381         struct radv_shader_binary base;
 382         unsigned elf_size;
 383         unsigned llvm_ir_size;
 384         uint8_t data[0];
 385 };
 386
 387 struct radv_compiler_statistic_info {
 388         char name[32];
 389         char desc[64];
 390 };
 391
 392 struct radv_compiler_statistics {
 393         unsigned count;
 394         struct radv_compiler_statistic_info *infos;
 395         uint32_t values[];
 396 };
 397
 398 struct radv_shader_variant {
 399         uint32_t ref_count;
 400
 401         struct radeon_winsys_bo *bo;
 402         uint64_t bo_offset;
 403         struct ac_shader_config config;
 404         uint32_t code_size;
 405         uint32_t exec_size;
 406         struct radv_shader_info info;
 407
 408         /* debug only */
 409         char *spirv;
 410         uint32_t spirv_size;
 411         char *nir_string;
 412         char *disasm_string;
 413         char *ir_string;
 414         struct radv_compiler_statistics *statistics;
 415
 416         struct list_head slab_list;
 417 };
 418
 419 struct radv_shader_slab {
 420         struct list_head slabs;
 421         struct list_head shaders;
 422         struct radeon_winsys_bo *bo;
 423         uint64_t size;
 424         char *ptr;
 425 };
 426
 427 void
 428 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 429                   bool allow_copies);
 430 bool
 431 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 432                              const struct radv_pipeline_layout *layout);
 433
 434 nir_shader *
 435 radv_shader_compile_to_nir(struct radv_device *device,
 436                            struct radv_shader_module *module,
 437                            const char *entrypoint_name,
 438                            gl_shader_stage stage,
 439                            const VkSpecializationInfo *spec_info,
 440                            const VkPipelineCreateFlags flags,
 441                            const struct radv_pipeline_layout *layout,
 442                            unsigned subgroup_size, unsigned ballot_bit_size);
 443
 444 void
 445 radv_destroy_shader_slabs(struct radv_device *device);
 446
 447 VkResult
 448 radv_create_shaders(struct radv_pipeline *pipeline,
 449                     struct radv_device *device,
 450                     struct radv_pipeline_cache *cache,
 451                     const struct radv_pipeline_key *key,
 452                     const VkPipelineShaderStageCreateInfo **pStages,
 453                     const VkPipelineCreateFlags flags,
 454                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 455                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 456
 457 struct radv_shader_variant *
 458 radv_shader_variant_create(struct radv_device *device,
 459                            const struct radv_shader_binary *binary,
 460                            bool keep_shader_info);
 461 struct radv_shader_variant *
 462 radv_shader_variant_compile(struct radv_device *device,
 463                             struct radv_shader_module *module,
 464                             struct nir_shader *const *shaders,
 465                             int shader_count,
 466                             struct radv_pipeline_layout *layout,
 467                             const struct radv_shader_variant_key *key,
 468                             struct radv_shader_info *info,
 469                             bool keep_shader_info, bool keep_statistic_info,
 470                             struct radv_shader_binary **binary_out);
 471
 472 struct radv_shader_variant *
 473 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 474                            struct radv_shader_info *info,
 475                            struct radv_shader_binary **binary_out,
 476                            bool multiview,  bool keep_shader_info,
 477                            bool keep_statistic_info);
 478
 479 void
 480 radv_shader_variant_destroy(struct radv_device *device,
 481                             struct radv_shader_variant *variant);
 482
 483
 484 unsigned
 485 radv_get_max_waves(struct radv_device *device,
 486                    struct radv_shader_variant *variant,
 487                    gl_shader_stage stage);
 488
 489 unsigned
 490 radv_get_max_workgroup_size(enum chip_class chip_class,
 491                             gl_shader_stage stage,
 492                             const unsigned *sizes);
 493
 494 const char *
 495 radv_get_shader_name(struct radv_shader_info *info,
 496                      gl_shader_stage stage);
 497
 498 void
 499 radv_shader_dump_stats(struct radv_device *device,
 500                        struct radv_shader_variant *variant,
 501                        gl_shader_stage stage,
 502                        FILE *file);
 503
 504 bool
 505 radv_can_dump_shader(struct radv_device *device,
 506                      struct radv_shader_module *module,
 507                      bool is_gs_copy_shader);
 508
 509 bool
 510 radv_can_dump_shader_stats(struct radv_device *device,
 511                            struct radv_shader_module *module);
 512
 513 static inline unsigned
 514 shader_io_get_unique_index(gl_varying_slot slot)
 515 {
 516         /* handle patch indices separate */
 517         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 518                 return 0;
 519         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 520                 return 1;
 521         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 522                 return 2 + (slot - VARYING_SLOT_PATCH0);
 523         if (slot == VARYING_SLOT_POS)
 524                 return 0;
 525         if (slot == VARYING_SLOT_PSIZ)
 526                 return 1;
 527         if (slot == VARYING_SLOT_CLIP_DIST0)
 528                 return 2;
 529         if (slot == VARYING_SLOT_CLIP_DIST1)
 530                 return 3;
 531         /* 3 is reserved for clip dist as well */
 532         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 533                 return 4 + (slot - VARYING_SLOT_VAR0);
 534         unreachable("illegal slot in get unique index\n");
 535 }
 536
 537 static inline unsigned
 538 calculate_tess_lds_size(enum chip_class chip_class,
 539                         unsigned tcs_num_input_vertices,
 540                         unsigned tcs_num_output_vertices,
 541                         unsigned tcs_num_inputs,
 542                         unsigned tcs_num_patches,
 543                         unsigned tcs_num_outputs,
 544                         unsigned tcs_num_patch_outputs)
 545 {
 546         unsigned input_vertex_size = tcs_num_inputs * 16;
 547         unsigned output_vertex_size = tcs_num_outputs * 16;
 548
 549         unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
 550
 551         unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 552         unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 553
 554         unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 555
 556         unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
 557
 558         if (chip_class >= GFX7) {
 559                 assert(lds_size <= 65536);
 560                 lds_size = align(lds_size, 512) / 512;
 561         } else {
 562                 assert(lds_size <= 32768);
 563                 lds_size = align(lds_size, 256) / 256;
 564         }
 565
 566         return lds_size;
 567 }
 568
 569 static inline unsigned
 570 get_tcs_num_patches(unsigned tcs_num_input_vertices,
 571                         unsigned tcs_num_output_vertices,
 572                         unsigned tcs_num_inputs,
 573                         unsigned tcs_num_outputs,
 574                         unsigned tcs_num_patch_outputs,
 575                         unsigned tess_offchip_block_dw_size,
 576                         enum chip_class chip_class,
 577                         enum radeon_family family)
 578 {
 579         uint32_t input_vertex_size = tcs_num_inputs * 16;
 580         uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
 581         uint32_t output_vertex_size = tcs_num_outputs * 16;
 582         uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 583         uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 584
 585         /* Ensure that we only need one wave per SIMD so we don't need to check
 586          * resource usage. Also ensures that the number of tcs in and out
 587          * vertices per threadgroup are at most 256.
 588          */
 589         unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
 590         /* Make sure that the data fits in LDS. This assumes the shaders only
 591          * use LDS for the inputs and outputs.
 592          */
 593         unsigned hardware_lds_size = 32768;
 594
 595         /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
 596          * threadgroup, even though there is more than 32 KiB LDS.
 597          *
 598          * Test: dEQP-VK.tessellation.shader_input_output.barrier
 599          */
 600         if (chip_class >= GFX7 && family != CHIP_STONEY)
 601                 hardware_lds_size = 65536;
 602
 603         num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
 604         /* Make sure the output data fits in the offchip buffer */
 605         num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
 606         /* Not necessary for correctness, but improves performance. The
 607          * specific value is taken from the proprietary driver.
 608          */
 609         num_patches = MIN2(num_patches, 40);
 610
 611         /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
 612         if (chip_class == GFX6) {
 613                 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
 614                 num_patches = MIN2(num_patches, one_wave);
 615         }
 616         return num_patches;
 617 }
 618
 619 void
 620 radv_lower_fs_io(nir_shader *nir);
 621
 622 #endif