src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26
  27 static void mark_sampler_desc(const nir_variable *var,
  28                               struct radv_shader_info *info)
  29 {
  30         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  31 }
  32
  33 static void
  34 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
  35                       struct radv_shader_info *info)
  36 {
  37         switch (instr->intrinsic) {
  38         case nir_intrinsic_interp_var_at_sample:
  39                 info->ps.needs_sample_positions = true;
  40                 break;
  41         case nir_intrinsic_load_draw_id:
  42                 info->vs.needs_draw_id = true;
  43                 break;
  44         case nir_intrinsic_load_instance_id:
  45                 info->vs.needs_instance_id = true;
  46                 break;
  47         case nir_intrinsic_load_num_work_groups:
  48                 info->cs.uses_grid_size = true;
  49                 break;
  50         case nir_intrinsic_load_local_invocation_id:
  51         case nir_intrinsic_load_work_group_id: {
  52                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
  53                 while (mask) {
  54                         unsigned i = u_bit_scan(&mask);
  55
  56                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
  57                                 info->cs.uses_block_id[i] = true;
  58                         else
  59                                 info->cs.uses_thread_id[i] = true;
  60                 }
  61                 break;
  62         }
  63         case nir_intrinsic_load_local_invocation_index:
  64         case nir_intrinsic_load_subgroup_id:
  65         case nir_intrinsic_load_num_subgroups:
  66                 info->cs.uses_local_invocation_idx = true;
  67                 break;
  68         case nir_intrinsic_load_sample_id:
  69                 info->ps.force_persample = true;
  70                 break;
  71         case nir_intrinsic_load_sample_pos:
  72                 info->ps.force_persample = true;
  73                 break;
  74         case nir_intrinsic_load_view_index:
  75                 info->needs_multiview_view_index = true;
  76                 break;
  77         case nir_intrinsic_load_invocation_id:
  78                 info->uses_invocation_id = true;
  79                 break;
  80         case nir_intrinsic_load_primitive_id:
  81                 info->uses_prim_id = true;
  82                 break;
  83         case nir_intrinsic_load_push_constant:
  84                 info->loads_push_constants = true;
  85                 break;
  86         case nir_intrinsic_vulkan_resource_index:
  87                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
  88                 break;
  89         case nir_intrinsic_image_load:
  90         case nir_intrinsic_image_store:
  91         case nir_intrinsic_image_atomic_add:
  92         case nir_intrinsic_image_atomic_min:
  93         case nir_intrinsic_image_atomic_max:
  94         case nir_intrinsic_image_atomic_and:
  95         case nir_intrinsic_image_atomic_or:
  96         case nir_intrinsic_image_atomic_xor:
  97         case nir_intrinsic_image_atomic_exchange:
  98         case nir_intrinsic_image_atomic_comp_swap:
  99         case nir_intrinsic_image_size: {
 100                 const struct glsl_type *type = instr->variables[0]->var->type;
 101                 if(instr->variables[0]->deref.child)
 102                         type = instr->variables[0]->deref.child->type;
 103
 104                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 105                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 106                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
 107                         info->ps.uses_input_attachments = true;
 108                 mark_sampler_desc(instr->variables[0]->var, info);
 109
 110                 if (nir_intrinsic_image_store ||
 111                     nir_intrinsic_image_atomic_add ||
 112                     nir_intrinsic_image_atomic_min ||
 113                     nir_intrinsic_image_atomic_max ||
 114                     nir_intrinsic_image_atomic_and ||
 115                     nir_intrinsic_image_atomic_or ||
 116                     nir_intrinsic_image_atomic_xor ||
 117                     nir_intrinsic_image_atomic_exchange ||
 118                     nir_intrinsic_image_atomic_comp_swap) {
 119                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 120                                 info->ps.writes_memory = true;
 121                 }
 122                 break;
 123         }
 124         case nir_intrinsic_store_ssbo:
 125         case nir_intrinsic_ssbo_atomic_add:
 126         case nir_intrinsic_ssbo_atomic_imin:
 127         case nir_intrinsic_ssbo_atomic_umin:
 128         case nir_intrinsic_ssbo_atomic_imax:
 129         case nir_intrinsic_ssbo_atomic_umax:
 130         case nir_intrinsic_ssbo_atomic_and:
 131         case nir_intrinsic_ssbo_atomic_or:
 132         case nir_intrinsic_ssbo_atomic_xor:
 133         case nir_intrinsic_ssbo_atomic_exchange:
 134         case nir_intrinsic_ssbo_atomic_comp_swap:
 135                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 136                         info->ps.writes_memory = true;
 137                 break;
 138         case nir_intrinsic_load_var:
 139                 if (nir->info.stage == MESA_SHADER_VERTEX) {
 140                         nir_deref_var *dvar = instr->variables[0];
 141                         nir_variable *var = dvar->var;
 142
 143                         if (var->data.mode == nir_var_shader_in) {
 144                                 unsigned idx = var->data.location;
 145                                 uint8_t mask =
 146                                         nir_ssa_def_components_read(&instr->dest.ssa) << var->data.location_frac;
 147                                 info->vs.input_usage_mask[idx] |= mask;
 148                         }
 149                 }
 150                 break;
 151         case nir_intrinsic_store_var: {
 152                 nir_deref_var *dvar = instr->variables[0];
 153                 nir_variable *var = dvar->var;
 154
 155                 if (var->data.mode == nir_var_shader_out) {
 156                         unsigned idx = var->data.location;
 157                         unsigned comp = var->data.location_frac;
 158
 159                         if (nir->info.stage == MESA_SHADER_VERTEX) {
 160                                 info->vs.output_usage_mask[idx] |=
 161                                         instr->const_index[0] << comp;
 162                         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 163                                 info->tes.output_usage_mask[idx] |=
 164                                         instr->const_index[0] << comp;
 165                         }
 166                 }
 167                 break;
 168         }
 169         default:
 170                 break;
 171         }
 172 }
 173
 174 static void
 175 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 176                 struct radv_shader_info *info)
 177 {
 178         if (instr->sampler)
 179                 mark_sampler_desc(instr->sampler->var, info);
 180         if (instr->texture)
 181                 mark_sampler_desc(instr->texture->var, info);
 182 }
 183
 184 static void
 185 gather_info_block(const nir_shader *nir, const nir_block *block,
 186                   struct radv_shader_info *info)
 187 {
 188         nir_foreach_instr(instr, block) {
 189                 switch (instr->type) {
 190                 case nir_instr_type_intrinsic:
 191                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 192                         break;
 193                 case nir_instr_type_tex:
 194                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 195                         break;
 196                 default:
 197                         break;
 198                 }
 199         }
 200 }
 201
 202 static void
 203 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 204                           struct radv_shader_info *info)
 205 {
 206         int idx = var->data.location;
 207
 208         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 209                 info->vs.has_vertex_buffers = true;
 210 }
 211
 212 static void
 213 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 214                           struct radv_shader_info *info)
 215 {
 216         const struct glsl_type *type = glsl_without_array(var->type);
 217         int idx = var->data.location;
 218
 219         switch (idx) {
 220         case VARYING_SLOT_PNTC:
 221                 info->ps.has_pcoord = true;
 222                 break;
 223         case VARYING_SLOT_PRIMITIVE_ID:
 224                 info->ps.prim_id_input = true;
 225                 break;
 226         case VARYING_SLOT_LAYER:
 227                 info->ps.layer_input = true;
 228                 break;
 229         default:
 230                 break;
 231         }
 232
 233         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 234                 if (var->data.sample)
 235                         info->ps.force_persample = true;
 236         }
 237 }
 238
 239 static void
 240 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 241                        struct radv_shader_info *info)
 242 {
 243         switch (nir->info.stage) {
 244         case MESA_SHADER_VERTEX:
 245                 gather_info_input_decl_vs(nir, var, info);
 246                 break;
 247         case MESA_SHADER_FRAGMENT:
 248                 gather_info_input_decl_ps(nir, var, info);
 249                 break;
 250         default:
 251                 break;
 252         }
 253 }
 254
 255 static void
 256 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 257                            struct radv_shader_info *info)
 258 {
 259         int idx = var->data.location;
 260
 261         switch (idx) {
 262         case FRAG_RESULT_DEPTH:
 263                 info->ps.writes_z = true;
 264                 break;
 265         case FRAG_RESULT_STENCIL:
 266                 info->ps.writes_stencil = true;
 267                 break;
 268         case FRAG_RESULT_SAMPLE_MASK:
 269                 info->ps.writes_sample_mask = true;
 270                 break;
 271         default:
 272                 break;
 273         }
 274 }
 275
 276 static void
 277 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 278                         struct radv_shader_info *info)
 279 {
 280         switch (nir->info.stage) {
 281         case MESA_SHADER_FRAGMENT:
 282                 gather_info_output_decl_ps(nir, var, info);
 283                 break;
 284         default:
 285                 break;
 286         }
 287 }
 288
 289 void
 290 radv_nir_shader_info_pass(const struct nir_shader *nir,
 291                           const struct radv_nir_compiler_options *options,
 292                           struct radv_shader_info *info)
 293 {
 294         struct nir_function *func =
 295                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 296
 297         if (options->layout->dynamic_offset_count)
 298                 info->loads_push_constants = true;
 299
 300         nir_foreach_variable(variable, &nir->inputs)
 301                 gather_info_input_decl(nir, variable, info);
 302
 303         nir_foreach_block(block, func->impl) {
 304                 gather_info_block(nir, block, info);
 305         }
 306
 307         nir_foreach_variable(variable, &nir->outputs)
 308                 gather_info_output_decl(nir, variable, info);
 309 }