2 * Copyright © 2017 Red Hat
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "radv_private.h"
24 #include "radv_shader.h"
26 #include "nir/nir_deref.h"
27 #include "nir/nir_xfb_info.h"
29 static void mark_sampler_desc(const nir_variable
*var
,
30 struct radv_shader_info
*info
)
32 info
->desc_set_used_mask
|= (1 << var
->data
.descriptor_set
);
35 static void mark_ls_output(struct radv_shader_info
*info
,
36 uint32_t param
, int num_slots
)
38 uint64_t mask
= (1ull << num_slots
) - 1ull;
39 info
->vs
.ls_outputs_written
|= (mask
<< param
);
42 static void mark_tess_output(struct radv_shader_info
*info
,
43 bool is_patch
, uint32_t param
, int num_slots
)
45 uint64_t mask
= (1ull << num_slots
) - 1ull;
47 info
->tcs
.patch_outputs_written
|= (mask
<< param
);
49 info
->tcs
.outputs_written
|= (mask
<< param
);
53 get_deref_offset(nir_deref_instr
*instr
,
56 nir_variable
*var
= nir_deref_instr_get_variable(instr
);
60 if (var
->data
.compact
) {
61 assert(instr
->deref_type
== nir_deref_type_array
);
62 *const_out
= nir_src_as_uint(instr
->arr
.index
);
66 nir_deref_path_init(&path
, instr
, NULL
);
68 uint32_t const_offset
= 0;
70 for (; path
.path
[idx_lvl
]; ++idx_lvl
) {
71 const struct glsl_type
*parent_type
= path
.path
[idx_lvl
- 1]->type
;
72 if (path
.path
[idx_lvl
]->deref_type
== nir_deref_type_struct
) {
73 unsigned index
= path
.path
[idx_lvl
]->strct
.index
;
75 for (unsigned i
= 0; i
< index
; i
++) {
76 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
77 const_offset
+= glsl_count_attribute_slots(ft
, false);
79 } else if(path
.path
[idx_lvl
]->deref_type
== nir_deref_type_array
) {
80 unsigned size
= glsl_count_attribute_slots(path
.path
[idx_lvl
]->type
, false);
81 if (nir_src_is_const(path
.path
[idx_lvl
]->arr
.index
))
82 const_offset
+= nir_src_as_uint(path
.path
[idx_lvl
]->arr
.index
) * size
;
84 unreachable("Uhandled deref type in get_deref_instr_offset");
87 *const_out
= const_offset
;
89 nir_deref_path_finish(&path
);
93 gather_intrinsic_load_deref_info(const nir_shader
*nir
,
94 const nir_intrinsic_instr
*instr
,
95 struct radv_shader_info
*info
)
97 switch (nir
->info
.stage
) {
98 case MESA_SHADER_VERTEX
: {
99 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
101 if (var
&& var
->data
.mode
== nir_var_shader_in
) {
102 unsigned idx
= var
->data
.location
;
103 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
105 info
->vs
.input_usage_mask
[idx
] |=
106 mask
<< var
->data
.location_frac
;
116 widen_writemask(uint32_t wrmask
)
118 uint32_t new_wrmask
= 0;
119 for(unsigned i
= 0; i
< 4; i
++)
120 new_wrmask
|= (wrmask
& (1 << i
) ? 0x3 : 0x0) << (i
* 2);
125 set_output_usage_mask(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
126 uint8_t *output_usage_mask
)
128 nir_deref_instr
*deref_instr
=
129 nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
);
130 nir_variable
*var
= nir_deref_instr_get_variable(deref_instr
);
131 unsigned attrib_count
= glsl_count_attribute_slots(deref_instr
->type
, false);
132 unsigned idx
= var
->data
.location
;
133 unsigned comp
= var
->data
.location_frac
;
134 unsigned const_offset
= 0;
136 get_deref_offset(deref_instr
, &const_offset
);
138 if (var
->data
.compact
) {
139 assert(!glsl_type_is_64bit(deref_instr
->type
));
140 const_offset
+= comp
;
141 output_usage_mask
[idx
+ const_offset
/ 4] |= 1 << (const_offset
% 4);
145 uint32_t wrmask
= nir_intrinsic_write_mask(instr
);
146 if (glsl_type_is_64bit(deref_instr
->type
))
147 wrmask
= widen_writemask(wrmask
);
149 for (unsigned i
= 0; i
< attrib_count
; i
++)
150 output_usage_mask
[idx
+ i
+ const_offset
] |=
151 ((wrmask
>> (i
* 4)) & 0xf) << comp
;
155 gather_intrinsic_store_deref_info(const nir_shader
*nir
,
156 const nir_intrinsic_instr
*instr
,
157 struct radv_shader_info
*info
)
159 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
161 if (var
&& var
->data
.mode
== nir_var_shader_out
) {
162 unsigned idx
= var
->data
.location
;
164 switch (nir
->info
.stage
) {
165 case MESA_SHADER_VERTEX
:
166 set_output_usage_mask(nir
, instr
,
167 info
->vs
.output_usage_mask
);
169 case MESA_SHADER_GEOMETRY
:
170 set_output_usage_mask(nir
, instr
,
171 info
->gs
.output_usage_mask
);
173 case MESA_SHADER_TESS_EVAL
:
174 set_output_usage_mask(nir
, instr
,
175 info
->tes
.output_usage_mask
);
177 case MESA_SHADER_TESS_CTRL
: {
178 unsigned param
= shader_io_get_unique_index(idx
);
179 const struct glsl_type
*type
= var
->type
;
181 if (!var
->data
.patch
)
182 type
= glsl_get_array_element(var
->type
);
185 var
->data
.compact
? DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(type
), 4)
186 : glsl_count_attribute_slots(type
, false);
188 mark_tess_output(info
, var
->data
.patch
, param
, slots
);
198 gather_push_constant_info(const nir_shader
*nir
,
199 const nir_intrinsic_instr
*instr
,
200 struct radv_shader_info
*info
)
202 int base
= nir_intrinsic_base(instr
);
204 if (!nir_src_is_const(instr
->src
[0])) {
205 info
->has_indirect_push_constants
= true;
207 uint32_t min
= base
+ nir_src_as_uint(instr
->src
[0]);
208 uint32_t max
= min
+ instr
->num_components
* 4;
210 info
->max_push_constant_used
=
211 MAX2(max
, info
->max_push_constant_used
);
212 info
->min_push_constant_used
=
213 MIN2(min
, info
->min_push_constant_used
);
216 if (instr
->dest
.ssa
.bit_size
!= 32)
217 info
->has_only_32bit_push_constants
= false;
219 info
->loads_push_constants
= true;
223 gather_intrinsic_info(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
224 struct radv_shader_info
*info
)
226 switch (instr
->intrinsic
) {
227 case nir_intrinsic_load_barycentric_at_sample
:
228 info
->ps
.needs_sample_positions
= true;
230 case nir_intrinsic_load_draw_id
:
231 info
->vs
.needs_draw_id
= true;
233 case nir_intrinsic_load_instance_id
:
234 info
->vs
.needs_instance_id
= true;
236 case nir_intrinsic_load_num_work_groups
:
237 info
->cs
.uses_grid_size
= true;
239 case nir_intrinsic_load_local_invocation_id
:
240 case nir_intrinsic_load_work_group_id
: {
241 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
243 unsigned i
= u_bit_scan(&mask
);
245 if (instr
->intrinsic
== nir_intrinsic_load_work_group_id
)
246 info
->cs
.uses_block_id
[i
] = true;
248 info
->cs
.uses_thread_id
[i
] = true;
252 case nir_intrinsic_load_local_invocation_index
:
253 case nir_intrinsic_load_subgroup_id
:
254 case nir_intrinsic_load_num_subgroups
:
255 info
->cs
.uses_local_invocation_idx
= true;
257 case nir_intrinsic_load_sample_id
:
258 info
->ps
.force_persample
= true;
260 case nir_intrinsic_load_sample_pos
:
261 info
->ps
.force_persample
= true;
263 case nir_intrinsic_load_view_index
:
264 info
->needs_multiview_view_index
= true;
265 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
266 info
->ps
.layer_input
= true;
268 case nir_intrinsic_load_layer_id
:
269 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
270 info
->ps
.layer_input
= true;
272 case nir_intrinsic_load_invocation_id
:
273 info
->uses_invocation_id
= true;
275 case nir_intrinsic_load_primitive_id
:
276 info
->uses_prim_id
= true;
278 case nir_intrinsic_load_push_constant
:
279 gather_push_constant_info(nir
, instr
, info
);
281 case nir_intrinsic_vulkan_resource_index
:
282 info
->desc_set_used_mask
|= (1 << nir_intrinsic_desc_set(instr
));
284 case nir_intrinsic_image_deref_load
:
285 case nir_intrinsic_image_deref_store
:
286 case nir_intrinsic_image_deref_atomic_add
:
287 case nir_intrinsic_image_deref_atomic_imin
:
288 case nir_intrinsic_image_deref_atomic_umin
:
289 case nir_intrinsic_image_deref_atomic_imax
:
290 case nir_intrinsic_image_deref_atomic_umax
:
291 case nir_intrinsic_image_deref_atomic_and
:
292 case nir_intrinsic_image_deref_atomic_or
:
293 case nir_intrinsic_image_deref_atomic_xor
:
294 case nir_intrinsic_image_deref_atomic_exchange
:
295 case nir_intrinsic_image_deref_atomic_comp_swap
:
296 case nir_intrinsic_image_deref_size
: {
297 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
298 mark_sampler_desc(var
, info
);
300 if (instr
->intrinsic
== nir_intrinsic_image_deref_store
||
301 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_add
||
302 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_imin
||
303 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_umin
||
304 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_imax
||
305 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_umax
||
306 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_and
||
307 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_or
||
308 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_xor
||
309 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_exchange
||
310 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
) {
311 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
312 info
->ps
.writes_memory
= true;
316 case nir_intrinsic_store_ssbo
:
317 case nir_intrinsic_ssbo_atomic_add
:
318 case nir_intrinsic_ssbo_atomic_imin
:
319 case nir_intrinsic_ssbo_atomic_umin
:
320 case nir_intrinsic_ssbo_atomic_imax
:
321 case nir_intrinsic_ssbo_atomic_umax
:
322 case nir_intrinsic_ssbo_atomic_and
:
323 case nir_intrinsic_ssbo_atomic_or
:
324 case nir_intrinsic_ssbo_atomic_xor
:
325 case nir_intrinsic_ssbo_atomic_exchange
:
326 case nir_intrinsic_ssbo_atomic_comp_swap
:
327 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
328 info
->ps
.writes_memory
= true;
330 case nir_intrinsic_load_deref
:
331 gather_intrinsic_load_deref_info(nir
, instr
, info
);
333 case nir_intrinsic_store_deref
:
334 gather_intrinsic_store_deref_info(nir
, instr
, info
);
342 gather_tex_info(const nir_shader
*nir
, const nir_tex_instr
*instr
,
343 struct radv_shader_info
*info
)
345 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
346 switch (instr
->src
[i
].src_type
) {
347 case nir_tex_src_texture_deref
:
348 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
350 case nir_tex_src_sampler_deref
:
351 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
360 gather_info_block(const nir_shader
*nir
, const nir_block
*block
,
361 struct radv_shader_info
*info
)
363 nir_foreach_instr(instr
, block
) {
364 switch (instr
->type
) {
365 case nir_instr_type_intrinsic
:
366 gather_intrinsic_info(nir
, nir_instr_as_intrinsic(instr
), info
);
368 case nir_instr_type_tex
:
369 gather_tex_info(nir
, nir_instr_as_tex(instr
), info
);
378 gather_info_input_decl_vs(const nir_shader
*nir
, const nir_variable
*var
,
379 struct radv_shader_info
*info
,
380 const struct radv_nir_compiler_options
*options
)
382 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, true);
383 int idx
= var
->data
.location
;
385 if (idx
>= VERT_ATTRIB_GENERIC0
&& idx
<= VERT_ATTRIB_GENERIC15
)
386 info
->vs
.has_vertex_buffers
= true;
388 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
389 unsigned attrib_index
= var
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
391 if (options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
))
392 info
->vs
.needs_instance_id
= true;
397 mark_16bit_ps_input(struct radv_shader_info
*info
, const struct glsl_type
*type
,
400 if (glsl_type_is_scalar(type
) || glsl_type_is_vector(type
) || glsl_type_is_matrix(type
)) {
401 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
402 if (glsl_type_is_16bit(type
)) {
403 info
->ps
.float16_shaded_mask
|= ((1ull << attrib_count
) - 1) << location
;
405 } else if (glsl_type_is_array(type
)) {
406 unsigned stride
= glsl_count_attribute_slots(glsl_get_array_element(type
), false);
407 for (unsigned i
= 0; i
< glsl_get_length(type
); ++i
) {
408 mark_16bit_ps_input(info
, glsl_get_array_element(type
), location
+ i
* stride
);
411 assert(glsl_type_is_struct_or_ifc(type
));
412 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
413 mark_16bit_ps_input(info
, glsl_get_struct_field(type
, i
), location
);
414 location
+= glsl_count_attribute_slots(glsl_get_struct_field(type
, i
), false);
419 gather_info_input_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
420 struct radv_shader_info
*info
)
422 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
423 const struct glsl_type
*type
= glsl_without_array(var
->type
);
424 int idx
= var
->data
.location
;
427 case VARYING_SLOT_PNTC
:
428 info
->ps
.has_pcoord
= true;
430 case VARYING_SLOT_PRIMITIVE_ID
:
431 info
->ps
.prim_id_input
= true;
433 case VARYING_SLOT_LAYER
:
434 info
->ps
.layer_input
= true;
436 case VARYING_SLOT_CLIP_DIST0
:
437 case VARYING_SLOT_CLIP_DIST1
:
438 info
->ps
.num_input_clips_culls
+= attrib_count
;
444 if (glsl_get_base_type(type
) == GLSL_TYPE_FLOAT
) {
445 if (var
->data
.sample
)
446 info
->ps
.force_persample
= true;
449 if (var
->data
.compact
) {
450 unsigned component_count
= var
->data
.location_frac
+
451 glsl_get_length(var
->type
);
452 attrib_count
= (component_count
+ 3) / 4;
454 mark_16bit_ps_input(info
, var
->type
, var
->data
.driver_location
);
457 uint64_t mask
= ((1ull << attrib_count
) - 1);
459 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
460 info
->ps
.flat_shaded_mask
|= mask
<< var
->data
.driver_location
;
462 if (var
->data
.location
>= VARYING_SLOT_VAR0
)
463 info
->ps
.input_mask
|= mask
<< (var
->data
.location
- VARYING_SLOT_VAR0
);
467 gather_info_input_decl(const nir_shader
*nir
, const nir_variable
*var
,
468 struct radv_shader_info
*info
,
469 const struct radv_nir_compiler_options
*options
)
471 switch (nir
->info
.stage
) {
472 case MESA_SHADER_VERTEX
:
473 gather_info_input_decl_vs(nir
, var
, info
, options
);
475 case MESA_SHADER_FRAGMENT
:
476 gather_info_input_decl_ps(nir
, var
, info
);
484 gather_info_output_decl_ls(const nir_shader
*nir
, const nir_variable
*var
,
485 struct radv_shader_info
*info
)
487 int idx
= var
->data
.location
;
488 unsigned param
= shader_io_get_unique_index(idx
);
489 int num_slots
= glsl_count_attribute_slots(var
->type
, false);
490 if (var
->data
.compact
)
491 num_slots
= DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(var
->type
), 4);
492 mark_ls_output(info
, param
, num_slots
);
496 gather_info_output_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
497 struct radv_shader_info
*info
)
499 int idx
= var
->data
.location
;
502 case FRAG_RESULT_DEPTH
:
503 info
->ps
.writes_z
= true;
505 case FRAG_RESULT_STENCIL
:
506 info
->ps
.writes_stencil
= true;
508 case FRAG_RESULT_SAMPLE_MASK
:
509 info
->ps
.writes_sample_mask
= true;
517 gather_info_output_decl_gs(const nir_shader
*nir
, const nir_variable
*var
,
518 struct radv_shader_info
*info
)
520 unsigned num_components
= glsl_get_component_slots(var
->type
);
521 unsigned stream
= var
->data
.stream
;
522 unsigned idx
= var
->data
.location
;
526 info
->gs
.max_stream
= MAX2(info
->gs
.max_stream
, stream
);
527 info
->gs
.num_stream_output_components
[stream
] += num_components
;
528 info
->gs
.output_streams
[idx
] = stream
;
532 gather_info_output_decl(const nir_shader
*nir
, const nir_variable
*var
,
533 struct radv_shader_info
*info
,
534 const struct radv_nir_compiler_options
*options
)
536 struct radv_vs_output_info
*vs_info
= NULL
;
538 switch (nir
->info
.stage
) {
539 case MESA_SHADER_FRAGMENT
:
540 gather_info_output_decl_ps(nir
, var
, info
);
542 case MESA_SHADER_VERTEX
:
543 if (!options
->key
.vs_common_out
.as_ls
&&
544 !options
->key
.vs_common_out
.as_es
)
545 vs_info
= &info
->vs
.outinfo
;
547 if (options
->key
.vs_common_out
.as_ls
)
548 gather_info_output_decl_ls(nir
, var
, info
);
550 case MESA_SHADER_GEOMETRY
:
551 vs_info
= &info
->vs
.outinfo
;
552 gather_info_output_decl_gs(nir
, var
, info
);
554 case MESA_SHADER_TESS_EVAL
:
555 if (!options
->key
.vs_common_out
.as_es
)
556 vs_info
= &info
->tes
.outinfo
;
563 switch (var
->data
.location
) {
564 case VARYING_SLOT_CLIP_DIST0
:
565 vs_info
->clip_dist_mask
=
566 (1 << nir
->info
.clip_distance_array_size
) - 1;
567 vs_info
->cull_dist_mask
=
568 (1 << nir
->info
.cull_distance_array_size
) - 1;
569 vs_info
->cull_dist_mask
<<= nir
->info
.clip_distance_array_size
;
571 case VARYING_SLOT_PSIZ
:
572 vs_info
->writes_pointsize
= true;
581 gather_xfb_info(const nir_shader
*nir
, struct radv_shader_info
*info
)
583 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
584 struct radv_streamout_info
*so
= &info
->so
;
589 assert(xfb
->output_count
< MAX_SO_OUTPUTS
);
590 so
->num_outputs
= xfb
->output_count
;
592 for (unsigned i
= 0; i
< xfb
->output_count
; i
++) {
593 struct radv_stream_output
*output
= &so
->outputs
[i
];
595 output
->buffer
= xfb
->outputs
[i
].buffer
;
596 output
->stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
597 output
->offset
= xfb
->outputs
[i
].offset
;
598 output
->location
= xfb
->outputs
[i
].location
;
599 output
->component_mask
= xfb
->outputs
[i
].component_mask
;
601 so
->enabled_stream_buffers_mask
|=
602 (1 << output
->buffer
) << (output
->stream
* 4);
606 for (unsigned i
= 0; i
< NIR_MAX_XFB_BUFFERS
; i
++) {
607 so
->strides
[i
] = xfb
->buffers
[i
].stride
/ 4;
614 radv_nir_shader_info_init(struct radv_shader_info
*info
)
616 /* Assume that shaders only have 32-bit push constants by default. */
617 info
->min_push_constant_used
= UINT8_MAX
;
618 info
->has_only_32bit_push_constants
= true;
622 radv_nir_shader_info_pass(const struct nir_shader
*nir
,
623 const struct radv_nir_compiler_options
*options
,
624 struct radv_shader_info
*info
)
626 struct nir_function
*func
=
627 (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
629 if (options
->layout
&& options
->layout
->dynamic_offset_count
&&
630 (options
->layout
->dynamic_shader_stages
& mesa_to_vk_shader_stage(nir
->info
.stage
))) {
631 info
->loads_push_constants
= true;
632 info
->loads_dynamic_offsets
= true;
635 nir_foreach_variable(variable
, &nir
->inputs
)
636 gather_info_input_decl(nir
, variable
, info
, options
);
638 nir_foreach_block(block
, func
->impl
) {
639 gather_info_block(nir
, block
, info
);
642 nir_foreach_variable(variable
, &nir
->outputs
)
643 gather_info_output_decl(nir
, variable
, info
, options
);
645 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
646 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
647 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
648 gather_xfb_info(nir
, info
);
650 /* Make sure to export the LayerID if the fragment shader needs it. */
651 if (options
->key
.vs_common_out
.export_layer_id
) {
652 switch (nir
->info
.stage
) {
653 case MESA_SHADER_VERTEX
:
654 info
->vs
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
656 case MESA_SHADER_TESS_EVAL
:
657 info
->tes
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
659 case MESA_SHADER_GEOMETRY
:
660 info
->gs
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
667 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
668 info
->ps
.num_interp
= nir
->num_inputs
;
670 switch (nir
->info
.stage
) {
671 case MESA_SHADER_COMPUTE
:
672 for (int i
= 0; i
< 3; ++i
)
673 info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
675 case MESA_SHADER_FRAGMENT
:
676 info
->ps
.can_discard
= nir
->info
.fs
.uses_discard
;
677 info
->ps
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
678 info
->ps
.post_depth_coverage
= nir
->info
.fs
.post_depth_coverage
;
680 case MESA_SHADER_GEOMETRY
:
681 info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
682 info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
683 info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
684 info
->gs
.invocations
= nir
->info
.gs
.invocations
;
686 case MESA_SHADER_TESS_EVAL
:
687 info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
688 info
->tes
.spacing
= nir
->info
.tess
.spacing
;
689 info
->tes
.ccw
= nir
->info
.tess
.ccw
;
690 info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
691 info
->tes
.as_es
= options
->key
.vs_common_out
.as_es
;
692 info
->tes
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
693 info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
695 case MESA_SHADER_TESS_CTRL
:
696 info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
698 case MESA_SHADER_VERTEX
:
699 info
->vs
.as_es
= options
->key
.vs_common_out
.as_es
;
700 info
->vs
.as_ls
= options
->key
.vs_common_out
.as_ls
;
701 info
->vs
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
702 info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;