2 * Copyright © 2017 Red Hat
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "radv_private.h"
24 #include "radv_shader.h"
26 #include "nir/nir_deref.h"
27 #include "nir/nir_xfb_info.h"
29 static void mark_sampler_desc(const nir_variable
*var
,
30 struct radv_shader_info
*info
)
32 info
->desc_set_used_mask
|= (1 << var
->data
.descriptor_set
);
35 static void mark_ls_output(struct radv_shader_info
*info
,
36 uint32_t param
, int num_slots
)
38 uint64_t mask
= (1ull << num_slots
) - 1ull;
39 info
->vs
.ls_outputs_written
|= (mask
<< param
);
42 static void mark_tess_output(struct radv_shader_info
*info
,
43 bool is_patch
, uint32_t param
, int num_slots
)
45 uint64_t mask
= (1ull << num_slots
) - 1ull;
47 info
->tcs
.patch_outputs_written
|= (mask
<< param
);
49 info
->tcs
.outputs_written
|= (mask
<< param
);
53 get_deref_offset(nir_deref_instr
*instr
,
56 nir_variable
*var
= nir_deref_instr_get_variable(instr
);
60 if (var
->data
.compact
) {
61 assert(instr
->deref_type
== nir_deref_type_array
);
62 *const_out
= nir_src_as_uint(instr
->arr
.index
);
66 nir_deref_path_init(&path
, instr
, NULL
);
68 uint32_t const_offset
= 0;
70 for (; path
.path
[idx_lvl
]; ++idx_lvl
) {
71 const struct glsl_type
*parent_type
= path
.path
[idx_lvl
- 1]->type
;
72 if (path
.path
[idx_lvl
]->deref_type
== nir_deref_type_struct
) {
73 unsigned index
= path
.path
[idx_lvl
]->strct
.index
;
75 for (unsigned i
= 0; i
< index
; i
++) {
76 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
77 const_offset
+= glsl_count_attribute_slots(ft
, false);
79 } else if(path
.path
[idx_lvl
]->deref_type
== nir_deref_type_array
) {
80 unsigned size
= glsl_count_attribute_slots(path
.path
[idx_lvl
]->type
, false);
81 if (nir_src_is_const(path
.path
[idx_lvl
]->arr
.index
))
82 const_offset
+= nir_src_as_uint(path
.path
[idx_lvl
]->arr
.index
) * size
;
84 unreachable("Uhandled deref type in get_deref_instr_offset");
87 *const_out
= const_offset
;
89 nir_deref_path_finish(&path
);
93 gather_intrinsic_load_deref_info(const nir_shader
*nir
,
94 const nir_intrinsic_instr
*instr
,
95 struct radv_shader_info
*info
)
97 switch (nir
->info
.stage
) {
98 case MESA_SHADER_VERTEX
: {
99 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
101 if (var
&& var
->data
.mode
== nir_var_shader_in
) {
102 unsigned idx
= var
->data
.location
;
103 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
105 info
->vs
.input_usage_mask
[idx
] |=
106 mask
<< var
->data
.location_frac
;
116 widen_writemask(uint32_t wrmask
)
118 uint32_t new_wrmask
= 0;
119 for(unsigned i
= 0; i
< 4; i
++)
120 new_wrmask
|= (wrmask
& (1 << i
) ? 0x3 : 0x0) << (i
* 2);
125 set_output_usage_mask(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
126 uint8_t *output_usage_mask
)
128 nir_deref_instr
*deref_instr
=
129 nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
);
130 nir_variable
*var
= nir_deref_instr_get_variable(deref_instr
);
131 unsigned attrib_count
= glsl_count_attribute_slots(deref_instr
->type
, false);
132 unsigned idx
= var
->data
.location
;
133 unsigned comp
= var
->data
.location_frac
;
134 unsigned const_offset
= 0;
136 get_deref_offset(deref_instr
, &const_offset
);
138 if (var
->data
.compact
) {
139 assert(!glsl_type_is_64bit(deref_instr
->type
));
140 const_offset
+= comp
;
141 output_usage_mask
[idx
+ const_offset
/ 4] |= 1 << (const_offset
% 4);
145 uint32_t wrmask
= nir_intrinsic_write_mask(instr
);
146 if (glsl_type_is_64bit(deref_instr
->type
))
147 wrmask
= widen_writemask(wrmask
);
149 for (unsigned i
= 0; i
< attrib_count
; i
++)
150 output_usage_mask
[idx
+ i
+ const_offset
] |=
151 ((wrmask
>> (i
* 4)) & 0xf) << comp
;
155 set_writes_memory(const nir_shader
*nir
, struct radv_shader_info
*info
)
157 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
158 info
->ps
.writes_memory
= true;
159 else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
160 info
->gs
.writes_memory
= true;
164 gather_intrinsic_store_deref_info(const nir_shader
*nir
,
165 const nir_intrinsic_instr
*instr
,
166 struct radv_shader_info
*info
)
168 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
170 if (var
&& var
->data
.mode
== nir_var_shader_out
) {
171 unsigned idx
= var
->data
.location
;
173 switch (nir
->info
.stage
) {
174 case MESA_SHADER_VERTEX
:
175 set_output_usage_mask(nir
, instr
,
176 info
->vs
.output_usage_mask
);
178 case MESA_SHADER_GEOMETRY
:
179 set_output_usage_mask(nir
, instr
,
180 info
->gs
.output_usage_mask
);
182 case MESA_SHADER_TESS_EVAL
:
183 set_output_usage_mask(nir
, instr
,
184 info
->tes
.output_usage_mask
);
186 case MESA_SHADER_TESS_CTRL
: {
187 unsigned param
= shader_io_get_unique_index(idx
);
188 const struct glsl_type
*type
= var
->type
;
190 if (!var
->data
.patch
)
191 type
= glsl_get_array_element(var
->type
);
194 var
->data
.compact
? DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(type
), 4)
195 : glsl_count_attribute_slots(type
, false);
197 mark_tess_output(info
, var
->data
.patch
, param
, slots
);
207 gather_push_constant_info(const nir_shader
*nir
,
208 const nir_intrinsic_instr
*instr
,
209 struct radv_shader_info
*info
)
211 int base
= nir_intrinsic_base(instr
);
213 if (!nir_src_is_const(instr
->src
[0])) {
214 info
->has_indirect_push_constants
= true;
216 uint32_t min
= base
+ nir_src_as_uint(instr
->src
[0]);
217 uint32_t max
= min
+ instr
->num_components
* 4;
219 info
->max_push_constant_used
=
220 MAX2(max
, info
->max_push_constant_used
);
221 info
->min_push_constant_used
=
222 MIN2(min
, info
->min_push_constant_used
);
225 if (instr
->dest
.ssa
.bit_size
!= 32)
226 info
->has_only_32bit_push_constants
= false;
228 info
->loads_push_constants
= true;
232 gather_intrinsic_info(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
233 struct radv_shader_info
*info
)
235 switch (instr
->intrinsic
) {
236 case nir_intrinsic_load_barycentric_at_sample
:
237 info
->ps
.needs_sample_positions
= true;
239 case nir_intrinsic_load_draw_id
:
240 info
->vs
.needs_draw_id
= true;
242 case nir_intrinsic_load_instance_id
:
243 info
->vs
.needs_instance_id
= true;
245 case nir_intrinsic_load_num_work_groups
:
246 info
->cs
.uses_grid_size
= true;
248 case nir_intrinsic_load_local_invocation_id
:
249 case nir_intrinsic_load_work_group_id
: {
250 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
252 unsigned i
= u_bit_scan(&mask
);
254 if (instr
->intrinsic
== nir_intrinsic_load_work_group_id
)
255 info
->cs
.uses_block_id
[i
] = true;
257 info
->cs
.uses_thread_id
[i
] = true;
261 case nir_intrinsic_load_local_invocation_index
:
262 case nir_intrinsic_load_subgroup_id
:
263 case nir_intrinsic_load_num_subgroups
:
264 info
->cs
.uses_local_invocation_idx
= true;
266 case nir_intrinsic_load_sample_id
:
267 info
->ps
.force_persample
= true;
269 case nir_intrinsic_load_sample_pos
:
270 info
->ps
.force_persample
= true;
272 case nir_intrinsic_load_view_index
:
273 info
->needs_multiview_view_index
= true;
274 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
275 info
->ps
.layer_input
= true;
277 case nir_intrinsic_load_layer_id
:
278 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
279 info
->ps
.layer_input
= true;
281 case nir_intrinsic_load_invocation_id
:
282 info
->uses_invocation_id
= true;
284 case nir_intrinsic_load_primitive_id
:
285 info
->uses_prim_id
= true;
287 case nir_intrinsic_load_push_constant
:
288 gather_push_constant_info(nir
, instr
, info
);
290 case nir_intrinsic_vulkan_resource_index
:
291 info
->desc_set_used_mask
|= (1 << nir_intrinsic_desc_set(instr
));
293 case nir_intrinsic_image_deref_load
:
294 case nir_intrinsic_image_deref_store
:
295 case nir_intrinsic_image_deref_atomic_add
:
296 case nir_intrinsic_image_deref_atomic_imin
:
297 case nir_intrinsic_image_deref_atomic_umin
:
298 case nir_intrinsic_image_deref_atomic_imax
:
299 case nir_intrinsic_image_deref_atomic_umax
:
300 case nir_intrinsic_image_deref_atomic_and
:
301 case nir_intrinsic_image_deref_atomic_or
:
302 case nir_intrinsic_image_deref_atomic_xor
:
303 case nir_intrinsic_image_deref_atomic_exchange
:
304 case nir_intrinsic_image_deref_atomic_comp_swap
:
305 case nir_intrinsic_image_deref_size
: {
306 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
307 mark_sampler_desc(var
, info
);
309 if (instr
->intrinsic
== nir_intrinsic_image_deref_store
||
310 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_add
||
311 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_imin
||
312 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_umin
||
313 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_imax
||
314 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_umax
||
315 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_and
||
316 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_or
||
317 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_xor
||
318 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_exchange
||
319 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
) {
320 set_writes_memory(nir
, info
);
324 case nir_intrinsic_store_ssbo
:
325 case nir_intrinsic_ssbo_atomic_add
:
326 case nir_intrinsic_ssbo_atomic_imin
:
327 case nir_intrinsic_ssbo_atomic_umin
:
328 case nir_intrinsic_ssbo_atomic_imax
:
329 case nir_intrinsic_ssbo_atomic_umax
:
330 case nir_intrinsic_ssbo_atomic_and
:
331 case nir_intrinsic_ssbo_atomic_or
:
332 case nir_intrinsic_ssbo_atomic_xor
:
333 case nir_intrinsic_ssbo_atomic_exchange
:
334 case nir_intrinsic_ssbo_atomic_comp_swap
:
335 set_writes_memory(nir
, info
);
337 case nir_intrinsic_load_deref
:
338 gather_intrinsic_load_deref_info(nir
, instr
, info
);
340 case nir_intrinsic_store_deref
:
341 gather_intrinsic_store_deref_info(nir
, instr
, info
);
343 case nir_intrinsic_deref_atomic_add
:
344 case nir_intrinsic_deref_atomic_imin
:
345 case nir_intrinsic_deref_atomic_umin
:
346 case nir_intrinsic_deref_atomic_imax
:
347 case nir_intrinsic_deref_atomic_umax
:
348 case nir_intrinsic_deref_atomic_and
:
349 case nir_intrinsic_deref_atomic_or
:
350 case nir_intrinsic_deref_atomic_xor
:
351 case nir_intrinsic_deref_atomic_exchange
:
352 case nir_intrinsic_deref_atomic_comp_swap
: {
353 if (nir_src_as_deref(instr
->src
[0])->mode
& (nir_var_mem_global
| nir_var_mem_ssbo
))
354 set_writes_memory(nir
, info
);
363 gather_tex_info(const nir_shader
*nir
, const nir_tex_instr
*instr
,
364 struct radv_shader_info
*info
)
366 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
367 switch (instr
->src
[i
].src_type
) {
368 case nir_tex_src_texture_deref
:
369 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
371 case nir_tex_src_sampler_deref
:
372 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
381 gather_info_block(const nir_shader
*nir
, const nir_block
*block
,
382 struct radv_shader_info
*info
)
384 nir_foreach_instr(instr
, block
) {
385 switch (instr
->type
) {
386 case nir_instr_type_intrinsic
:
387 gather_intrinsic_info(nir
, nir_instr_as_intrinsic(instr
), info
);
389 case nir_instr_type_tex
:
390 gather_tex_info(nir
, nir_instr_as_tex(instr
), info
);
399 gather_info_input_decl_vs(const nir_shader
*nir
, const nir_variable
*var
,
400 struct radv_shader_info
*info
,
401 const struct radv_shader_variant_key
*key
)
403 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, true);
404 int idx
= var
->data
.location
;
406 if (idx
>= VERT_ATTRIB_GENERIC0
&& idx
<= VERT_ATTRIB_GENERIC15
)
407 info
->vs
.has_vertex_buffers
= true;
409 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
410 unsigned attrib_index
= var
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
412 if (key
->vs
.instance_rate_inputs
& (1u << attrib_index
))
413 info
->vs
.needs_instance_id
= true;
418 mark_16bit_ps_input(struct radv_shader_info
*info
, const struct glsl_type
*type
,
421 if (glsl_type_is_scalar(type
) || glsl_type_is_vector(type
) || glsl_type_is_matrix(type
)) {
422 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
423 if (glsl_type_is_16bit(type
)) {
424 info
->ps
.float16_shaded_mask
|= ((1ull << attrib_count
) - 1) << location
;
426 } else if (glsl_type_is_array(type
)) {
427 unsigned stride
= glsl_count_attribute_slots(glsl_get_array_element(type
), false);
428 for (unsigned i
= 0; i
< glsl_get_length(type
); ++i
) {
429 mark_16bit_ps_input(info
, glsl_get_array_element(type
), location
+ i
* stride
);
432 assert(glsl_type_is_struct_or_ifc(type
));
433 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
434 mark_16bit_ps_input(info
, glsl_get_struct_field(type
, i
), location
);
435 location
+= glsl_count_attribute_slots(glsl_get_struct_field(type
, i
), false);
440 gather_info_input_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
441 struct radv_shader_info
*info
)
443 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
444 const struct glsl_type
*type
= glsl_without_array(var
->type
);
445 int idx
= var
->data
.location
;
448 case VARYING_SLOT_PNTC
:
449 info
->ps
.has_pcoord
= true;
451 case VARYING_SLOT_PRIMITIVE_ID
:
452 info
->ps
.prim_id_input
= true;
454 case VARYING_SLOT_LAYER
:
455 info
->ps
.layer_input
= true;
457 case VARYING_SLOT_CLIP_DIST0
:
458 case VARYING_SLOT_CLIP_DIST1
:
459 info
->ps
.num_input_clips_culls
+= attrib_count
;
465 if (glsl_get_base_type(type
) == GLSL_TYPE_FLOAT
) {
466 if (var
->data
.sample
)
467 info
->ps
.force_persample
= true;
470 if (var
->data
.compact
) {
471 unsigned component_count
= var
->data
.location_frac
+
472 glsl_get_length(var
->type
);
473 attrib_count
= (component_count
+ 3) / 4;
475 mark_16bit_ps_input(info
, var
->type
, var
->data
.driver_location
);
478 uint64_t mask
= ((1ull << attrib_count
) - 1);
480 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
481 info
->ps
.flat_shaded_mask
|= mask
<< var
->data
.driver_location
;
483 if (var
->data
.location
>= VARYING_SLOT_VAR0
)
484 info
->ps
.input_mask
|= mask
<< (var
->data
.location
- VARYING_SLOT_VAR0
);
488 gather_info_input_decl(const nir_shader
*nir
, const nir_variable
*var
,
489 struct radv_shader_info
*info
,
490 const struct radv_shader_variant_key
*key
)
492 switch (nir
->info
.stage
) {
493 case MESA_SHADER_VERTEX
:
494 gather_info_input_decl_vs(nir
, var
, info
, key
);
496 case MESA_SHADER_FRAGMENT
:
497 gather_info_input_decl_ps(nir
, var
, info
);
505 gather_info_output_decl_ls(const nir_shader
*nir
, const nir_variable
*var
,
506 struct radv_shader_info
*info
)
508 int idx
= var
->data
.location
;
509 unsigned param
= shader_io_get_unique_index(idx
);
510 int num_slots
= glsl_count_attribute_slots(var
->type
, false);
511 if (var
->data
.compact
)
512 num_slots
= DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(var
->type
), 4);
513 mark_ls_output(info
, param
, num_slots
);
517 gather_info_output_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
518 struct radv_shader_info
*info
)
520 int idx
= var
->data
.location
;
523 case FRAG_RESULT_DEPTH
:
524 info
->ps
.writes_z
= true;
526 case FRAG_RESULT_STENCIL
:
527 info
->ps
.writes_stencil
= true;
529 case FRAG_RESULT_SAMPLE_MASK
:
530 info
->ps
.writes_sample_mask
= true;
538 gather_info_output_decl_gs(const nir_shader
*nir
, const nir_variable
*var
,
539 struct radv_shader_info
*info
)
541 unsigned num_components
= glsl_get_component_slots(var
->type
);
542 unsigned stream
= var
->data
.stream
;
543 unsigned idx
= var
->data
.location
;
547 info
->gs
.max_stream
= MAX2(info
->gs
.max_stream
, stream
);
548 info
->gs
.num_stream_output_components
[stream
] += num_components
;
549 info
->gs
.output_streams
[idx
] = stream
;
553 gather_info_output_decl(const nir_shader
*nir
, const nir_variable
*var
,
554 struct radv_shader_info
*info
,
555 const struct radv_shader_variant_key
*key
)
557 struct radv_vs_output_info
*vs_info
= NULL
;
559 switch (nir
->info
.stage
) {
560 case MESA_SHADER_FRAGMENT
:
561 gather_info_output_decl_ps(nir
, var
, info
);
563 case MESA_SHADER_VERTEX
:
564 if (!key
->vs_common_out
.as_ls
&&
565 !key
->vs_common_out
.as_es
)
566 vs_info
= &info
->vs
.outinfo
;
568 if (key
->vs_common_out
.as_ls
)
569 gather_info_output_decl_ls(nir
, var
, info
);
570 else if (key
->vs_common_out
.as_ngg
)
571 gather_info_output_decl_gs(nir
, var
, info
);
573 case MESA_SHADER_GEOMETRY
:
574 vs_info
= &info
->vs
.outinfo
;
575 gather_info_output_decl_gs(nir
, var
, info
);
577 case MESA_SHADER_TESS_EVAL
:
578 if (!key
->vs_common_out
.as_es
)
579 vs_info
= &info
->tes
.outinfo
;
586 switch (var
->data
.location
) {
587 case VARYING_SLOT_CLIP_DIST0
:
588 vs_info
->clip_dist_mask
=
589 (1 << nir
->info
.clip_distance_array_size
) - 1;
590 vs_info
->cull_dist_mask
=
591 (1 << nir
->info
.cull_distance_array_size
) - 1;
592 vs_info
->cull_dist_mask
<<= nir
->info
.clip_distance_array_size
;
594 case VARYING_SLOT_PSIZ
:
595 vs_info
->writes_pointsize
= true;
597 case VARYING_SLOT_VIEWPORT
:
598 vs_info
->writes_viewport_index
= true;
600 case VARYING_SLOT_LAYER
:
601 vs_info
->writes_layer
= true;
610 gather_xfb_info(const nir_shader
*nir
, struct radv_shader_info
*info
)
612 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
613 struct radv_streamout_info
*so
= &info
->so
;
618 assert(xfb
->output_count
< MAX_SO_OUTPUTS
);
619 so
->num_outputs
= xfb
->output_count
;
621 for (unsigned i
= 0; i
< xfb
->output_count
; i
++) {
622 struct radv_stream_output
*output
= &so
->outputs
[i
];
624 output
->buffer
= xfb
->outputs
[i
].buffer
;
625 output
->stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
626 output
->offset
= xfb
->outputs
[i
].offset
;
627 output
->location
= xfb
->outputs
[i
].location
;
628 output
->component_mask
= xfb
->outputs
[i
].component_mask
;
630 so
->enabled_stream_buffers_mask
|=
631 (1 << output
->buffer
) << (output
->stream
* 4);
635 for (unsigned i
= 0; i
< NIR_MAX_XFB_BUFFERS
; i
++) {
636 so
->strides
[i
] = xfb
->buffers
[i
].stride
/ 4;
643 radv_nir_shader_info_init(struct radv_shader_info
*info
)
645 /* Assume that shaders only have 32-bit push constants by default. */
646 info
->min_push_constant_used
= UINT8_MAX
;
647 info
->has_only_32bit_push_constants
= true;
651 radv_nir_shader_info_pass(const struct nir_shader
*nir
,
652 const struct radv_pipeline_layout
*layout
,
653 const struct radv_shader_variant_key
*key
,
654 struct radv_shader_info
*info
)
656 struct nir_function
*func
=
657 (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
659 if (layout
&& layout
->dynamic_offset_count
&&
660 (layout
->dynamic_shader_stages
& mesa_to_vk_shader_stage(nir
->info
.stage
))) {
661 info
->loads_push_constants
= true;
662 info
->loads_dynamic_offsets
= true;
665 nir_foreach_variable(variable
, &nir
->inputs
)
666 gather_info_input_decl(nir
, variable
, info
, key
);
668 nir_foreach_block(block
, func
->impl
) {
669 gather_info_block(nir
, block
, info
);
672 nir_foreach_variable(variable
, &nir
->outputs
)
673 gather_info_output_decl(nir
, variable
, info
, key
);
675 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
676 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
677 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
678 gather_xfb_info(nir
, info
);
680 /* Make sure to export the LayerID if the fragment shader needs it. */
681 if (key
->vs_common_out
.export_layer_id
) {
682 switch (nir
->info
.stage
) {
683 case MESA_SHADER_VERTEX
:
684 info
->vs
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
686 case MESA_SHADER_TESS_EVAL
:
687 info
->tes
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
689 case MESA_SHADER_GEOMETRY
:
690 info
->gs
.output_usage_mask
[VARYING_SLOT_LAYER
] |= 0x1;
697 /* Make sure to export the LayerID if the subpass has multiviews. */
698 if (key
->has_multiview_view_index
) {
699 switch (nir
->info
.stage
) {
700 case MESA_SHADER_VERTEX
:
701 info
->vs
.outinfo
.writes_layer
= true;
703 case MESA_SHADER_TESS_EVAL
:
704 info
->tes
.outinfo
.writes_layer
= true;
706 case MESA_SHADER_GEOMETRY
:
707 info
->vs
.outinfo
.writes_layer
= true;
714 /* Make sure to export the PrimitiveID if the fragment shader needs it. */
715 if (key
->vs_common_out
.export_prim_id
) {
716 switch (nir
->info
.stage
) {
717 case MESA_SHADER_VERTEX
:
718 info
->vs
.outinfo
.export_prim_id
= true;
720 case MESA_SHADER_TESS_EVAL
:
721 info
->tes
.outinfo
.export_prim_id
= true;
723 case MESA_SHADER_GEOMETRY
:
724 info
->vs
.outinfo
.export_prim_id
= true;
731 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
732 info
->ps
.num_interp
= nir
->num_inputs
;
734 switch (nir
->info
.stage
) {
735 case MESA_SHADER_COMPUTE
:
736 for (int i
= 0; i
< 3; ++i
)
737 info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
739 case MESA_SHADER_FRAGMENT
:
740 info
->ps
.can_discard
= nir
->info
.fs
.uses_discard
;
741 info
->ps
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
742 info
->ps
.post_depth_coverage
= nir
->info
.fs
.post_depth_coverage
;
744 case MESA_SHADER_GEOMETRY
:
745 info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
746 info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
747 info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
748 info
->gs
.invocations
= nir
->info
.gs
.invocations
;
750 case MESA_SHADER_TESS_EVAL
:
751 info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
752 info
->tes
.spacing
= nir
->info
.tess
.spacing
;
753 info
->tes
.ccw
= nir
->info
.tess
.ccw
;
754 info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
755 info
->tes
.as_es
= key
->vs_common_out
.as_es
;
756 info
->tes
.export_prim_id
= key
->vs_common_out
.export_prim_id
;
757 info
->is_ngg
= key
->vs_common_out
.as_ngg
;
759 case MESA_SHADER_TESS_CTRL
:
760 info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
762 case MESA_SHADER_VERTEX
:
763 info
->vs
.as_es
= key
->vs_common_out
.as_es
;
764 info
->vs
.as_ls
= key
->vs_common_out
.as_ls
;
765 info
->vs
.export_prim_id
= key
->vs_common_out
.export_prim_id
;
766 info
->is_ngg
= key
->vs_common_out
.as_ngg
;
772 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
773 unsigned add_clip
= nir
->info
.clip_distance_array_size
+
774 nir
->info
.cull_distance_array_size
> 4;
775 info
->gs
.gsvs_vertex_size
=
776 (util_bitcount64(nir
->info
.outputs_written
) + add_clip
) * 16;
777 info
->gs
.max_gsvs_emit_size
=
778 info
->gs
.gsvs_vertex_size
* nir
->info
.gs
.vertices_out
;
781 /* Compute the ESGS item size for VS or TES as ES. */
782 if ((nir
->info
.stage
== MESA_SHADER_VERTEX
||
783 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) &&
784 key
->vs_common_out
.as_es
) {
785 struct radv_es_output_info
*es_info
=
786 nir
->info
.stage
== MESA_SHADER_VERTEX
? &info
->vs
.es_info
: &info
->tes
.es_info
;
787 uint32_t max_output_written
= 0;
789 uint64_t output_mask
= nir
->info
.outputs_written
;
790 while (output_mask
) {
791 const int i
= u_bit_scan64(&output_mask
);
792 unsigned param_index
= shader_io_get_unique_index(i
);
794 max_output_written
= MAX2(param_index
, max_output_written
);
797 es_info
->esgs_itemsize
= (max_output_written
+ 1) * 16;
800 info
->float_controls_mode
= nir
->info
.float_controls_execution_mode
;