2 * Copyright © 2017 Red Hat
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "radv_private.h"
24 #include "radv_shader.h"
26 #include "nir/nir_deref.h"
27 #include "nir/nir_xfb_info.h"
29 static void mark_sampler_desc(const nir_variable
*var
,
30 struct radv_shader_info
*info
)
32 info
->desc_set_used_mask
|= (1 << var
->data
.descriptor_set
);
35 static void mark_ls_output(struct radv_shader_info
*info
,
36 uint32_t param
, int num_slots
)
38 uint64_t mask
= (1ull << num_slots
) - 1ull;
39 info
->vs
.ls_outputs_written
|= (mask
<< param
);
42 static void mark_tess_output(struct radv_shader_info
*info
,
43 bool is_patch
, uint32_t param
, int num_slots
)
45 uint64_t mask
= (1ull << num_slots
) - 1ull;
47 info
->tcs
.patch_outputs_written
|= (mask
<< param
);
49 info
->tcs
.outputs_written
|= (mask
<< param
);
53 get_deref_offset(nir_deref_instr
*instr
,
56 nir_variable
*var
= nir_deref_instr_get_variable(instr
);
60 if (var
->data
.compact
) {
61 assert(instr
->deref_type
== nir_deref_type_array
);
62 nir_const_value
*v
= nir_src_as_const_value(instr
->arr
.index
);
64 *const_out
= v
->u32
[0];
68 nir_deref_path_init(&path
, instr
, NULL
);
70 uint32_t const_offset
= 0;
72 for (; path
.path
[idx_lvl
]; ++idx_lvl
) {
73 const struct glsl_type
*parent_type
= path
.path
[idx_lvl
- 1]->type
;
74 if (path
.path
[idx_lvl
]->deref_type
== nir_deref_type_struct
) {
75 unsigned index
= path
.path
[idx_lvl
]->strct
.index
;
77 for (unsigned i
= 0; i
< index
; i
++) {
78 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
79 const_offset
+= glsl_count_attribute_slots(ft
, false);
81 } else if(path
.path
[idx_lvl
]->deref_type
== nir_deref_type_array
) {
82 unsigned size
= glsl_count_attribute_slots(path
.path
[idx_lvl
]->type
, false);
83 nir_const_value
*v
= nir_src_as_const_value(path
.path
[idx_lvl
]->arr
.index
);
85 const_offset
+= v
->u32
[0] * size
;
87 unreachable("Uhandled deref type in get_deref_instr_offset");
90 *const_out
= const_offset
;
92 nir_deref_path_finish(&path
);
96 gather_intrinsic_load_deref_info(const nir_shader
*nir
,
97 const nir_intrinsic_instr
*instr
,
98 struct radv_shader_info
*info
)
100 switch (nir
->info
.stage
) {
101 case MESA_SHADER_VERTEX
: {
102 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
104 if (var
&& var
->data
.mode
== nir_var_shader_in
) {
105 unsigned idx
= var
->data
.location
;
106 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
108 info
->vs
.input_usage_mask
[idx
] |=
109 mask
<< var
->data
.location_frac
;
119 set_output_usage_mask(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
120 uint8_t *output_usage_mask
)
122 nir_deref_instr
*deref_instr
=
123 nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
);
124 nir_variable
*var
= nir_deref_instr_get_variable(deref_instr
);
125 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
126 unsigned idx
= var
->data
.location
;
127 unsigned comp
= var
->data
.location_frac
;
128 unsigned const_offset
= 0;
130 get_deref_offset(deref_instr
, &const_offset
);
132 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
133 /* Special case for clip/cull distances because there are
134 * combined into a single array that contains both.
136 output_usage_mask
[idx
] |= 1 << const_offset
;
140 for (unsigned i
= 0; i
< attrib_count
; i
++) {
141 output_usage_mask
[idx
+ i
+ const_offset
] |=
142 instr
->const_index
[0] << comp
;
147 gather_intrinsic_store_deref_info(const nir_shader
*nir
,
148 const nir_intrinsic_instr
*instr
,
149 struct radv_shader_info
*info
)
151 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
153 if (var
&& var
->data
.mode
== nir_var_shader_out
) {
154 unsigned idx
= var
->data
.location
;
156 switch (nir
->info
.stage
) {
157 case MESA_SHADER_VERTEX
:
158 set_output_usage_mask(nir
, instr
,
159 info
->vs
.output_usage_mask
);
161 case MESA_SHADER_GEOMETRY
:
162 set_output_usage_mask(nir
, instr
,
163 info
->gs
.output_usage_mask
);
165 case MESA_SHADER_TESS_EVAL
:
166 set_output_usage_mask(nir
, instr
,
167 info
->tes
.output_usage_mask
);
169 case MESA_SHADER_TESS_CTRL
: {
170 unsigned param
= shader_io_get_unique_index(idx
);
171 const struct glsl_type
*type
= var
->type
;
173 if (!var
->data
.patch
)
174 type
= glsl_get_array_element(var
->type
);
177 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(type
), 4)
178 : glsl_count_attribute_slots(type
, false);
180 if (idx
== VARYING_SLOT_CLIP_DIST0
)
181 slots
= (nir
->info
.clip_distance_array_size
+
182 nir
->info
.cull_distance_array_size
> 4) ? 2 : 1;
184 mark_tess_output(info
, var
->data
.patch
, param
, slots
);
194 gather_push_constant_info(const nir_shader
*nir
,
195 const nir_intrinsic_instr
*instr
,
196 struct radv_shader_info
*info
)
198 nir_const_value
*cval
= nir_src_as_const_value(instr
->src
[0]);
199 int base
= nir_intrinsic_base(instr
);
200 int range
= nir_intrinsic_range(instr
);
203 info
->has_indirect_push_constants
= true;
205 uint32_t min
= base
+ cval
->u32
[0];
206 uint32_t max
= min
+ instr
->num_components
* 4;
208 info
->max_push_constant_used
=
209 MAX2(max
, info
->max_push_constant_used
);
210 info
->min_push_constant_used
=
211 MIN2(min
, info
->min_push_constant_used
);
214 if (instr
->dest
.ssa
.bit_size
!= 32)
215 info
->has_only_32bit_push_constants
= false;
217 info
->loads_push_constants
= true;
221 gather_intrinsic_info(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
222 struct radv_shader_info
*info
)
224 switch (instr
->intrinsic
) {
225 case nir_intrinsic_interp_deref_at_sample
:
226 info
->ps
.needs_sample_positions
= true;
228 case nir_intrinsic_load_draw_id
:
229 info
->vs
.needs_draw_id
= true;
231 case nir_intrinsic_load_instance_id
:
232 info
->vs
.needs_instance_id
= true;
234 case nir_intrinsic_load_num_work_groups
:
235 info
->cs
.uses_grid_size
= true;
237 case nir_intrinsic_load_local_invocation_id
:
238 case nir_intrinsic_load_work_group_id
: {
239 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
241 unsigned i
= u_bit_scan(&mask
);
243 if (instr
->intrinsic
== nir_intrinsic_load_work_group_id
)
244 info
->cs
.uses_block_id
[i
] = true;
246 info
->cs
.uses_thread_id
[i
] = true;
250 case nir_intrinsic_load_local_invocation_index
:
251 case nir_intrinsic_load_subgroup_id
:
252 case nir_intrinsic_load_num_subgroups
:
253 info
->cs
.uses_local_invocation_idx
= true;
255 case nir_intrinsic_load_sample_id
:
256 info
->ps
.force_persample
= true;
258 case nir_intrinsic_load_sample_pos
:
259 info
->ps
.force_persample
= true;
261 case nir_intrinsic_load_view_index
:
262 info
->needs_multiview_view_index
= true;
263 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
264 info
->ps
.layer_input
= true;
266 case nir_intrinsic_load_invocation_id
:
267 info
->uses_invocation_id
= true;
269 case nir_intrinsic_load_primitive_id
:
270 info
->uses_prim_id
= true;
272 case nir_intrinsic_load_push_constant
:
273 gather_push_constant_info(nir
, instr
, info
);
275 case nir_intrinsic_vulkan_resource_index
:
276 info
->desc_set_used_mask
|= (1 << nir_intrinsic_desc_set(instr
));
278 case nir_intrinsic_image_deref_load
:
279 case nir_intrinsic_image_deref_store
:
280 case nir_intrinsic_image_deref_atomic_add
:
281 case nir_intrinsic_image_deref_atomic_min
:
282 case nir_intrinsic_image_deref_atomic_max
:
283 case nir_intrinsic_image_deref_atomic_and
:
284 case nir_intrinsic_image_deref_atomic_or
:
285 case nir_intrinsic_image_deref_atomic_xor
:
286 case nir_intrinsic_image_deref_atomic_exchange
:
287 case nir_intrinsic_image_deref_atomic_comp_swap
:
288 case nir_intrinsic_image_deref_size
: {
289 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
290 const struct glsl_type
*type
= glsl_without_array(var
->type
);
292 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
293 if (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
294 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) {
295 info
->ps
.layer_input
= true;
296 info
->ps
.uses_input_attachments
= true;
298 mark_sampler_desc(var
, info
);
300 if (instr
->intrinsic
== nir_intrinsic_image_deref_store
||
301 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_add
||
302 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_min
||
303 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_max
||
304 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_and
||
305 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_or
||
306 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_xor
||
307 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_exchange
||
308 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
) {
309 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
310 info
->ps
.writes_memory
= true;
314 case nir_intrinsic_store_ssbo
:
315 case nir_intrinsic_ssbo_atomic_add
:
316 case nir_intrinsic_ssbo_atomic_imin
:
317 case nir_intrinsic_ssbo_atomic_umin
:
318 case nir_intrinsic_ssbo_atomic_imax
:
319 case nir_intrinsic_ssbo_atomic_umax
:
320 case nir_intrinsic_ssbo_atomic_and
:
321 case nir_intrinsic_ssbo_atomic_or
:
322 case nir_intrinsic_ssbo_atomic_xor
:
323 case nir_intrinsic_ssbo_atomic_exchange
:
324 case nir_intrinsic_ssbo_atomic_comp_swap
:
325 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
326 info
->ps
.writes_memory
= true;
328 case nir_intrinsic_load_deref
:
329 gather_intrinsic_load_deref_info(nir
, instr
, info
);
331 case nir_intrinsic_store_deref
:
332 gather_intrinsic_store_deref_info(nir
, instr
, info
);
340 gather_tex_info(const nir_shader
*nir
, const nir_tex_instr
*instr
,
341 struct radv_shader_info
*info
)
343 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
344 switch (instr
->src
[i
].src_type
) {
345 case nir_tex_src_texture_deref
:
346 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
348 case nir_tex_src_sampler_deref
:
349 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
358 gather_info_block(const nir_shader
*nir
, const nir_block
*block
,
359 struct radv_shader_info
*info
)
361 nir_foreach_instr(instr
, block
) {
362 switch (instr
->type
) {
363 case nir_instr_type_intrinsic
:
364 gather_intrinsic_info(nir
, nir_instr_as_intrinsic(instr
), info
);
366 case nir_instr_type_tex
:
367 gather_tex_info(nir
, nir_instr_as_tex(instr
), info
);
376 gather_info_input_decl_vs(const nir_shader
*nir
, const nir_variable
*var
,
377 struct radv_shader_info
*info
)
379 int idx
= var
->data
.location
;
381 if (idx
>= VERT_ATTRIB_GENERIC0
&& idx
<= VERT_ATTRIB_GENERIC15
)
382 info
->vs
.has_vertex_buffers
= true;
386 gather_info_input_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
387 struct radv_shader_info
*info
)
389 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
390 const struct glsl_type
*type
= glsl_without_array(var
->type
);
391 int idx
= var
->data
.location
;
394 case VARYING_SLOT_PNTC
:
395 info
->ps
.has_pcoord
= true;
397 case VARYING_SLOT_PRIMITIVE_ID
:
398 info
->ps
.prim_id_input
= true;
400 case VARYING_SLOT_LAYER
:
401 info
->ps
.layer_input
= true;
403 case VARYING_SLOT_CLIP_DIST0
:
404 info
->ps
.num_input_clips_culls
= attrib_count
;
410 if (glsl_get_base_type(type
) == GLSL_TYPE_FLOAT
) {
411 if (var
->data
.sample
)
412 info
->ps
.force_persample
= true;
417 gather_info_input_decl(const nir_shader
*nir
, const nir_variable
*var
,
418 struct radv_shader_info
*info
)
420 switch (nir
->info
.stage
) {
421 case MESA_SHADER_VERTEX
:
422 gather_info_input_decl_vs(nir
, var
, info
);
424 case MESA_SHADER_FRAGMENT
:
425 gather_info_input_decl_ps(nir
, var
, info
);
433 gather_info_output_decl_ls(const nir_shader
*nir
, const nir_variable
*var
,
434 struct radv_shader_info
*info
)
436 int idx
= var
->data
.location
;
437 unsigned param
= shader_io_get_unique_index(idx
);
438 int num_slots
= glsl_count_attribute_slots(var
->type
, false);
439 if (idx
== VARYING_SLOT_CLIP_DIST0
)
440 num_slots
= (nir
->info
.clip_distance_array_size
+ nir
->info
.cull_distance_array_size
> 4) ? 2 : 1;
441 mark_ls_output(info
, param
, num_slots
);
445 gather_info_output_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
446 struct radv_shader_info
*info
)
448 int idx
= var
->data
.location
;
451 case FRAG_RESULT_DEPTH
:
452 info
->ps
.writes_z
= true;
454 case FRAG_RESULT_STENCIL
:
455 info
->ps
.writes_stencil
= true;
457 case FRAG_RESULT_SAMPLE_MASK
:
458 info
->ps
.writes_sample_mask
= true;
466 gather_info_output_decl_gs(const nir_shader
*nir
, const nir_variable
*var
,
467 struct radv_shader_info
*info
)
469 unsigned num_components
= glsl_get_component_slots(var
->type
);
470 unsigned stream
= var
->data
.stream
;
471 unsigned idx
= var
->data
.location
;
475 info
->gs
.max_stream
= MAX2(info
->gs
.max_stream
, stream
);
476 info
->gs
.num_stream_output_components
[stream
] += num_components
;
477 info
->gs
.output_streams
[idx
] = stream
;
481 gather_info_output_decl(const nir_shader
*nir
, const nir_variable
*var
,
482 struct radv_shader_info
*info
,
483 const struct radv_nir_compiler_options
*options
)
485 switch (nir
->info
.stage
) {
486 case MESA_SHADER_FRAGMENT
:
487 gather_info_output_decl_ps(nir
, var
, info
);
489 case MESA_SHADER_VERTEX
:
490 if (options
->key
.vs
.as_ls
)
491 gather_info_output_decl_ls(nir
, var
, info
);
493 case MESA_SHADER_GEOMETRY
:
494 gather_info_output_decl_gs(nir
, var
, info
);
502 gather_xfb_info(const nir_shader
*nir
, struct radv_shader_info
*info
)
504 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
505 struct radv_streamout_info
*so
= &info
->so
;
510 assert(xfb
->output_count
< MAX_SO_OUTPUTS
);
511 so
->num_outputs
= xfb
->output_count
;
513 for (unsigned i
= 0; i
< xfb
->output_count
; i
++) {
514 struct radv_stream_output
*output
= &so
->outputs
[i
];
516 output
->buffer
= xfb
->outputs
[i
].buffer
;
517 output
->stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
518 output
->offset
= xfb
->outputs
[i
].offset
;
519 output
->location
= xfb
->outputs
[i
].location
;
520 output
->component_mask
= xfb
->outputs
[i
].component_mask
;
522 so
->enabled_stream_buffers_mask
|=
523 (1 << output
->buffer
) << (output
->stream
* 4);
527 for (unsigned i
= 0; i
< NIR_MAX_XFB_BUFFERS
; i
++) {
528 so
->strides
[i
] = xfb
->strides
[i
] / 4;
535 radv_nir_shader_info_init(struct radv_shader_info
*info
)
537 /* Assume that shaders only have 32-bit push constants by default. */
538 info
->min_push_constant_used
= UINT8_MAX
;
539 info
->has_only_32bit_push_constants
= true;
543 radv_nir_shader_info_pass(const struct nir_shader
*nir
,
544 const struct radv_nir_compiler_options
*options
,
545 struct radv_shader_info
*info
)
547 struct nir_function
*func
=
548 (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
550 if (options
->layout
&& options
->layout
->dynamic_offset_count
&&
551 (options
->layout
->dynamic_shader_stages
& mesa_to_vk_shader_stage(nir
->info
.stage
))) {
552 info
->loads_push_constants
= true;
555 nir_foreach_variable(variable
, &nir
->inputs
)
556 gather_info_input_decl(nir
, variable
, info
);
558 nir_foreach_block(block
, func
->impl
) {
559 gather_info_block(nir
, block
, info
);
562 nir_foreach_variable(variable
, &nir
->outputs
)
563 gather_info_output_decl(nir
, variable
, info
, options
);
565 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
566 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
567 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
568 gather_xfb_info(nir
, info
);