2 * Copyright © 2017 Red Hat
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "radv_private.h"
24 #include "radv_shader.h"
26 #include "nir/nir_deref.h"
27 #include "nir/nir_xfb_info.h"
29 static void mark_sampler_desc(const nir_variable
*var
,
30 struct radv_shader_info
*info
)
32 info
->desc_set_used_mask
|= (1 << var
->data
.descriptor_set
);
35 static void mark_ls_output(struct radv_shader_info
*info
,
36 uint32_t param
, int num_slots
)
38 uint64_t mask
= (1ull << num_slots
) - 1ull;
39 info
->vs
.ls_outputs_written
|= (mask
<< param
);
42 static void mark_tess_output(struct radv_shader_info
*info
,
43 bool is_patch
, uint32_t param
, int num_slots
)
45 uint64_t mask
= (1ull << num_slots
) - 1ull;
47 info
->tcs
.patch_outputs_written
|= (mask
<< param
);
49 info
->tcs
.outputs_written
|= (mask
<< param
);
53 get_deref_offset(nir_deref_instr
*instr
,
56 nir_variable
*var
= nir_deref_instr_get_variable(instr
);
60 if (var
->data
.compact
) {
61 assert(instr
->deref_type
== nir_deref_type_array
);
62 *const_out
= nir_src_as_uint(instr
->arr
.index
);
66 nir_deref_path_init(&path
, instr
, NULL
);
68 uint32_t const_offset
= 0;
70 for (; path
.path
[idx_lvl
]; ++idx_lvl
) {
71 const struct glsl_type
*parent_type
= path
.path
[idx_lvl
- 1]->type
;
72 if (path
.path
[idx_lvl
]->deref_type
== nir_deref_type_struct
) {
73 unsigned index
= path
.path
[idx_lvl
]->strct
.index
;
75 for (unsigned i
= 0; i
< index
; i
++) {
76 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
77 const_offset
+= glsl_count_attribute_slots(ft
, false);
79 } else if(path
.path
[idx_lvl
]->deref_type
== nir_deref_type_array
) {
80 unsigned size
= glsl_count_attribute_slots(path
.path
[idx_lvl
]->type
, false);
81 if (nir_src_is_const(path
.path
[idx_lvl
]->arr
.index
))
82 const_offset
+= nir_src_as_uint(path
.path
[idx_lvl
]->arr
.index
) * size
;
84 unreachable("Uhandled deref type in get_deref_instr_offset");
87 *const_out
= const_offset
;
89 nir_deref_path_finish(&path
);
93 gather_intrinsic_load_deref_info(const nir_shader
*nir
,
94 const nir_intrinsic_instr
*instr
,
95 struct radv_shader_info
*info
)
97 switch (nir
->info
.stage
) {
98 case MESA_SHADER_VERTEX
: {
99 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
101 if (var
&& var
->data
.mode
== nir_var_shader_in
) {
102 unsigned idx
= var
->data
.location
;
103 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
105 info
->vs
.input_usage_mask
[idx
] |=
106 mask
<< var
->data
.location_frac
;
116 widen_writemask(uint32_t wrmask
)
118 uint32_t new_wrmask
= 0;
119 for(unsigned i
= 0; i
< 4; i
++)
120 new_wrmask
|= (wrmask
& (1 << i
) ? 0x3 : 0x0) << (i
* 2);
125 set_output_usage_mask(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
126 uint8_t *output_usage_mask
)
128 nir_deref_instr
*deref_instr
=
129 nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
);
130 nir_variable
*var
= nir_deref_instr_get_variable(deref_instr
);
131 unsigned attrib_count
= glsl_count_attribute_slots(deref_instr
->type
, false);
132 unsigned idx
= var
->data
.location
;
133 unsigned comp
= var
->data
.location_frac
;
134 unsigned const_offset
= 0;
136 get_deref_offset(deref_instr
, &const_offset
);
138 if (var
->data
.compact
) {
139 assert(!glsl_type_is_64bit(deref_instr
->type
));
140 const_offset
+= comp
;
141 output_usage_mask
[idx
+ const_offset
/ 4] |= 1 << (const_offset
% 4);
145 uint32_t wrmask
= nir_intrinsic_write_mask(instr
);
146 if (glsl_type_is_64bit(deref_instr
->type
))
147 wrmask
= widen_writemask(wrmask
);
149 for (unsigned i
= 0; i
< attrib_count
; i
++)
150 output_usage_mask
[idx
+ i
+ const_offset
] |=
151 ((wrmask
>> (i
* 4)) & 0xf) << comp
;
155 gather_intrinsic_store_deref_info(const nir_shader
*nir
,
156 const nir_intrinsic_instr
*instr
,
157 struct radv_shader_info
*info
)
159 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
161 if (var
&& var
->data
.mode
== nir_var_shader_out
) {
162 unsigned idx
= var
->data
.location
;
164 switch (nir
->info
.stage
) {
165 case MESA_SHADER_VERTEX
:
166 set_output_usage_mask(nir
, instr
,
167 info
->vs
.output_usage_mask
);
169 case MESA_SHADER_GEOMETRY
:
170 set_output_usage_mask(nir
, instr
,
171 info
->gs
.output_usage_mask
);
173 case MESA_SHADER_TESS_EVAL
:
174 set_output_usage_mask(nir
, instr
,
175 info
->tes
.output_usage_mask
);
177 case MESA_SHADER_TESS_CTRL
: {
178 unsigned param
= shader_io_get_unique_index(idx
);
179 const struct glsl_type
*type
= var
->type
;
181 if (!var
->data
.patch
)
182 type
= glsl_get_array_element(var
->type
);
185 var
->data
.compact
? DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(type
), 4)
186 : glsl_count_attribute_slots(type
, false);
188 mark_tess_output(info
, var
->data
.patch
, param
, slots
);
198 gather_push_constant_info(const nir_shader
*nir
,
199 const nir_intrinsic_instr
*instr
,
200 struct radv_shader_info
*info
)
202 int base
= nir_intrinsic_base(instr
);
204 if (!nir_src_is_const(instr
->src
[0])) {
205 info
->has_indirect_push_constants
= true;
207 uint32_t min
= base
+ nir_src_as_uint(instr
->src
[0]);
208 uint32_t max
= min
+ instr
->num_components
* 4;
210 info
->max_push_constant_used
=
211 MAX2(max
, info
->max_push_constant_used
);
212 info
->min_push_constant_used
=
213 MIN2(min
, info
->min_push_constant_used
);
216 if (instr
->dest
.ssa
.bit_size
!= 32)
217 info
->has_only_32bit_push_constants
= false;
219 info
->loads_push_constants
= true;
223 gather_intrinsic_info(const nir_shader
*nir
, const nir_intrinsic_instr
*instr
,
224 struct radv_shader_info
*info
)
226 switch (instr
->intrinsic
) {
227 case nir_intrinsic_interp_deref_at_sample
:
228 info
->ps
.needs_sample_positions
= true;
230 case nir_intrinsic_load_draw_id
:
231 info
->vs
.needs_draw_id
= true;
233 case nir_intrinsic_load_instance_id
:
234 info
->vs
.needs_instance_id
= true;
236 case nir_intrinsic_load_num_work_groups
:
237 info
->cs
.uses_grid_size
= true;
239 case nir_intrinsic_load_local_invocation_id
:
240 case nir_intrinsic_load_work_group_id
: {
241 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
243 unsigned i
= u_bit_scan(&mask
);
245 if (instr
->intrinsic
== nir_intrinsic_load_work_group_id
)
246 info
->cs
.uses_block_id
[i
] = true;
248 info
->cs
.uses_thread_id
[i
] = true;
252 case nir_intrinsic_load_local_invocation_index
:
253 case nir_intrinsic_load_subgroup_id
:
254 case nir_intrinsic_load_num_subgroups
:
255 info
->cs
.uses_local_invocation_idx
= true;
257 case nir_intrinsic_load_sample_id
:
258 info
->ps
.force_persample
= true;
260 case nir_intrinsic_load_sample_pos
:
261 info
->ps
.force_persample
= true;
263 case nir_intrinsic_load_view_index
:
264 info
->needs_multiview_view_index
= true;
265 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
266 info
->ps
.layer_input
= true;
268 case nir_intrinsic_load_invocation_id
:
269 info
->uses_invocation_id
= true;
271 case nir_intrinsic_load_primitive_id
:
272 info
->uses_prim_id
= true;
274 case nir_intrinsic_load_push_constant
:
275 gather_push_constant_info(nir
, instr
, info
);
277 case nir_intrinsic_vulkan_resource_index
:
278 info
->desc_set_used_mask
|= (1 << nir_intrinsic_desc_set(instr
));
280 case nir_intrinsic_image_deref_load
:
281 case nir_intrinsic_image_deref_store
:
282 case nir_intrinsic_image_deref_atomic_add
:
283 case nir_intrinsic_image_deref_atomic_min
:
284 case nir_intrinsic_image_deref_atomic_max
:
285 case nir_intrinsic_image_deref_atomic_and
:
286 case nir_intrinsic_image_deref_atomic_or
:
287 case nir_intrinsic_image_deref_atomic_xor
:
288 case nir_intrinsic_image_deref_atomic_exchange
:
289 case nir_intrinsic_image_deref_atomic_comp_swap
:
290 case nir_intrinsic_image_deref_size
: {
291 nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
292 const struct glsl_type
*type
= glsl_without_array(var
->type
);
294 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
295 if (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
296 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) {
297 info
->ps
.layer_input
= true;
298 info
->ps
.uses_input_attachments
= true;
300 mark_sampler_desc(var
, info
);
302 if (instr
->intrinsic
== nir_intrinsic_image_deref_store
||
303 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_add
||
304 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_min
||
305 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_max
||
306 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_and
||
307 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_or
||
308 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_xor
||
309 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_exchange
||
310 instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
) {
311 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
312 info
->ps
.writes_memory
= true;
316 case nir_intrinsic_store_ssbo
:
317 case nir_intrinsic_ssbo_atomic_add
:
318 case nir_intrinsic_ssbo_atomic_imin
:
319 case nir_intrinsic_ssbo_atomic_umin
:
320 case nir_intrinsic_ssbo_atomic_imax
:
321 case nir_intrinsic_ssbo_atomic_umax
:
322 case nir_intrinsic_ssbo_atomic_and
:
323 case nir_intrinsic_ssbo_atomic_or
:
324 case nir_intrinsic_ssbo_atomic_xor
:
325 case nir_intrinsic_ssbo_atomic_exchange
:
326 case nir_intrinsic_ssbo_atomic_comp_swap
:
327 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
328 info
->ps
.writes_memory
= true;
330 case nir_intrinsic_load_deref
:
331 gather_intrinsic_load_deref_info(nir
, instr
, info
);
333 case nir_intrinsic_store_deref
:
334 gather_intrinsic_store_deref_info(nir
, instr
, info
);
342 gather_tex_info(const nir_shader
*nir
, const nir_tex_instr
*instr
,
343 struct radv_shader_info
*info
)
345 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
346 switch (instr
->src
[i
].src_type
) {
347 case nir_tex_src_texture_deref
:
348 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
350 case nir_tex_src_sampler_deref
:
351 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
)), info
);
360 gather_info_block(const nir_shader
*nir
, const nir_block
*block
,
361 struct radv_shader_info
*info
)
363 nir_foreach_instr(instr
, block
) {
364 switch (instr
->type
) {
365 case nir_instr_type_intrinsic
:
366 gather_intrinsic_info(nir
, nir_instr_as_intrinsic(instr
), info
);
368 case nir_instr_type_tex
:
369 gather_tex_info(nir
, nir_instr_as_tex(instr
), info
);
378 gather_info_input_decl_vs(const nir_shader
*nir
, const nir_variable
*var
,
379 struct radv_shader_info
*info
)
381 int idx
= var
->data
.location
;
383 if (idx
>= VERT_ATTRIB_GENERIC0
&& idx
<= VERT_ATTRIB_GENERIC15
)
384 info
->vs
.has_vertex_buffers
= true;
388 gather_info_input_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
389 struct radv_shader_info
*info
)
391 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
392 const struct glsl_type
*type
= glsl_without_array(var
->type
);
393 int idx
= var
->data
.location
;
396 case VARYING_SLOT_PNTC
:
397 info
->ps
.has_pcoord
= true;
399 case VARYING_SLOT_PRIMITIVE_ID
:
400 info
->ps
.prim_id_input
= true;
402 case VARYING_SLOT_LAYER
:
403 info
->ps
.layer_input
= true;
405 case VARYING_SLOT_CLIP_DIST0
:
406 case VARYING_SLOT_CLIP_DIST1
:
407 info
->ps
.num_input_clips_culls
+= attrib_count
;
413 if (glsl_get_base_type(type
) == GLSL_TYPE_FLOAT
) {
414 if (var
->data
.sample
)
415 info
->ps
.force_persample
= true;
420 gather_info_input_decl(const nir_shader
*nir
, const nir_variable
*var
,
421 struct radv_shader_info
*info
)
423 switch (nir
->info
.stage
) {
424 case MESA_SHADER_VERTEX
:
425 gather_info_input_decl_vs(nir
, var
, info
);
427 case MESA_SHADER_FRAGMENT
:
428 gather_info_input_decl_ps(nir
, var
, info
);
436 gather_info_output_decl_ls(const nir_shader
*nir
, const nir_variable
*var
,
437 struct radv_shader_info
*info
)
439 int idx
= var
->data
.location
;
440 unsigned param
= shader_io_get_unique_index(idx
);
441 int num_slots
= glsl_count_attribute_slots(var
->type
, false);
442 if (var
->data
.compact
)
443 num_slots
= DIV_ROUND_UP(var
->data
.location_frac
+ glsl_get_length(var
->type
), 4);
444 mark_ls_output(info
, param
, num_slots
);
448 gather_info_output_decl_ps(const nir_shader
*nir
, const nir_variable
*var
,
449 struct radv_shader_info
*info
)
451 int idx
= var
->data
.location
;
454 case FRAG_RESULT_DEPTH
:
455 info
->ps
.writes_z
= true;
457 case FRAG_RESULT_STENCIL
:
458 info
->ps
.writes_stencil
= true;
460 case FRAG_RESULT_SAMPLE_MASK
:
461 info
->ps
.writes_sample_mask
= true;
469 gather_info_output_decl_gs(const nir_shader
*nir
, const nir_variable
*var
,
470 struct radv_shader_info
*info
)
472 unsigned num_components
= glsl_get_component_slots(var
->type
);
473 unsigned stream
= var
->data
.stream
;
474 unsigned idx
= var
->data
.location
;
478 info
->gs
.max_stream
= MAX2(info
->gs
.max_stream
, stream
);
479 info
->gs
.num_stream_output_components
[stream
] += num_components
;
480 info
->gs
.output_streams
[idx
] = stream
;
484 gather_info_output_decl(const nir_shader
*nir
, const nir_variable
*var
,
485 struct radv_shader_info
*info
,
486 const struct radv_nir_compiler_options
*options
)
488 switch (nir
->info
.stage
) {
489 case MESA_SHADER_FRAGMENT
:
490 gather_info_output_decl_ps(nir
, var
, info
);
492 case MESA_SHADER_VERTEX
:
493 if (options
->key
.vs
.as_ls
)
494 gather_info_output_decl_ls(nir
, var
, info
);
496 case MESA_SHADER_GEOMETRY
:
497 gather_info_output_decl_gs(nir
, var
, info
);
505 gather_xfb_info(const nir_shader
*nir
, struct radv_shader_info
*info
)
507 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
508 struct radv_streamout_info
*so
= &info
->so
;
513 assert(xfb
->output_count
< MAX_SO_OUTPUTS
);
514 so
->num_outputs
= xfb
->output_count
;
516 for (unsigned i
= 0; i
< xfb
->output_count
; i
++) {
517 struct radv_stream_output
*output
= &so
->outputs
[i
];
519 output
->buffer
= xfb
->outputs
[i
].buffer
;
520 output
->stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
521 output
->offset
= xfb
->outputs
[i
].offset
;
522 output
->location
= xfb
->outputs
[i
].location
;
523 output
->component_mask
= xfb
->outputs
[i
].component_mask
;
525 so
->enabled_stream_buffers_mask
|=
526 (1 << output
->buffer
) << (output
->stream
* 4);
530 for (unsigned i
= 0; i
< NIR_MAX_XFB_BUFFERS
; i
++) {
531 so
->strides
[i
] = xfb
->buffers
[i
].stride
/ 4;
538 radv_nir_shader_info_init(struct radv_shader_info
*info
)
540 /* Assume that shaders only have 32-bit push constants by default. */
541 info
->min_push_constant_used
= UINT8_MAX
;
542 info
->has_only_32bit_push_constants
= true;
546 radv_nir_shader_info_pass(const struct nir_shader
*nir
,
547 const struct radv_nir_compiler_options
*options
,
548 struct radv_shader_info
*info
)
550 struct nir_function
*func
=
551 (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
553 if (options
->layout
&& options
->layout
->dynamic_offset_count
&&
554 (options
->layout
->dynamic_shader_stages
& mesa_to_vk_shader_stage(nir
->info
.stage
))) {
555 info
->loads_push_constants
= true;
556 info
->loads_dynamic_offsets
= true;
559 nir_foreach_variable(variable
, &nir
->inputs
)
560 gather_info_input_decl(nir
, variable
, info
);
562 nir_foreach_block(block
, func
->impl
) {
563 gather_info_block(nir
, block
, info
);
566 nir_foreach_variable(variable
, &nir
->outputs
)
567 gather_info_output_decl(nir
, variable
, info
, options
);
569 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
570 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
571 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
572 gather_xfb_info(nir
, info
);