src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26 #include "nir/nir_deref.h"
  27 #include "nir/nir_xfb_info.h"
  28
  29 static void mark_sampler_desc(const nir_variable *var,
  30                               struct radv_shader_info *info)
  31 {
  32         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  33 }
  34
  35 static void mark_ls_output(struct radv_shader_info *info,
  36                            uint32_t param, int num_slots)
  37 {
  38         uint64_t mask = (1ull << num_slots) - 1ull;
  39         info->vs.ls_outputs_written |= (mask << param);
  40 }
  41
  42 static void mark_tess_output(struct radv_shader_info *info,
  43                              bool is_patch, uint32_t param, int num_slots)
  44 {
  45         uint64_t mask = (1ull << num_slots) - 1ull;
  46         if (is_patch)
  47                 info->tcs.patch_outputs_written |= (mask << param);
  48         else
  49                 info->tcs.outputs_written |= (mask << param);
  50 }
  51
  52 static void
  53 get_deref_offset(nir_deref_instr *instr,
  54                  unsigned *const_out)
  55 {
  56         nir_variable *var = nir_deref_instr_get_variable(instr);
  57         nir_deref_path path;
  58         unsigned idx_lvl = 1;
  59
  60         if (var->data.compact) {
  61                 assert(instr->deref_type == nir_deref_type_array);
  62                 nir_const_value *v = nir_src_as_const_value(instr->arr.index);
  63                 assert(v);
  64                 *const_out = v->u32[0];
  65                 return;
  66         }
  67
  68         nir_deref_path_init(&path, instr, NULL);
  69
  70         uint32_t const_offset = 0;
  71
  72         for (; path.path[idx_lvl]; ++idx_lvl) {
  73                 const struct glsl_type *parent_type = path.path[idx_lvl - 1]->type;
  74                 if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
  75                         unsigned index = path.path[idx_lvl]->strct.index;
  76
  77                         for (unsigned i = 0; i < index; i++) {
  78                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  79                                 const_offset += glsl_count_attribute_slots(ft, false);
  80                         }
  81                 } else if(path.path[idx_lvl]->deref_type == nir_deref_type_array) {
  82                         unsigned size = glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
  83                         nir_const_value *v = nir_src_as_const_value(path.path[idx_lvl]->arr.index);
  84                         if (v)
  85                                 const_offset += v->u32[0] * size;
  86                 } else
  87                         unreachable("Uhandled deref type in get_deref_instr_offset");
  88         }
  89
  90         *const_out = const_offset;
  91
  92         nir_deref_path_finish(&path);
  93 }
  94
  95 static void
  96 gather_intrinsic_load_deref_info(const nir_shader *nir,
  97                                const nir_intrinsic_instr *instr,
  98                                struct radv_shader_info *info)
  99 {
 100         switch (nir->info.stage) {
 101         case MESA_SHADER_VERTEX: {
 102                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 103
 104                 if (var && var->data.mode == nir_var_shader_in) {
 105                         unsigned idx = var->data.location;
 106                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 107
 108                         info->vs.input_usage_mask[idx] |=
 109                                 mask << var->data.location_frac;
 110                 }
 111                 break;
 112         }
 113         default:
 114                 break;
 115         }
 116 }
 117
 118 static void
 119 set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 120                       uint8_t *output_usage_mask)
 121 {
 122         nir_deref_instr *deref_instr =
 123                 nir_instr_as_deref(instr->src[0].ssa->parent_instr);
 124         nir_variable *var = nir_deref_instr_get_variable(deref_instr);
 125         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 126         unsigned idx = var->data.location;
 127         unsigned comp = var->data.location_frac;
 128         unsigned const_offset = 0;
 129
 130         get_deref_offset(deref_instr, &const_offset);
 131
 132         if (var->data.compact) {
 133                 const_offset += comp;
 134                 output_usage_mask[idx + const_offset / 4] |= 1 << (const_offset % 4);
 135                 return;
 136         }
 137
 138         for (unsigned i = 0; i < attrib_count; i++) {
 139                 output_usage_mask[idx + i + const_offset] |=
 140                         instr->const_index[0] << comp;
 141         }
 142 }
 143
 144 static void
 145 gather_intrinsic_store_deref_info(const nir_shader *nir,
 146                                 const nir_intrinsic_instr *instr,
 147                                 struct radv_shader_info *info)
 148 {
 149         nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 150
 151         if (var && var->data.mode == nir_var_shader_out) {
 152                 unsigned idx = var->data.location;
 153
 154                 switch (nir->info.stage) {
 155                 case MESA_SHADER_VERTEX:
 156                         set_output_usage_mask(nir, instr,
 157                                               info->vs.output_usage_mask);
 158                         break;
 159                 case MESA_SHADER_GEOMETRY:
 160                         set_output_usage_mask(nir, instr,
 161                                               info->gs.output_usage_mask);
 162                         break;
 163                 case MESA_SHADER_TESS_EVAL:
 164                         set_output_usage_mask(nir, instr,
 165                                               info->tes.output_usage_mask);
 166                         break;
 167                 case MESA_SHADER_TESS_CTRL: {
 168                         unsigned param = shader_io_get_unique_index(idx);
 169                         const struct glsl_type *type = var->type;
 170
 171                         if (!var->data.patch)
 172                                 type = glsl_get_array_element(var->type);
 173
 174                         unsigned slots =
 175                                 var->data.compact ? DIV_ROUND_UP(var->data.location_frac + glsl_get_length(type), 4)
 176                                                   : glsl_count_attribute_slots(type, false);
 177
 178                         mark_tess_output(info, var->data.patch, param, slots);
 179                         break;
 180                 }
 181                 default:
 182                         break;
 183                 }
 184         }
 185 }
 186
 187 static void
 188 gather_push_constant_info(const nir_shader *nir,
 189                           const nir_intrinsic_instr *instr,
 190                           struct radv_shader_info *info)
 191 {
 192         nir_const_value *cval = nir_src_as_const_value(instr->src[0]);
 193         int base = nir_intrinsic_base(instr);
 194
 195         if (!cval) {
 196                 info->has_indirect_push_constants = true;
 197         } else {
 198                 uint32_t min = base + cval->u32[0];
 199                 uint32_t max = min + instr->num_components * 4;
 200
 201                 info->max_push_constant_used =
 202                         MAX2(max, info->max_push_constant_used);
 203                 info->min_push_constant_used =
 204                         MIN2(min, info->min_push_constant_used);
 205         }
 206
 207         if (instr->dest.ssa.bit_size != 32)
 208                 info->has_only_32bit_push_constants = false;
 209
 210         info->loads_push_constants = true;
 211 }
 212
 213 static void
 214 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 215                       struct radv_shader_info *info)
 216 {
 217         switch (instr->intrinsic) {
 218         case nir_intrinsic_interp_deref_at_sample:
 219                 info->ps.needs_sample_positions = true;
 220                 break;
 221         case nir_intrinsic_load_draw_id:
 222                 info->vs.needs_draw_id = true;
 223                 break;
 224         case nir_intrinsic_load_instance_id:
 225                 info->vs.needs_instance_id = true;
 226                 break;
 227         case nir_intrinsic_load_num_work_groups:
 228                 info->cs.uses_grid_size = true;
 229                 break;
 230         case nir_intrinsic_load_local_invocation_id:
 231         case nir_intrinsic_load_work_group_id: {
 232                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 233                 while (mask) {
 234                         unsigned i = u_bit_scan(&mask);
 235
 236                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 237                                 info->cs.uses_block_id[i] = true;
 238                         else
 239                                 info->cs.uses_thread_id[i] = true;
 240                 }
 241                 break;
 242         }
 243         case nir_intrinsic_load_local_invocation_index:
 244         case nir_intrinsic_load_subgroup_id:
 245         case nir_intrinsic_load_num_subgroups:
 246                 info->cs.uses_local_invocation_idx = true;
 247                 break;
 248         case nir_intrinsic_load_sample_id:
 249                 info->ps.force_persample = true;
 250                 break;
 251         case nir_intrinsic_load_sample_pos:
 252                 info->ps.force_persample = true;
 253                 break;
 254         case nir_intrinsic_load_view_index:
 255                 info->needs_multiview_view_index = true;
 256                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 257                         info->ps.layer_input = true;
 258                 break;
 259         case nir_intrinsic_load_invocation_id:
 260                 info->uses_invocation_id = true;
 261                 break;
 262         case nir_intrinsic_load_primitive_id:
 263                 info->uses_prim_id = true;
 264                 break;
 265         case nir_intrinsic_load_push_constant:
 266                 gather_push_constant_info(nir, instr, info);
 267                 break;
 268         case nir_intrinsic_vulkan_resource_index:
 269                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 270                 break;
 271         case nir_intrinsic_image_deref_load:
 272         case nir_intrinsic_image_deref_store:
 273         case nir_intrinsic_image_deref_atomic_add:
 274         case nir_intrinsic_image_deref_atomic_min:
 275         case nir_intrinsic_image_deref_atomic_max:
 276         case nir_intrinsic_image_deref_atomic_and:
 277         case nir_intrinsic_image_deref_atomic_or:
 278         case nir_intrinsic_image_deref_atomic_xor:
 279         case nir_intrinsic_image_deref_atomic_exchange:
 280         case nir_intrinsic_image_deref_atomic_comp_swap:
 281         case nir_intrinsic_image_deref_size: {
 282                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 283                 const struct glsl_type *type = glsl_without_array(var->type);
 284
 285                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 286                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 287                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 288                         info->ps.layer_input = true;
 289                         info->ps.uses_input_attachments = true;
 290                 }
 291                 mark_sampler_desc(var, info);
 292
 293                 if (instr->intrinsic == nir_intrinsic_image_deref_store ||
 294                     instr->intrinsic == nir_intrinsic_image_deref_atomic_add ||
 295                     instr->intrinsic == nir_intrinsic_image_deref_atomic_min ||
 296                     instr->intrinsic == nir_intrinsic_image_deref_atomic_max ||
 297                     instr->intrinsic == nir_intrinsic_image_deref_atomic_and ||
 298                     instr->intrinsic == nir_intrinsic_image_deref_atomic_or ||
 299                     instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
 300                     instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange ||
 301                     instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
 302                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 303                                 info->ps.writes_memory = true;
 304                 }
 305                 break;
 306         }
 307         case nir_intrinsic_store_ssbo:
 308         case nir_intrinsic_ssbo_atomic_add:
 309         case nir_intrinsic_ssbo_atomic_imin:
 310         case nir_intrinsic_ssbo_atomic_umin:
 311         case nir_intrinsic_ssbo_atomic_imax:
 312         case nir_intrinsic_ssbo_atomic_umax:
 313         case nir_intrinsic_ssbo_atomic_and:
 314         case nir_intrinsic_ssbo_atomic_or:
 315         case nir_intrinsic_ssbo_atomic_xor:
 316         case nir_intrinsic_ssbo_atomic_exchange:
 317         case nir_intrinsic_ssbo_atomic_comp_swap:
 318                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 319                         info->ps.writes_memory = true;
 320                 break;
 321         case nir_intrinsic_load_deref:
 322                 gather_intrinsic_load_deref_info(nir, instr, info);
 323                 break;
 324         case nir_intrinsic_store_deref:
 325                 gather_intrinsic_store_deref_info(nir, instr, info);
 326                 break;
 327         default:
 328                 break;
 329         }
 330 }
 331
 332 static void
 333 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 334                 struct radv_shader_info *info)
 335 {
 336         for (unsigned i = 0; i < instr->num_srcs; i++) {
 337                 switch (instr->src[i].src_type) {
 338                 case nir_tex_src_texture_deref:
 339                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 340                         break;
 341                 case nir_tex_src_sampler_deref:
 342                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 343                         break;
 344                 default:
 345                         break;
 346                 }
 347         }
 348 }
 349
 350 static void
 351 gather_info_block(const nir_shader *nir, const nir_block *block,
 352                   struct radv_shader_info *info)
 353 {
 354         nir_foreach_instr(instr, block) {
 355                 switch (instr->type) {
 356                 case nir_instr_type_intrinsic:
 357                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 358                         break;
 359                 case nir_instr_type_tex:
 360                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 361                         break;
 362                 default:
 363                         break;
 364                 }
 365         }
 366 }
 367
 368 static void
 369 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 370                           struct radv_shader_info *info)
 371 {
 372         int idx = var->data.location;
 373
 374         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 375                 info->vs.has_vertex_buffers = true;
 376 }
 377
 378 static void
 379 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 380                           struct radv_shader_info *info)
 381 {
 382         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 383         const struct glsl_type *type = glsl_without_array(var->type);
 384         int idx = var->data.location;
 385
 386         switch (idx) {
 387         case VARYING_SLOT_PNTC:
 388                 info->ps.has_pcoord = true;
 389                 break;
 390         case VARYING_SLOT_PRIMITIVE_ID:
 391                 info->ps.prim_id_input = true;
 392                 break;
 393         case VARYING_SLOT_LAYER:
 394                 info->ps.layer_input = true;
 395                 break;
 396         case VARYING_SLOT_CLIP_DIST0:
 397         case VARYING_SLOT_CLIP_DIST1:
 398                 info->ps.num_input_clips_culls += attrib_count;
 399                 break;
 400         default:
 401                 break;
 402         }
 403
 404         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 405                 if (var->data.sample)
 406                         info->ps.force_persample = true;
 407         }
 408 }
 409
 410 static void
 411 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 412                        struct radv_shader_info *info)
 413 {
 414         switch (nir->info.stage) {
 415         case MESA_SHADER_VERTEX:
 416                 gather_info_input_decl_vs(nir, var, info);
 417                 break;
 418         case MESA_SHADER_FRAGMENT:
 419                 gather_info_input_decl_ps(nir, var, info);
 420                 break;
 421         default:
 422                 break;
 423         }
 424 }
 425
 426 static void
 427 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 428                            struct radv_shader_info *info)
 429 {
 430         int idx = var->data.location;
 431         unsigned param = shader_io_get_unique_index(idx);
 432         int num_slots = glsl_count_attribute_slots(var->type, false);
 433         if (var->data.compact)
 434                 num_slots = DIV_ROUND_UP(var->data.location_frac + glsl_get_length(var->type), 4);
 435         mark_ls_output(info, param, num_slots);
 436 }
 437
 438 static void
 439 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 440                            struct radv_shader_info *info)
 441 {
 442         int idx = var->data.location;
 443
 444         switch (idx) {
 445         case FRAG_RESULT_DEPTH:
 446                 info->ps.writes_z = true;
 447                 break;
 448         case FRAG_RESULT_STENCIL:
 449                 info->ps.writes_stencil = true;
 450                 break;
 451         case FRAG_RESULT_SAMPLE_MASK:
 452                 info->ps.writes_sample_mask = true;
 453                 break;
 454         default:
 455                 break;
 456         }
 457 }
 458
 459 static void
 460 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
 461                            struct radv_shader_info *info)
 462 {
 463         unsigned num_components = glsl_get_component_slots(var->type);
 464         unsigned stream = var->data.stream;
 465         unsigned idx = var->data.location;
 466
 467         assert(stream < 4);
 468
 469         info->gs.max_stream = MAX2(info->gs.max_stream, stream);
 470         info->gs.num_stream_output_components[stream] += num_components;
 471         info->gs.output_streams[idx] = stream;
 472 }
 473
 474 static void
 475 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 476                         struct radv_shader_info *info,
 477                         const struct radv_nir_compiler_options *options)
 478 {
 479         switch (nir->info.stage) {
 480         case MESA_SHADER_FRAGMENT:
 481                 gather_info_output_decl_ps(nir, var, info);
 482                 break;
 483         case MESA_SHADER_VERTEX:
 484                 if (options->key.vs.as_ls)
 485                         gather_info_output_decl_ls(nir, var, info);
 486                 break;
 487         case MESA_SHADER_GEOMETRY:
 488                 gather_info_output_decl_gs(nir, var, info);
 489                 break;
 490         default:
 491                 break;
 492         }
 493 }
 494
 495 static void
 496 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
 497 {
 498         nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 499         struct radv_streamout_info *so = &info->so;
 500
 501         if (!xfb)
 502                 return;
 503
 504         assert(xfb->output_count < MAX_SO_OUTPUTS);
 505         so->num_outputs = xfb->output_count;
 506
 507         for (unsigned i = 0; i < xfb->output_count; i++) {
 508                 struct radv_stream_output *output = &so->outputs[i];
 509
 510                 output->buffer = xfb->outputs[i].buffer;
 511                 output->stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 512                 output->offset = xfb->outputs[i].offset;
 513                 output->location = xfb->outputs[i].location;
 514                 output->component_mask = xfb->outputs[i].component_mask;
 515
 516                 so->enabled_stream_buffers_mask |=
 517                         (1 << output->buffer) << (output->stream * 4);
 518
 519         }
 520
 521         for (unsigned i = 0; i < NIR_MAX_XFB_BUFFERS; i++) {
 522                 so->strides[i] = xfb->strides[i] / 4;
 523         }
 524
 525         ralloc_free(xfb);
 526 }
 527
 528 void
 529 radv_nir_shader_info_init(struct radv_shader_info *info)
 530 {
 531         /* Assume that shaders only have 32-bit push constants by default. */
 532         info->min_push_constant_used = UINT8_MAX;
 533         info->has_only_32bit_push_constants = true;
 534 }
 535
 536 void
 537 radv_nir_shader_info_pass(const struct nir_shader *nir,
 538                           const struct radv_nir_compiler_options *options,
 539                           struct radv_shader_info *info)
 540 {
 541         struct nir_function *func =
 542                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 543
 544         if (options->layout && options->layout->dynamic_offset_count &&
 545             (options->layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
 546                 info->loads_push_constants = true;
 547                 info->loads_dynamic_offsets = true;
 548         }
 549
 550         nir_foreach_variable(variable, &nir->inputs)
 551                 gather_info_input_decl(nir, variable, info);
 552
 553         nir_foreach_block(block, func->impl) {
 554                 gather_info_block(nir, block, info);
 555         }
 556
 557         nir_foreach_variable(variable, &nir->outputs)
 558                 gather_info_output_decl(nir, variable, info, options);
 559
 560         if (nir->info.stage == MESA_SHADER_VERTEX ||
 561             nir->info.stage == MESA_SHADER_TESS_EVAL ||
 562             nir->info.stage == MESA_SHADER_GEOMETRY)
 563                 gather_xfb_info(nir, info);
 564 }