src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26 #include "nir/nir_deref.h"
  27
  28 static void mark_sampler_desc(const nir_variable *var,
  29                               struct radv_shader_info *info)
  30 {
  31         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  32 }
  33
  34 static void mark_ls_output(struct radv_shader_info *info,
  35                            uint32_t param, int num_slots)
  36 {
  37         uint64_t mask = (1ull << num_slots) - 1ull;
  38         info->vs.ls_outputs_written |= (mask << param);
  39 }
  40
  41 static void mark_tess_output(struct radv_shader_info *info,
  42                              bool is_patch, uint32_t param, int num_slots)
  43 {
  44         uint64_t mask = (1ull << num_slots) - 1ull;
  45         if (is_patch)
  46                 info->tcs.patch_outputs_written |= (mask << param);
  47         else
  48                 info->tcs.outputs_written |= (mask << param);
  49 }
  50
  51 static void
  52 get_deref_offset(nir_deref_instr *instr,
  53                  unsigned *const_out)
  54 {
  55         nir_variable *var = nir_deref_instr_get_variable(instr);
  56         nir_deref_path path;
  57         unsigned idx_lvl = 1;
  58
  59         if (var->data.compact) {
  60                 assert(instr->deref_type == nir_deref_type_array);
  61                 nir_const_value *v = nir_src_as_const_value(instr->arr.index);
  62                 assert(v);
  63                 *const_out = v->u32[0];
  64                 return;
  65         }
  66
  67         nir_deref_path_init(&path, instr, NULL);
  68
  69         uint32_t const_offset = 0;
  70
  71         for (; path.path[idx_lvl]; ++idx_lvl) {
  72                 const struct glsl_type *parent_type = path.path[idx_lvl - 1]->type;
  73                 if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
  74                         unsigned index = path.path[idx_lvl]->strct.index;
  75
  76                         for (unsigned i = 0; i < index; i++) {
  77                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  78                                 const_offset += glsl_count_attribute_slots(ft, false);
  79                         }
  80                 } else if(path.path[idx_lvl]->deref_type == nir_deref_type_array) {
  81                         unsigned size = glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
  82                         nir_const_value *v = nir_src_as_const_value(path.path[idx_lvl]->arr.index);
  83                         if (v)
  84                                 const_offset += v->u32[0] * size;
  85                 } else
  86                         unreachable("Uhandled deref type in get_deref_instr_offset");
  87         }
  88
  89         *const_out = const_offset;
  90
  91         nir_deref_path_finish(&path);
  92 }
  93
  94 static void
  95 gather_intrinsic_load_deref_info(const nir_shader *nir,
  96                                const nir_intrinsic_instr *instr,
  97                                struct radv_shader_info *info)
  98 {
  99         switch (nir->info.stage) {
 100         case MESA_SHADER_VERTEX: {
 101                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 102
 103                 if (var->data.mode == nir_var_shader_in) {
 104                         unsigned idx = var->data.location;
 105                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 106
 107                         info->vs.input_usage_mask[idx] |=
 108                                 mask << var->data.location_frac;
 109                 }
 110                 break;
 111         }
 112         default:
 113                 break;
 114         }
 115 }
 116
 117 static void
 118 gather_intrinsic_store_deref_info(const nir_shader *nir,
 119                                 const nir_intrinsic_instr *instr,
 120                                 struct radv_shader_info *info)
 121 {
 122         nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 123
 124         if (var->data.mode == nir_var_shader_out) {
 125                 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 126                 unsigned idx = var->data.location;
 127                 unsigned comp = var->data.location_frac;
 128                 unsigned const_offset = 0;
 129
 130                 get_deref_offset(nir_instr_as_deref(instr->src[0].ssa->parent_instr), &const_offset);
 131
 132                 switch (nir->info.stage) {
 133                 case MESA_SHADER_VERTEX:
 134                         for (unsigned i = 0; i < attrib_count; i++) {
 135                                 info->vs.output_usage_mask[idx + i + const_offset] |=
 136                                         instr->const_index[0] << comp;
 137                         }
 138                         break;
 139                 case MESA_SHADER_GEOMETRY:
 140                         for (unsigned i = 0; i < attrib_count; i++) {
 141                                 info->gs.output_usage_mask[idx + i + const_offset] |=
 142                                         instr->const_index[0] << comp;
 143                         }
 144                         break;
 145                 case MESA_SHADER_TESS_EVAL:
 146                         for (unsigned i = 0; i < attrib_count; i++) {
 147                                 info->tes.output_usage_mask[idx + i + const_offset] |=
 148                                         instr->const_index[0] << comp;
 149                         }
 150                         break;
 151                 case MESA_SHADER_TESS_CTRL: {
 152                         unsigned param = shader_io_get_unique_index(idx);
 153                         const struct glsl_type *type = var->type;
 154
 155                         if (!var->data.patch)
 156                                 type = glsl_get_array_element(var->type);
 157
 158                         unsigned slots =
 159                                 var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 160                                                   : glsl_count_attribute_slots(type, false);
 161
 162                         if (idx == VARYING_SLOT_CLIP_DIST0)
 163                                 slots = (nir->info.clip_distance_array_size +
 164                                          nir->info.cull_distance_array_size > 4) ? 2 : 1;
 165
 166                         mark_tess_output(info, var->data.patch, param, slots);
 167                         break;
 168                 }
 169                 default:
 170                         break;
 171                 }
 172         }
 173 }
 174
 175 static void
 176 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 177                       struct radv_shader_info *info)
 178 {
 179         switch (instr->intrinsic) {
 180         case nir_intrinsic_interp_deref_at_sample:
 181                 info->ps.needs_sample_positions = true;
 182                 break;
 183         case nir_intrinsic_load_draw_id:
 184                 info->vs.needs_draw_id = true;
 185                 break;
 186         case nir_intrinsic_load_instance_id:
 187                 info->vs.needs_instance_id = true;
 188                 break;
 189         case nir_intrinsic_load_num_work_groups:
 190                 info->cs.uses_grid_size = true;
 191                 break;
 192         case nir_intrinsic_load_local_invocation_id:
 193         case nir_intrinsic_load_work_group_id: {
 194                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 195                 while (mask) {
 196                         unsigned i = u_bit_scan(&mask);
 197
 198                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 199                                 info->cs.uses_block_id[i] = true;
 200                         else
 201                                 info->cs.uses_thread_id[i] = true;
 202                 }
 203                 break;
 204         }
 205         case nir_intrinsic_load_local_invocation_index:
 206         case nir_intrinsic_load_subgroup_id:
 207         case nir_intrinsic_load_num_subgroups:
 208                 info->cs.uses_local_invocation_idx = true;
 209                 break;
 210         case nir_intrinsic_load_sample_id:
 211                 info->ps.force_persample = true;
 212                 break;
 213         case nir_intrinsic_load_sample_pos:
 214                 info->ps.force_persample = true;
 215                 break;
 216         case nir_intrinsic_load_view_index:
 217                 info->needs_multiview_view_index = true;
 218                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 219                         info->ps.layer_input = true;
 220                 break;
 221         case nir_intrinsic_load_invocation_id:
 222                 info->uses_invocation_id = true;
 223                 break;
 224         case nir_intrinsic_load_primitive_id:
 225                 info->uses_prim_id = true;
 226                 break;
 227         case nir_intrinsic_load_push_constant:
 228                 info->loads_push_constants = true;
 229                 break;
 230         case nir_intrinsic_vulkan_resource_index:
 231                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 232                 break;
 233         case nir_intrinsic_image_deref_load:
 234         case nir_intrinsic_image_deref_store:
 235         case nir_intrinsic_image_deref_atomic_add:
 236         case nir_intrinsic_image_deref_atomic_min:
 237         case nir_intrinsic_image_deref_atomic_max:
 238         case nir_intrinsic_image_deref_atomic_and:
 239         case nir_intrinsic_image_deref_atomic_or:
 240         case nir_intrinsic_image_deref_atomic_xor:
 241         case nir_intrinsic_image_deref_atomic_exchange:
 242         case nir_intrinsic_image_deref_atomic_comp_swap:
 243         case nir_intrinsic_image_deref_size: {
 244                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 245                 const struct glsl_type *type = glsl_without_array(var->type);
 246
 247                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 248                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 249                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 250                         info->ps.layer_input = true;
 251                         info->ps.uses_input_attachments = true;
 252                 }
 253                 mark_sampler_desc(var, info);
 254
 255                 if (nir_intrinsic_image_deref_store ||
 256                     nir_intrinsic_image_deref_atomic_add ||
 257                     nir_intrinsic_image_deref_atomic_min ||
 258                     nir_intrinsic_image_deref_atomic_max ||
 259                     nir_intrinsic_image_deref_atomic_and ||
 260                     nir_intrinsic_image_deref_atomic_or ||
 261                     nir_intrinsic_image_deref_atomic_xor ||
 262                     nir_intrinsic_image_deref_atomic_exchange ||
 263                     nir_intrinsic_image_deref_atomic_comp_swap) {
 264                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 265                                 info->ps.writes_memory = true;
 266                 }
 267                 break;
 268         }
 269         case nir_intrinsic_store_ssbo:
 270         case nir_intrinsic_ssbo_atomic_add:
 271         case nir_intrinsic_ssbo_atomic_imin:
 272         case nir_intrinsic_ssbo_atomic_umin:
 273         case nir_intrinsic_ssbo_atomic_imax:
 274         case nir_intrinsic_ssbo_atomic_umax:
 275         case nir_intrinsic_ssbo_atomic_and:
 276         case nir_intrinsic_ssbo_atomic_or:
 277         case nir_intrinsic_ssbo_atomic_xor:
 278         case nir_intrinsic_ssbo_atomic_exchange:
 279         case nir_intrinsic_ssbo_atomic_comp_swap:
 280                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 281                         info->ps.writes_memory = true;
 282                 break;
 283         case nir_intrinsic_load_deref:
 284                 gather_intrinsic_load_deref_info(nir, instr, info);
 285                 break;
 286         case nir_intrinsic_store_deref:
 287                 gather_intrinsic_store_deref_info(nir, instr, info);
 288                 break;
 289         default:
 290                 break;
 291         }
 292 }
 293
 294 static void
 295 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 296                 struct radv_shader_info *info)
 297 {
 298         for (unsigned i = 0; i < instr->num_srcs; i++) {
 299                 switch (instr->src[i].src_type) {
 300                 case nir_tex_src_texture_deref:
 301                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 302                         break;
 303                 case nir_tex_src_sampler_deref:
 304                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 305                         break;
 306                 default:
 307                         break;
 308                 }
 309         }
 310 }
 311
 312 static void
 313 gather_info_block(const nir_shader *nir, const nir_block *block,
 314                   struct radv_shader_info *info)
 315 {
 316         nir_foreach_instr(instr, block) {
 317                 switch (instr->type) {
 318                 case nir_instr_type_intrinsic:
 319                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 320                         break;
 321                 case nir_instr_type_tex:
 322                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 323                         break;
 324                 default:
 325                         break;
 326                 }
 327         }
 328 }
 329
 330 static void
 331 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 332                           struct radv_shader_info *info)
 333 {
 334         int idx = var->data.location;
 335
 336         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 337                 info->vs.has_vertex_buffers = true;
 338 }
 339
 340 static void
 341 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 342                           struct radv_shader_info *info)
 343 {
 344         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 345         const struct glsl_type *type = glsl_without_array(var->type);
 346         int idx = var->data.location;
 347
 348         switch (idx) {
 349         case VARYING_SLOT_PNTC:
 350                 info->ps.has_pcoord = true;
 351                 break;
 352         case VARYING_SLOT_PRIMITIVE_ID:
 353                 info->ps.prim_id_input = true;
 354                 break;
 355         case VARYING_SLOT_LAYER:
 356                 info->ps.layer_input = true;
 357                 break;
 358         case VARYING_SLOT_CLIP_DIST0:
 359                 info->ps.num_input_clips_culls = attrib_count;
 360                 break;
 361         default:
 362                 break;
 363         }
 364
 365         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 366                 if (var->data.sample)
 367                         info->ps.force_persample = true;
 368         }
 369 }
 370
 371 static void
 372 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 373                        struct radv_shader_info *info)
 374 {
 375         switch (nir->info.stage) {
 376         case MESA_SHADER_VERTEX:
 377                 gather_info_input_decl_vs(nir, var, info);
 378                 break;
 379         case MESA_SHADER_FRAGMENT:
 380                 gather_info_input_decl_ps(nir, var, info);
 381                 break;
 382         default:
 383                 break;
 384         }
 385 }
 386
 387 static void
 388 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 389                            struct radv_shader_info *info)
 390 {
 391         int idx = var->data.location;
 392         unsigned param = shader_io_get_unique_index(idx);
 393         int num_slots = glsl_count_attribute_slots(var->type, false);
 394         if (idx == VARYING_SLOT_CLIP_DIST0)
 395                 num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 396         mark_ls_output(info, param, num_slots);
 397 }
 398
 399 static void
 400 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 401                            struct radv_shader_info *info)
 402 {
 403         int idx = var->data.location;
 404
 405         switch (idx) {
 406         case FRAG_RESULT_DEPTH:
 407                 info->ps.writes_z = true;
 408                 break;
 409         case FRAG_RESULT_STENCIL:
 410                 info->ps.writes_stencil = true;
 411                 break;
 412         case FRAG_RESULT_SAMPLE_MASK:
 413                 info->ps.writes_sample_mask = true;
 414                 break;
 415         default:
 416                 break;
 417         }
 418 }
 419
 420 static void
 421 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 422                         struct radv_shader_info *info,
 423                         const struct radv_nir_compiler_options *options)
 424 {
 425         switch (nir->info.stage) {
 426         case MESA_SHADER_FRAGMENT:
 427                 gather_info_output_decl_ps(nir, var, info);
 428                 break;
 429         case MESA_SHADER_VERTEX:
 430                 if (options->key.vs.as_ls)
 431                         gather_info_output_decl_ls(nir, var, info);
 432                 break;
 433         default:
 434                 break;
 435         }
 436 }
 437
 438 void
 439 radv_nir_shader_info_pass(const struct nir_shader *nir,
 440                           const struct radv_nir_compiler_options *options,
 441                           struct radv_shader_info *info)
 442 {
 443         struct nir_function *func =
 444                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 445
 446         if (options->layout && options->layout->dynamic_offset_count)
 447                 info->loads_push_constants = true;
 448
 449         nir_foreach_variable(variable, &nir->inputs)
 450                 gather_info_input_decl(nir, variable, info);
 451
 452         nir_foreach_block(block, func->impl) {
 453                 gather_info_block(nir, block, info);
 454         }
 455
 456         nir_foreach_variable(variable, &nir->outputs)
 457                 gather_info_output_decl(nir, variable, info, options);
 458 }