src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26
  27 static void mark_sampler_desc(const nir_variable *var,
  28                               struct radv_shader_info *info)
  29 {
  30         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  31 }
  32
  33 static void mark_ls_output(struct radv_shader_info *info,
  34                            uint32_t param, int num_slots)
  35 {
  36         uint64_t mask = (1ull << num_slots) - 1ull;
  37         info->vs.ls_outputs_written |= (mask << param);
  38 }
  39
  40 static void mark_tess_output(struct radv_shader_info *info,
  41                              bool is_patch, uint32_t param, int num_slots)
  42 {
  43         uint64_t mask = (1ull << num_slots) - 1ull;
  44         if (is_patch)
  45                 info->tcs.patch_outputs_written |= (mask << param);
  46         else
  47                 info->tcs.outputs_written |= (mask << param);
  48 }
  49
  50 static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
  51 {
  52         nir_deref *tail = &deref->deref;
  53         unsigned const_offset = 0;
  54
  55         if (deref->var->data.compact) {
  56                 assert(tail->child->deref_type == nir_deref_type_array);
  57                 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
  58
  59                 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
  60                 /* We always lower indirect dereferences for "compact" array vars. */
  61                 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
  62
  63                 *const_out = deref_array->base_offset;
  64                 return;
  65         }
  66
  67         while (tail->child != NULL) {
  68                 const struct glsl_type *parent_type = tail->type;
  69                 tail = tail->child;
  70
  71                 if (tail->deref_type == nir_deref_type_array) {
  72                         nir_deref_array *deref_array = nir_deref_as_array(tail);
  73                         unsigned size = glsl_count_attribute_slots(tail->type, false);
  74
  75                         const_offset += size * deref_array->base_offset;
  76                 } else if (tail->deref_type == nir_deref_type_struct) {
  77                         nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
  78
  79                         for (unsigned i = 0; i < deref_struct->index; i++) {
  80                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  81                                 const_offset += glsl_count_attribute_slots(ft, false);
  82                         }
  83                 } else
  84                         unreachable("unsupported deref type");
  85         }
  86
  87         *const_out = const_offset;
  88 }
  89
  90 static void
  91 gather_intrinsic_load_var_info(const nir_shader *nir,
  92                                const nir_intrinsic_instr *instr,
  93                                struct radv_shader_info *info)
  94 {
  95         switch (nir->info.stage) {
  96         case MESA_SHADER_VERTEX: {
  97                 nir_deref_var *dvar = instr->variables[0];
  98                 nir_variable *var = dvar->var;
  99
 100                 if (var->data.mode == nir_var_shader_in) {
 101                         unsigned idx = var->data.location;
 102                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 103
 104                         info->vs.input_usage_mask[idx] |=
 105                                 mask << var->data.location_frac;
 106                 }
 107                 break;
 108         }
 109         default:
 110                 break;
 111         }
 112 }
 113
 114 static void
 115 gather_intrinsic_store_var_info(const nir_shader *nir,
 116                                 const nir_intrinsic_instr *instr,
 117                                 struct radv_shader_info *info)
 118 {
 119         nir_deref_var *dvar = instr->variables[0];
 120         nir_variable *var = dvar->var;
 121
 122         if (var->data.mode == nir_var_shader_out) {
 123                 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 124                 unsigned idx = var->data.location;
 125                 unsigned comp = var->data.location_frac;
 126                 unsigned const_offset = 0;
 127
 128                 get_deref_offset(dvar, &const_offset);
 129
 130                 switch (nir->info.stage) {
 131                 case MESA_SHADER_VERTEX:
 132                         for (unsigned i = 0; i < attrib_count; i++) {
 133                                 info->vs.output_usage_mask[idx + i + const_offset] |=
 134                                         instr->const_index[0] << comp;
 135                         }
 136                         break;
 137                 case MESA_SHADER_GEOMETRY:
 138                         for (unsigned i = 0; i < attrib_count; i++) {
 139                                 info->gs.output_usage_mask[idx + i + const_offset] |=
 140                                         instr->const_index[0] << comp;
 141                         }
 142                         break;
 143                 case MESA_SHADER_TESS_EVAL:
 144                         for (unsigned i = 0; i < attrib_count; i++) {
 145                                 info->tes.output_usage_mask[idx + i + const_offset] |=
 146                                         instr->const_index[0] << comp;
 147                         }
 148                         break;
 149                 case MESA_SHADER_TESS_CTRL: {
 150                         unsigned param = shader_io_get_unique_index(idx);
 151                         const struct glsl_type *type = var->type;
 152
 153                         if (!var->data.patch)
 154                                 type = glsl_get_array_element(var->type);
 155
 156                         unsigned slots =
 157                                 var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 158                                                   : glsl_count_attribute_slots(type, false);
 159
 160                         if (idx == VARYING_SLOT_CLIP_DIST0)
 161                                 slots = (nir->info.clip_distance_array_size +
 162                                          nir->info.cull_distance_array_size > 4) ? 2 : 1;
 163
 164                         mark_tess_output(info, var->data.patch, param, slots);
 165                         break;
 166                 }
 167                 default:
 168                         break;
 169                 }
 170         }
 171 }
 172
 173 static void
 174 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 175                       struct radv_shader_info *info)
 176 {
 177         switch (instr->intrinsic) {
 178         case nir_intrinsic_interp_var_at_sample:
 179                 info->ps.needs_sample_positions = true;
 180                 break;
 181         case nir_intrinsic_load_draw_id:
 182                 info->vs.needs_draw_id = true;
 183                 break;
 184         case nir_intrinsic_load_instance_id:
 185                 info->vs.needs_instance_id = true;
 186                 break;
 187         case nir_intrinsic_load_num_work_groups:
 188                 info->cs.uses_grid_size = true;
 189                 break;
 190         case nir_intrinsic_load_local_invocation_id:
 191         case nir_intrinsic_load_work_group_id: {
 192                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 193                 while (mask) {
 194                         unsigned i = u_bit_scan(&mask);
 195
 196                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 197                                 info->cs.uses_block_id[i] = true;
 198                         else
 199                                 info->cs.uses_thread_id[i] = true;
 200                 }
 201                 break;
 202         }
 203         case nir_intrinsic_load_local_invocation_index:
 204         case nir_intrinsic_load_subgroup_id:
 205         case nir_intrinsic_load_num_subgroups:
 206                 info->cs.uses_local_invocation_idx = true;
 207                 break;
 208         case nir_intrinsic_load_sample_id:
 209                 info->ps.force_persample = true;
 210                 break;
 211         case nir_intrinsic_load_sample_pos:
 212                 info->ps.force_persample = true;
 213                 break;
 214         case nir_intrinsic_load_view_index:
 215                 info->needs_multiview_view_index = true;
 216                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 217                         info->ps.layer_input = true;
 218                 break;
 219         case nir_intrinsic_load_invocation_id:
 220                 info->uses_invocation_id = true;
 221                 break;
 222         case nir_intrinsic_load_primitive_id:
 223                 info->uses_prim_id = true;
 224                 break;
 225         case nir_intrinsic_load_push_constant:
 226                 info->loads_push_constants = true;
 227                 break;
 228         case nir_intrinsic_vulkan_resource_index:
 229                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 230                 break;
 231         case nir_intrinsic_image_var_load:
 232         case nir_intrinsic_image_var_store:
 233         case nir_intrinsic_image_var_atomic_add:
 234         case nir_intrinsic_image_var_atomic_min:
 235         case nir_intrinsic_image_var_atomic_max:
 236         case nir_intrinsic_image_var_atomic_and:
 237         case nir_intrinsic_image_var_atomic_or:
 238         case nir_intrinsic_image_var_atomic_xor:
 239         case nir_intrinsic_image_var_atomic_exchange:
 240         case nir_intrinsic_image_var_atomic_comp_swap:
 241         case nir_intrinsic_image_var_size: {
 242                 const struct glsl_type *type = instr->variables[0]->var->type;
 243                 if(instr->variables[0]->deref.child)
 244                         type = instr->variables[0]->deref.child->type;
 245
 246                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 247                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 248                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 249                         info->ps.layer_input = true;
 250                         info->ps.uses_input_attachments = true;
 251                 }
 252                 mark_sampler_desc(instr->variables[0]->var, info);
 253
 254                 if (nir_intrinsic_image_var_store ||
 255                     nir_intrinsic_image_var_atomic_add ||
 256                     nir_intrinsic_image_var_atomic_min ||
 257                     nir_intrinsic_image_var_atomic_max ||
 258                     nir_intrinsic_image_var_atomic_and ||
 259                     nir_intrinsic_image_var_atomic_or ||
 260                     nir_intrinsic_image_var_atomic_xor ||
 261                     nir_intrinsic_image_var_atomic_exchange ||
 262                     nir_intrinsic_image_var_atomic_comp_swap) {
 263                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 264                                 info->ps.writes_memory = true;
 265                 }
 266                 break;
 267         }
 268         case nir_intrinsic_store_ssbo:
 269         case nir_intrinsic_ssbo_atomic_add:
 270         case nir_intrinsic_ssbo_atomic_imin:
 271         case nir_intrinsic_ssbo_atomic_umin:
 272         case nir_intrinsic_ssbo_atomic_imax:
 273         case nir_intrinsic_ssbo_atomic_umax:
 274         case nir_intrinsic_ssbo_atomic_and:
 275         case nir_intrinsic_ssbo_atomic_or:
 276         case nir_intrinsic_ssbo_atomic_xor:
 277         case nir_intrinsic_ssbo_atomic_exchange:
 278         case nir_intrinsic_ssbo_atomic_comp_swap:
 279                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 280                         info->ps.writes_memory = true;
 281                 break;
 282         case nir_intrinsic_load_var:
 283                 gather_intrinsic_load_var_info(nir, instr, info);
 284                 break;
 285         case nir_intrinsic_store_var:
 286                 gather_intrinsic_store_var_info(nir, instr, info);
 287                 break;
 288         default:
 289                 break;
 290         }
 291 }
 292
 293 static void
 294 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 295                 struct radv_shader_info *info)
 296 {
 297         for (unsigned i = 0; i < instr->num_srcs; i++) {
 298                 switch (instr->src[i].src_type) {
 299                 case nir_tex_src_texture_deref:
 300                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 301                         break;
 302                 case nir_tex_src_sampler_deref:
 303                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 304                         break;
 305                 default:
 306                         break;
 307                 }
 308         }
 309
 310         if (instr->sampler)
 311                 mark_sampler_desc(instr->sampler->var, info);
 312         if (instr->texture)
 313                 mark_sampler_desc(instr->texture->var, info);
 314 }
 315
 316 static void
 317 gather_info_block(const nir_shader *nir, const nir_block *block,
 318                   struct radv_shader_info *info)
 319 {
 320         nir_foreach_instr(instr, block) {
 321                 switch (instr->type) {
 322                 case nir_instr_type_intrinsic:
 323                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 324                         break;
 325                 case nir_instr_type_tex:
 326                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 327                         break;
 328                 default:
 329                         break;
 330                 }
 331         }
 332 }
 333
 334 static void
 335 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 336                           struct radv_shader_info *info)
 337 {
 338         int idx = var->data.location;
 339
 340         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 341                 info->vs.has_vertex_buffers = true;
 342 }
 343
 344 static void
 345 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 346                           struct radv_shader_info *info)
 347 {
 348         const struct glsl_type *type = glsl_without_array(var->type);
 349         int idx = var->data.location;
 350
 351         switch (idx) {
 352         case VARYING_SLOT_PNTC:
 353                 info->ps.has_pcoord = true;
 354                 break;
 355         case VARYING_SLOT_PRIMITIVE_ID:
 356                 info->ps.prim_id_input = true;
 357                 break;
 358         case VARYING_SLOT_LAYER:
 359                 info->ps.layer_input = true;
 360                 break;
 361         default:
 362                 break;
 363         }
 364
 365         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 366                 if (var->data.sample)
 367                         info->ps.force_persample = true;
 368         }
 369 }
 370
 371 static void
 372 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 373                        struct radv_shader_info *info)
 374 {
 375         switch (nir->info.stage) {
 376         case MESA_SHADER_VERTEX:
 377                 gather_info_input_decl_vs(nir, var, info);
 378                 break;
 379         case MESA_SHADER_FRAGMENT:
 380                 gather_info_input_decl_ps(nir, var, info);
 381                 break;
 382         default:
 383                 break;
 384         }
 385 }
 386
 387 static void
 388 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 389                            struct radv_shader_info *info)
 390 {
 391         int idx = var->data.location;
 392         unsigned param = shader_io_get_unique_index(idx);
 393         int num_slots = glsl_count_attribute_slots(var->type, false);
 394         if (idx == VARYING_SLOT_CLIP_DIST0)
 395                 num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 396         mark_ls_output(info, param, num_slots);
 397 }
 398
 399 static void
 400 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 401                            struct radv_shader_info *info)
 402 {
 403         int idx = var->data.location;
 404
 405         switch (idx) {
 406         case FRAG_RESULT_DEPTH:
 407                 info->ps.writes_z = true;
 408                 break;
 409         case FRAG_RESULT_STENCIL:
 410                 info->ps.writes_stencil = true;
 411                 break;
 412         case FRAG_RESULT_SAMPLE_MASK:
 413                 info->ps.writes_sample_mask = true;
 414                 break;
 415         default:
 416                 break;
 417         }
 418 }
 419
 420 static void
 421 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 422                         struct radv_shader_info *info,
 423                         const struct radv_nir_compiler_options *options)
 424 {
 425         switch (nir->info.stage) {
 426         case MESA_SHADER_FRAGMENT:
 427                 gather_info_output_decl_ps(nir, var, info);
 428                 break;
 429         case MESA_SHADER_VERTEX:
 430                 if (options->key.vs.as_ls)
 431                         gather_info_output_decl_ls(nir, var, info);
 432                 break;
 433         default:
 434                 break;
 435         }
 436 }
 437
 438 void
 439 radv_nir_shader_info_pass(const struct nir_shader *nir,
 440                           const struct radv_nir_compiler_options *options,
 441                           struct radv_shader_info *info)
 442 {
 443         struct nir_function *func =
 444                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 445
 446         if (options->layout && options->layout->dynamic_offset_count)
 447                 info->loads_push_constants = true;
 448
 449         nir_foreach_variable(variable, &nir->inputs)
 450                 gather_info_input_decl(nir, variable, info);
 451
 452         nir_foreach_block(block, func->impl) {
 453                 gather_info_block(nir, block, info);
 454         }
 455
 456         nir_foreach_variable(variable, &nir->outputs)
 457                 gather_info_output_decl(nir, variable, info, options);
 458 }