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1464c913cd632215b2b12acd776040dcdf98dc10
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_cmdbuf *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
45 unsigned raster_config_se[4];
46 unsigned se;
47
48 ac_get_harvested_configs(&physical_device->rad_info,
49 raster_config,
50 &raster_config_1,
51 raster_config_se);
52
53 for (se = 0; se < num_se; se++) {
54 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
55 if (physical_device->rad_info.chip_class < CIK)
56 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
57 S_00802C_SE_INDEX(se) |
58 S_00802C_SH_BROADCAST_WRITES(1) |
59 S_00802C_INSTANCE_BROADCAST_WRITES(1));
60 else
61 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
62 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
63 S_030800_INSTANCE_BROADCAST_WRITES(1));
64 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
65 }
66
67 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
68 if (physical_device->rad_info.chip_class < CIK)
69 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
70 S_00802C_SE_BROADCAST_WRITES(1) |
71 S_00802C_SH_BROADCAST_WRITES(1) |
72 S_00802C_INSTANCE_BROADCAST_WRITES(1));
73 else
74 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
75 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
76 S_030800_INSTANCE_BROADCAST_WRITES(1));
77
78 if (physical_device->rad_info.chip_class >= CIK)
79 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
80 }
81
82 static void
83 si_emit_compute(struct radv_physical_device *physical_device,
84 struct radeon_cmdbuf *cs)
85 {
86 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89 radeon_emit(cs, 0);
90
91 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
92 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= CIK) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
101 S_00B864_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
103 S_00B868_SH1_CU_EN(0xffff));
104 }
105
106 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
107 * and is now per pipe, so it should be handled in the
108 * kernel if we want to use something other than the default value,
109 * which is now 0x22f.
110 */
111 if (physical_device->rad_info.chip_class <= SI) {
112 /* XXX: This should be:
113 * (number of compute units) * 4 * (waves per simd) - 1 */
114
115 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
116 0x190 /* Default value */);
117 }
118 }
119
120 void
121 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
122 {
123 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
124 si_emit_compute(physical_device, cmd_buffer->cs);
125 }
126
127 /* 12.4 fixed-point */
128 static unsigned radv_pack_float_12p4(float x)
129 {
130 return x <= 0 ? 0 :
131 x >= 4096 ? 0xffff : x * 16;
132 }
133
134 static void
135 si_set_raster_config(struct radv_physical_device *physical_device,
136 struct radeon_cmdbuf *cs)
137 {
138 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
139 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
140 unsigned raster_config, raster_config_1;
141
142 ac_get_raster_config(&physical_device->rad_info,
143 &raster_config,
144 &raster_config_1);
145
146 /* Always use the default config when all backends are enabled
147 * (or when we failed to determine the enabled backends).
148 */
149 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
150 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
151 raster_config);
152 if (physical_device->rad_info.chip_class >= CIK)
153 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
154 raster_config_1);
155 } else {
156 si_write_harvested_raster_configs(physical_device, cs,
157 raster_config,
158 raster_config_1);
159 }
160 }
161
162 static void
163 si_emit_config(struct radv_physical_device *physical_device,
164 struct radeon_cmdbuf *cs)
165 {
166 int i;
167
168 /* Only SI can disable CLEAR_STATE for now. */
169 assert(physical_device->has_clear_state ||
170 physical_device->rad_info.chip_class == SI);
171
172 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
173 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
174 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
175
176 if (physical_device->has_clear_state) {
177 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
178 radeon_emit(cs, 0);
179 }
180
181 if (physical_device->rad_info.chip_class <= VI)
182 si_set_raster_config(physical_device, cs);
183
184 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
185 if (!physical_device->has_clear_state)
186 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
187
188 /* FIXME calculate these values somehow ??? */
189 if (physical_device->rad_info.chip_class <= VI) {
190 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
191 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
192 }
193
194 if (!physical_device->has_clear_state) {
195 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
196 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
197 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
198 }
199
200 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
201 if (!physical_device->has_clear_state)
202 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
203 if (physical_device->rad_info.chip_class < CIK)
204 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
205 S_008A14_CLIP_VTX_REORDER_ENA(1));
206
207 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
208 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
209
210 if (!physical_device->has_clear_state)
211 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
212
213 /* CLEAR_STATE doesn't clear these correctly on certain generations.
214 * I don't know why. Deduced by trial and error.
215 */
216 if (physical_device->rad_info.chip_class <= CIK) {
217 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
218 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
219 S_028204_WINDOW_OFFSET_DISABLE(1));
220 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
221 S_028240_WINDOW_OFFSET_DISABLE(1));
222 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
223 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
224 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
225 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
226 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
227 }
228
229 if (!physical_device->has_clear_state) {
230 for (i = 0; i < 16; i++) {
231 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
232 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
233 }
234 }
235
236 if (!physical_device->has_clear_state) {
237 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
238 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
239 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
240 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
241 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
242 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
243 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
244 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
245 }
246
247 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
248 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
249 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
250
251 if (physical_device->rad_info.chip_class >= GFX9) {
252 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
253 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
254 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
255 } else {
256 /* These registers, when written, also overwrite the
257 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
258 * them. It would be an issue if there was another UMD
259 * changing them.
260 */
261 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
262 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
263 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
264 }
265
266 if (physical_device->rad_info.chip_class >= CIK) {
267 if (physical_device->rad_info.chip_class >= GFX9) {
268 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
269 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
270 } else {
271 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
272 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
273 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
274 S_00B41C_WAVE_LIMIT(0x3F));
275 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
276 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
277 /* If this is 0, Bonaire can hang even if GS isn't being used.
278 * Other chips are unaffected. These are suboptimal values,
279 * but we don't use on-chip GS.
280 */
281 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
282 S_028A44_ES_VERTS_PER_SUBGRP(64) |
283 S_028A44_GS_PRIMS_PER_SUBGRP(4));
284 }
285 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
286 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
287
288 if (physical_device->rad_info.num_good_compute_units /
289 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
290 /* Too few available compute units per SH. Disallowing
291 * VS to run on CU0 could hurt us more than late VS
292 * allocation would help.
293 *
294 * LATE_ALLOC_VS = 2 is the highest safe number.
295 */
296 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
297 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
298 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
299 } else {
300 /* Set LATE_ALLOC_VS == 31. It should be less than
301 * the number of scratch waves. Limitations:
302 * - VS can't execute on CU0.
303 * - If HS writes outputs to LDS, LS can't execute on CU0.
304 */
305 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
306 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
307 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
308 }
309
310 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
311 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
312 }
313
314 if (physical_device->rad_info.chip_class >= VI) {
315 uint32_t vgt_tess_distribution;
316 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
317 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
318 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
319
320 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
321 S_028B50_ACCUM_TRI(11) |
322 S_028B50_ACCUM_QUAD(11) |
323 S_028B50_DONUT_SPLIT(16);
324
325 if (physical_device->rad_info.family == CHIP_FIJI ||
326 physical_device->rad_info.family >= CHIP_POLARIS10)
327 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
328
329 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
330 vgt_tess_distribution);
331 } else if (!physical_device->has_clear_state) {
332 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
333 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
334 }
335
336 if (physical_device->rad_info.chip_class >= GFX9) {
337 unsigned num_se = physical_device->rad_info.max_se;
338 unsigned pc_lines = 0;
339
340 switch (physical_device->rad_info.family) {
341 case CHIP_VEGA10:
342 case CHIP_VEGA12:
343 case CHIP_VEGA20:
344 pc_lines = 4096;
345 break;
346 case CHIP_RAVEN:
347 pc_lines = 1024;
348 break;
349 default:
350 assert(0);
351 }
352
353 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
354 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
355 S_028C48_MAX_PRIM_PER_BATCH(1023));
356 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
357 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
358 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
359 }
360
361 unsigned tmp = (unsigned)(1.0 * 8.0);
362 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
363 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
364 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
365 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
366 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
367
368 if (!physical_device->has_clear_state) {
369 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
370 S_028004_ZPASS_INCREMENT_DISABLE(1));
371 }
372
373 /* Enable the Polaris small primitive filter control.
374 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
375 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
376 * and AMDVLK doesn't have a workaround as well.
377 */
378 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
379 unsigned small_prim_filter_cntl =
380 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
381 /* Workaround for a hw line bug. */
382 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
383
384 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
385 small_prim_filter_cntl);
386 }
387
388 si_emit_compute(physical_device, cs);
389 }
390
391 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
392 {
393 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
394
395 si_emit_config(physical_device, cmd_buffer->cs);
396 }
397
398 void
399 cik_create_gfx_config(struct radv_device *device)
400 {
401 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
402 if (!cs)
403 return;
404
405 si_emit_config(device->physical_device, cs);
406
407 while (cs->cdw & 7) {
408 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
409 radeon_emit(cs, 0x80000000);
410 else
411 radeon_emit(cs, 0xffff1000);
412 }
413
414 device->gfx_init = device->ws->buffer_create(device->ws,
415 cs->cdw * 4, 4096,
416 RADEON_DOMAIN_GTT,
417 RADEON_FLAG_CPU_ACCESS|
418 RADEON_FLAG_NO_INTERPROCESS_SHARING |
419 RADEON_FLAG_READ_ONLY);
420 if (!device->gfx_init)
421 goto fail;
422
423 void *map = device->ws->buffer_map(device->gfx_init);
424 if (!map) {
425 device->ws->buffer_destroy(device->gfx_init);
426 device->gfx_init = NULL;
427 goto fail;
428 }
429 memcpy(map, cs->buf, cs->cdw * 4);
430
431 device->ws->buffer_unmap(device->gfx_init);
432 device->gfx_init_size_dw = cs->cdw;
433 fail:
434 device->ws->cs_destroy(cs);
435 }
436
437 static void
438 get_viewport_xform(const VkViewport *viewport,
439 float scale[3], float translate[3])
440 {
441 float x = viewport->x;
442 float y = viewport->y;
443 float half_width = 0.5f * viewport->width;
444 float half_height = 0.5f * viewport->height;
445 double n = viewport->minDepth;
446 double f = viewport->maxDepth;
447
448 scale[0] = half_width;
449 translate[0] = half_width + x;
450 scale[1] = half_height;
451 translate[1] = half_height + y;
452
453 scale[2] = (f - n);
454 translate[2] = n;
455 }
456
457 void
458 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
459 int count, const VkViewport *viewports)
460 {
461 int i;
462
463 assert(count);
464 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
465 first_vp * 4 * 6, count * 6);
466
467 for (i = 0; i < count; i++) {
468 float scale[3], translate[3];
469
470
471 get_viewport_xform(&viewports[i], scale, translate);
472 radeon_emit(cs, fui(scale[0]));
473 radeon_emit(cs, fui(translate[0]));
474 radeon_emit(cs, fui(scale[1]));
475 radeon_emit(cs, fui(translate[1]));
476 radeon_emit(cs, fui(scale[2]));
477 radeon_emit(cs, fui(translate[2]));
478 }
479
480 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
481 first_vp * 4 * 2, count * 2);
482 for (i = 0; i < count; i++) {
483 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
484 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
485 radeon_emit(cs, fui(zmin));
486 radeon_emit(cs, fui(zmax));
487 }
488 }
489
490 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
491 {
492 float scale[3], translate[3];
493 VkRect2D rect;
494
495 get_viewport_xform(viewport, scale, translate);
496
497 rect.offset.x = translate[0] - fabs(scale[0]);
498 rect.offset.y = translate[1] - fabs(scale[1]);
499 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
500 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
501
502 return rect;
503 }
504
505 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
506 VkRect2D ret;
507 ret.offset.x = MAX2(a->offset.x, b->offset.x);
508 ret.offset.y = MAX2(a->offset.y, b->offset.y);
509 ret.extent.width = MIN2(a->offset.x + a->extent.width,
510 b->offset.x + b->extent.width) - ret.offset.x;
511 ret.extent.height = MIN2(a->offset.y + a->extent.height,
512 b->offset.y + b->extent.height) - ret.offset.y;
513 return ret;
514 }
515
516 void
517 si_write_scissors(struct radeon_cmdbuf *cs, int first,
518 int count, const VkRect2D *scissors,
519 const VkViewport *viewports, bool can_use_guardband)
520 {
521 int i;
522 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
523 const float max_range = 32767.0f;
524 if (!count)
525 return;
526
527 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
528 for (i = 0; i < count; i++) {
529 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
530 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
531
532 get_viewport_xform(viewports + i, scale, translate);
533 scale[0] = abs(scale[0]);
534 scale[1] = abs(scale[1]);
535
536 if (scale[0] < 0.5)
537 scale[0] = 0.5;
538 if (scale[1] < 0.5)
539 scale[1] = 0.5;
540
541 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
542 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
543
544 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
545 S_028250_TL_Y(scissor.offset.y) |
546 S_028250_WINDOW_OFFSET_DISABLE(1));
547 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
548 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
549 }
550 if (!can_use_guardband) {
551 guardband_x = 1.0;
552 guardband_y = 1.0;
553 }
554
555 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
556 radeon_emit(cs, fui(guardband_y));
557 radeon_emit(cs, fui(1.0));
558 radeon_emit(cs, fui(guardband_x));
559 radeon_emit(cs, fui(1.0));
560 }
561
562 static inline unsigned
563 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
564 {
565 if (num == 0)
566 return 0;
567
568 if (info->incr == 0)
569 return 0;
570
571 if (num < info->min)
572 return 0;
573
574 return 1 + ((num - info->min) / info->incr);
575 }
576
577 uint32_t
578 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
579 bool instanced_draw, bool indirect_draw,
580 uint32_t draw_vertex_count)
581 {
582 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
583 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
584 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
585 const unsigned max_primgroup_in_wave = 2;
586 /* SWITCH_ON_EOP(0) is always preferable. */
587 bool wd_switch_on_eop = false;
588 bool ia_switch_on_eop = false;
589 bool ia_switch_on_eoi = false;
590 bool partial_vs_wave = false;
591 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
592 bool multi_instances_smaller_than_primgroup;
593
594 multi_instances_smaller_than_primgroup = indirect_draw;
595 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
596 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
597 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
598 multi_instances_smaller_than_primgroup = true;
599 }
600
601 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
602 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
603
604 if (chip_class >= CIK) {
605 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
606
607 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
608 * We don't know that for indirect drawing, so treat it as
609 * always problematic. */
610 if (family == CHIP_HAWAII &&
611 (instanced_draw || indirect_draw))
612 wd_switch_on_eop = true;
613
614 /* Performance recommendation for 4 SE Gfx7-8 parts if
615 * instances are smaller than a primgroup.
616 * Assume indirect draws always use small instances.
617 * This is needed for good VS wave utilization.
618 */
619 if (chip_class <= VI &&
620 info->max_se == 4 &&
621 multi_instances_smaller_than_primgroup)
622 wd_switch_on_eop = true;
623
624 /* Required on CIK and later. */
625 if (info->max_se > 2 && !wd_switch_on_eop)
626 ia_switch_on_eoi = true;
627
628 /* Required by Hawaii and, for some special cases, by VI. */
629 if (ia_switch_on_eoi &&
630 (family == CHIP_HAWAII ||
631 (chip_class == VI &&
632 /* max primgroup in wave is always 2 - leave this for documentation */
633 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
634 partial_vs_wave = true;
635
636 /* Instancing bug on Bonaire. */
637 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
638 (instanced_draw || indirect_draw))
639 partial_vs_wave = true;
640
641 /* If the WD switch is false, the IA switch must be false too. */
642 assert(wd_switch_on_eop || !ia_switch_on_eop);
643 }
644 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
645 if (chip_class <= VI && ia_switch_on_eoi)
646 partial_es_wave = true;
647
648 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
649 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
650 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
651 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
652 */
653 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
654 bool set_vgt_flush = indirect_draw;
655 if (!set_vgt_flush && instanced_draw) {
656 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
657 if (num_prims <= 1)
658 set_vgt_flush = true;
659 }
660 if (set_vgt_flush)
661 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
662 }
663 }
664
665 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
666 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
667 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
668 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
669 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
670 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
671
672 }
673
674 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
675 enum chip_class chip_class,
676 bool is_mec,
677 unsigned event, unsigned event_flags,
678 unsigned data_sel,
679 uint64_t va,
680 uint32_t old_fence,
681 uint32_t new_fence,
682 uint64_t gfx9_eop_bug_va)
683 {
684 unsigned op = EVENT_TYPE(event) |
685 EVENT_INDEX(5) |
686 event_flags;
687 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
688 unsigned sel = EOP_DATA_SEL(data_sel);
689
690 /* Wait for write confirmation before writing data, but don't send
691 * an interrupt. */
692 if (data_sel != EOP_DATA_SEL_DISCARD)
693 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
694
695 if (chip_class >= GFX9 || is_gfx8_mec) {
696 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
697 * counters) must immediately precede every timestamp event to
698 * prevent a GPU hang on GFX9.
699 */
700 if (chip_class == GFX9) {
701 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
702 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
703 radeon_emit(cs, gfx9_eop_bug_va);
704 radeon_emit(cs, gfx9_eop_bug_va >> 32);
705 }
706
707 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
708 radeon_emit(cs, op);
709 radeon_emit(cs, sel);
710 radeon_emit(cs, va); /* address lo */
711 radeon_emit(cs, va >> 32); /* address hi */
712 radeon_emit(cs, new_fence); /* immediate data lo */
713 radeon_emit(cs, 0); /* immediate data hi */
714 if (!is_gfx8_mec)
715 radeon_emit(cs, 0); /* unused */
716 } else {
717 if (chip_class == CIK ||
718 chip_class == VI) {
719 /* Two EOP events are required to make all engines go idle
720 * (and optional cache flushes executed) before the timestamp
721 * is written.
722 */
723 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
724 radeon_emit(cs, op);
725 radeon_emit(cs, va);
726 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
727 radeon_emit(cs, old_fence); /* immediate data */
728 radeon_emit(cs, 0); /* unused */
729 }
730
731 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
732 radeon_emit(cs, op);
733 radeon_emit(cs, va);
734 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
735 radeon_emit(cs, new_fence); /* immediate data */
736 radeon_emit(cs, 0); /* unused */
737 }
738 }
739
740 void
741 si_emit_wait_fence(struct radeon_cmdbuf *cs,
742 uint64_t va, uint32_t ref,
743 uint32_t mask)
744 {
745 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
746 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
747 radeon_emit(cs, va);
748 radeon_emit(cs, va >> 32);
749 radeon_emit(cs, ref); /* reference value */
750 radeon_emit(cs, mask); /* mask */
751 radeon_emit(cs, 4); /* poll interval */
752 }
753
754 static void
755 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
756 bool is_mec,
757 bool is_gfx9,
758 unsigned cp_coher_cntl)
759 {
760 if (is_mec || is_gfx9) {
761 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
762 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
763 PKT3_SHADER_TYPE_S(is_mec));
764 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
765 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
766 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
767 radeon_emit(cs, 0); /* CP_COHER_BASE */
768 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
769 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
770 } else {
771 /* ACQUIRE_MEM is only required on a compute ring. */
772 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
773 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
774 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
775 radeon_emit(cs, 0); /* CP_COHER_BASE */
776 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
777 }
778 }
779
780 void
781 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
782 enum chip_class chip_class,
783 uint32_t *flush_cnt,
784 uint64_t flush_va,
785 bool is_mec,
786 enum radv_cmd_flush_bits flush_bits,
787 uint64_t gfx9_eop_bug_va)
788 {
789 unsigned cp_coher_cntl = 0;
790 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
791 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
792
793 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
794 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
795 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
796 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
797
798 if (chip_class <= VI) {
799 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
800 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
801 S_0085F0_CB0_DEST_BASE_ENA(1) |
802 S_0085F0_CB1_DEST_BASE_ENA(1) |
803 S_0085F0_CB2_DEST_BASE_ENA(1) |
804 S_0085F0_CB3_DEST_BASE_ENA(1) |
805 S_0085F0_CB4_DEST_BASE_ENA(1) |
806 S_0085F0_CB5_DEST_BASE_ENA(1) |
807 S_0085F0_CB6_DEST_BASE_ENA(1) |
808 S_0085F0_CB7_DEST_BASE_ENA(1);
809
810 /* Necessary for DCC */
811 if (chip_class >= VI) {
812 si_cs_emit_write_event_eop(cs,
813 chip_class,
814 is_mec,
815 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
816 0,
817 EOP_DATA_SEL_DISCARD,
818 0, 0, 0,
819 gfx9_eop_bug_va);
820 }
821 }
822 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
823 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
824 S_0085F0_DB_DEST_BASE_ENA(1);
825 }
826 }
827
828 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
830 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
831 }
832
833 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
834 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
835 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
836 }
837
838 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
841 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
842 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
843 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
844 }
845
846 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
847 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
848 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
849 }
850
851 if (chip_class >= GFX9 && flush_cb_db) {
852 unsigned cb_db_event, tc_flags;
853
854 /* Set the CB/DB flush event. */
855 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
856
857 /* These are the only allowed combinations. If you need to
858 * do multiple operations at once, do them separately.
859 * All operations that invalidate L2 also seem to invalidate
860 * metadata. Volatile (VOL) and WC flushes are not listed here.
861 *
862 * TC | TC_WB = writeback & invalidate L2 & L1
863 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
864 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
865 * TC | TC_NC = invalidate L2 for MTYPE == NC
866 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
867 * TCL1 = invalidate L1
868 */
869 tc_flags = EVENT_TC_ACTION_ENA |
870 EVENT_TC_MD_ACTION_ENA;
871
872 /* Ideally flush TC together with CB/DB. */
873 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
874 /* Writeback and invalidate everything in L2 & L1. */
875 tc_flags = EVENT_TC_ACTION_ENA |
876 EVENT_TC_WB_ACTION_ENA;
877
878
879 /* Clear the flags. */
880 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
881 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
882 RADV_CMD_FLAG_INV_VMEM_L1);
883 }
884 assert(flush_cnt);
885 uint32_t old_fence = (*flush_cnt)++;
886
887 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
888 EOP_DATA_SEL_VALUE_32BIT,
889 flush_va, old_fence, *flush_cnt,
890 gfx9_eop_bug_va);
891 si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
892 }
893
894 /* VGT state sync */
895 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
897 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
898 }
899
900 /* Make sure ME is idle (it executes most packets) before continuing.
901 * This prevents read-after-write hazards between PFP and ME.
902 */
903 if ((cp_coher_cntl ||
904 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
905 RADV_CMD_FLAG_INV_VMEM_L1 |
906 RADV_CMD_FLAG_INV_GLOBAL_L2 |
907 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
908 !is_mec) {
909 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
910 radeon_emit(cs, 0);
911 }
912
913 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
914 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
915 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
916 cp_coher_cntl |
917 S_0085F0_TC_ACTION_ENA(1) |
918 S_0085F0_TCL1_ACTION_ENA(1) |
919 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
920 cp_coher_cntl = 0;
921 } else {
922 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
923 /* WB = write-back
924 * NC = apply to non-coherent MTYPEs
925 * (i.e. MTYPE <= 1, which is what we use everywhere)
926 *
927 * WB doesn't work without NC.
928 */
929 si_emit_acquire_mem(cs, is_mec,
930 chip_class >= GFX9,
931 cp_coher_cntl |
932 S_0301F0_TC_WB_ACTION_ENA(1) |
933 S_0301F0_TC_NC_ACTION_ENA(1));
934 cp_coher_cntl = 0;
935 }
936 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
937 si_emit_acquire_mem(cs, is_mec,
938 chip_class >= GFX9,
939 cp_coher_cntl |
940 S_0085F0_TCL1_ACTION_ENA(1));
941 cp_coher_cntl = 0;
942 }
943 }
944
945 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
946 * Therefore, it should be last. Done in PFP.
947 */
948 if (cp_coher_cntl)
949 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
950
951 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
952 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
953 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
954 EVENT_INDEX(0));
955 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
956 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
957 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
958 EVENT_INDEX(0));
959 }
960 }
961
962 void
963 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
964 {
965 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
966
967 if (is_compute)
968 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
969 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
970 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
971 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
972 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
973 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
974 RADV_CMD_FLAG_VGT_FLUSH |
975 RADV_CMD_FLAG_START_PIPELINE_STATS |
976 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
977
978 if (!cmd_buffer->state.flush_bits)
979 return;
980
981 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
982 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
983
984 uint32_t *ptr = NULL;
985 uint64_t va = 0;
986 if (chip_class == GFX9) {
987 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
988 ptr = &cmd_buffer->gfx9_fence_idx;
989 }
990 si_cs_emit_cache_flush(cmd_buffer->cs,
991 cmd_buffer->device->physical_device->rad_info.chip_class,
992 ptr, va,
993 radv_cmd_buffer_uses_mec(cmd_buffer),
994 cmd_buffer->state.flush_bits,
995 cmd_buffer->gfx9_eop_bug_va);
996
997
998 if (unlikely(cmd_buffer->device->trace_bo))
999 radv_cmd_buffer_trace_emit(cmd_buffer);
1000
1001 cmd_buffer->state.flush_bits = 0;
1002 }
1003
1004 /* sets the CP predication state using a boolean stored at va */
1005 void
1006 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1007 bool draw_visible, uint64_t va)
1008 {
1009 uint32_t op = 0;
1010
1011 if (va) {
1012 op = PRED_OP(PREDICATION_OP_BOOL64);
1013
1014 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1015 * zero, all rendering commands are discarded. Otherwise, they
1016 * are discarded if the value is non zero.
1017 */
1018 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1019 PREDICATION_DRAW_NOT_VISIBLE;
1020 }
1021 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1022 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1023 radeon_emit(cmd_buffer->cs, op);
1024 radeon_emit(cmd_buffer->cs, va);
1025 radeon_emit(cmd_buffer->cs, va >> 32);
1026 } else {
1027 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1028 radeon_emit(cmd_buffer->cs, va);
1029 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1030 }
1031 }
1032
1033 /* Set this if you want the 3D engine to wait until CP DMA is done.
1034 * It should be set on the last CP DMA packet. */
1035 #define CP_DMA_SYNC (1 << 0)
1036
1037 /* Set this if the source data was used as a destination in a previous CP DMA
1038 * packet. It's for preventing a read-after-write (RAW) hazard between two
1039 * CP DMA packets. */
1040 #define CP_DMA_RAW_WAIT (1 << 1)
1041 #define CP_DMA_USE_L2 (1 << 2)
1042 #define CP_DMA_CLEAR (1 << 3)
1043
1044 /* Alignment for optimal performance. */
1045 #define SI_CPDMA_ALIGNMENT 32
1046
1047 /* The max number of bytes that can be copied per packet. */
1048 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1049 {
1050 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1051 S_414_BYTE_COUNT_GFX9(~0u) :
1052 S_414_BYTE_COUNT_GFX6(~0u);
1053
1054 /* make it aligned for optimal performance */
1055 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1056 }
1057
1058 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1059 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1060 * clear value.
1061 */
1062 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1063 uint64_t dst_va, uint64_t src_va,
1064 unsigned size, unsigned flags)
1065 {
1066 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1067 uint32_t header = 0, command = 0;
1068
1069 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1070
1071 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1072 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1073 command |= S_414_BYTE_COUNT_GFX9(size);
1074 else
1075 command |= S_414_BYTE_COUNT_GFX6(size);
1076
1077 /* Sync flags. */
1078 if (flags & CP_DMA_SYNC)
1079 header |= S_411_CP_SYNC(1);
1080 else {
1081 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1082 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1083 else
1084 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1085 }
1086
1087 if (flags & CP_DMA_RAW_WAIT)
1088 command |= S_414_RAW_WAIT(1);
1089
1090 /* Src and dst flags. */
1091 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1092 !(flags & CP_DMA_CLEAR) &&
1093 src_va == dst_va)
1094 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1095 else if (flags & CP_DMA_USE_L2)
1096 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1097
1098 if (flags & CP_DMA_CLEAR)
1099 header |= S_411_SRC_SEL(V_411_DATA);
1100 else if (flags & CP_DMA_USE_L2)
1101 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1102
1103 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1104 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1105 radeon_emit(cs, header);
1106 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1107 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1108 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1109 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1110 radeon_emit(cs, command);
1111 } else {
1112 assert(!(flags & CP_DMA_USE_L2));
1113 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1114 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1115 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1116 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1117 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1118 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1119 radeon_emit(cs, command);
1120 }
1121
1122 /* CP DMA is executed in ME, but index buffers are read by PFP.
1123 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1124 * indices. If we wanted to execute CP DMA in PFP, this packet
1125 * should precede it.
1126 */
1127 if (flags & CP_DMA_SYNC) {
1128 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1129 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1130 radeon_emit(cs, 0);
1131 }
1132
1133 /* CP will see the sync flag and wait for all DMAs to complete. */
1134 cmd_buffer->state.dma_is_busy = false;
1135 }
1136
1137 if (unlikely(cmd_buffer->device->trace_bo))
1138 radv_cmd_buffer_trace_emit(cmd_buffer);
1139 }
1140
1141 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1142 unsigned size)
1143 {
1144 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1145 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1146
1147 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1148 aligned_size, CP_DMA_USE_L2);
1149 }
1150
1151 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1152 uint64_t remaining_size, unsigned *flags)
1153 {
1154
1155 /* Flush the caches for the first copy only.
1156 * Also wait for the previous CP DMA operations.
1157 */
1158 if (cmd_buffer->state.flush_bits) {
1159 si_emit_cache_flush(cmd_buffer);
1160 *flags |= CP_DMA_RAW_WAIT;
1161 }
1162
1163 /* Do the synchronization after the last dma, so that all data
1164 * is written to memory.
1165 */
1166 if (byte_count == remaining_size)
1167 *flags |= CP_DMA_SYNC;
1168 }
1169
1170 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1171 {
1172 uint64_t va;
1173 uint32_t offset;
1174 unsigned dma_flags = 0;
1175 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1176 void *ptr;
1177
1178 assert(size < SI_CPDMA_ALIGNMENT);
1179
1180 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1181
1182 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1183 va += offset;
1184
1185 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1186
1187 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1188 dma_flags);
1189 }
1190
1191 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1192 uint64_t src_va, uint64_t dest_va,
1193 uint64_t size)
1194 {
1195 uint64_t main_src_va, main_dest_va;
1196 uint64_t skipped_size = 0, realign_size = 0;
1197
1198 /* Assume that we are not going to sync after the last DMA operation. */
1199 cmd_buffer->state.dma_is_busy = true;
1200
1201 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1202 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1203 /* If the size is not aligned, we must add a dummy copy at the end
1204 * just to align the internal counter. Otherwise, the DMA engine
1205 * would slow down by an order of magnitude for following copies.
1206 */
1207 if (size % SI_CPDMA_ALIGNMENT)
1208 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1209
1210 /* If the copy begins unaligned, we must start copying from the next
1211 * aligned block and the skipped part should be copied after everything
1212 * else has been copied. Only the src alignment matters, not dst.
1213 */
1214 if (src_va % SI_CPDMA_ALIGNMENT) {
1215 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1216 /* The main part will be skipped if the size is too small. */
1217 skipped_size = MIN2(skipped_size, size);
1218 size -= skipped_size;
1219 }
1220 }
1221 main_src_va = src_va + skipped_size;
1222 main_dest_va = dest_va + skipped_size;
1223
1224 while (size) {
1225 unsigned dma_flags = 0;
1226 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1227
1228 si_cp_dma_prepare(cmd_buffer, byte_count,
1229 size + skipped_size + realign_size,
1230 &dma_flags);
1231
1232 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1233 byte_count, dma_flags);
1234
1235 size -= byte_count;
1236 main_src_va += byte_count;
1237 main_dest_va += byte_count;
1238 }
1239
1240 if (skipped_size) {
1241 unsigned dma_flags = 0;
1242
1243 si_cp_dma_prepare(cmd_buffer, skipped_size,
1244 size + skipped_size + realign_size,
1245 &dma_flags);
1246
1247 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1248 skipped_size, dma_flags);
1249 }
1250 if (realign_size)
1251 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1252 }
1253
1254 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1255 uint64_t size, unsigned value)
1256 {
1257
1258 if (!size)
1259 return;
1260
1261 assert(va % 4 == 0 && size % 4 == 0);
1262
1263 /* Assume that we are not going to sync after the last DMA operation. */
1264 cmd_buffer->state.dma_is_busy = true;
1265
1266 while (size) {
1267 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1268 unsigned dma_flags = CP_DMA_CLEAR;
1269
1270 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1271
1272 /* Emit the clear packet. */
1273 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1274 dma_flags);
1275
1276 size -= byte_count;
1277 va += byte_count;
1278 }
1279 }
1280
1281 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1282 {
1283 if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
1284 return;
1285
1286 if (!cmd_buffer->state.dma_is_busy)
1287 return;
1288
1289 /* Issue a dummy DMA that copies zero bytes.
1290 *
1291 * The DMA engine will see that there's no work to do and skip this
1292 * DMA request, however, the CP will see the sync flag and still wait
1293 * for all DMAs to complete.
1294 */
1295 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1296
1297 cmd_buffer->state.dma_is_busy = false;
1298 }
1299
1300 /* For MSAA sample positions. */
1301 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1302 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1303 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1304 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1305 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1306
1307
1308 /* 2xMSAA
1309 * There are two locations (4, 4), (-4, -4). */
1310 const uint32_t eg_sample_locs_2x[4] = {
1311 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1312 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1313 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1314 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1315 };
1316 const unsigned eg_max_dist_2x = 4;
1317 /* 4xMSAA
1318 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1319 const uint32_t eg_sample_locs_4x[4] = {
1320 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1321 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1322 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1323 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1324 };
1325 const unsigned eg_max_dist_4x = 6;
1326
1327 /* Cayman 8xMSAA */
1328 static const uint32_t cm_sample_locs_8x[] = {
1329 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1330 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1331 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1332 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1333 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1334 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1335 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1336 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1337 };
1338 static const unsigned cm_max_dist_8x = 8;
1339 /* Cayman 16xMSAA */
1340 static const uint32_t cm_sample_locs_16x[] = {
1341 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1342 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1343 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1344 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1345 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1346 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1347 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1348 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1349 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1350 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1351 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1352 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1353 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1354 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1355 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1356 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1357 };
1358 static const unsigned cm_max_dist_16x = 8;
1359
1360 unsigned radv_cayman_get_maxdist(int log_samples)
1361 {
1362 unsigned max_dist[] = {
1363 0,
1364 eg_max_dist_2x,
1365 eg_max_dist_4x,
1366 cm_max_dist_8x,
1367 cm_max_dist_16x
1368 };
1369 return max_dist[log_samples];
1370 }
1371
1372 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
1373 {
1374 switch (nr_samples) {
1375 default:
1376 case 1:
1377 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1378 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1379 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1380 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1381 break;
1382 case 2:
1383 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1384 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1385 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1386 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1387 break;
1388 case 4:
1389 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1390 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1391 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1392 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1393 break;
1394 case 8:
1395 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1396 radeon_emit(cs, cm_sample_locs_8x[0]);
1397 radeon_emit(cs, cm_sample_locs_8x[4]);
1398 radeon_emit(cs, 0);
1399 radeon_emit(cs, 0);
1400 radeon_emit(cs, cm_sample_locs_8x[1]);
1401 radeon_emit(cs, cm_sample_locs_8x[5]);
1402 radeon_emit(cs, 0);
1403 radeon_emit(cs, 0);
1404 radeon_emit(cs, cm_sample_locs_8x[2]);
1405 radeon_emit(cs, cm_sample_locs_8x[6]);
1406 radeon_emit(cs, 0);
1407 radeon_emit(cs, 0);
1408 radeon_emit(cs, cm_sample_locs_8x[3]);
1409 radeon_emit(cs, cm_sample_locs_8x[7]);
1410 break;
1411 case 16:
1412 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1413 radeon_emit(cs, cm_sample_locs_16x[0]);
1414 radeon_emit(cs, cm_sample_locs_16x[4]);
1415 radeon_emit(cs, cm_sample_locs_16x[8]);
1416 radeon_emit(cs, cm_sample_locs_16x[12]);
1417 radeon_emit(cs, cm_sample_locs_16x[1]);
1418 radeon_emit(cs, cm_sample_locs_16x[5]);
1419 radeon_emit(cs, cm_sample_locs_16x[9]);
1420 radeon_emit(cs, cm_sample_locs_16x[13]);
1421 radeon_emit(cs, cm_sample_locs_16x[2]);
1422 radeon_emit(cs, cm_sample_locs_16x[6]);
1423 radeon_emit(cs, cm_sample_locs_16x[10]);
1424 radeon_emit(cs, cm_sample_locs_16x[14]);
1425 radeon_emit(cs, cm_sample_locs_16x[3]);
1426 radeon_emit(cs, cm_sample_locs_16x[7]);
1427 radeon_emit(cs, cm_sample_locs_16x[11]);
1428 radeon_emit(cs, cm_sample_locs_16x[15]);
1429 break;
1430 }
1431 }
1432
1433 static void radv_cayman_get_sample_position(struct radv_device *device,
1434 unsigned sample_count,
1435 unsigned sample_index, float *out_value)
1436 {
1437 int offset, index;
1438 struct {
1439 int idx:4;
1440 } val;
1441 switch (sample_count) {
1442 case 1:
1443 default:
1444 out_value[0] = out_value[1] = 0.5;
1445 break;
1446 case 2:
1447 offset = 4 * (sample_index * 2);
1448 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1449 out_value[0] = (float)(val.idx + 8) / 16.0f;
1450 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1451 out_value[1] = (float)(val.idx + 8) / 16.0f;
1452 break;
1453 case 4:
1454 offset = 4 * (sample_index * 2);
1455 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1456 out_value[0] = (float)(val.idx + 8) / 16.0f;
1457 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1458 out_value[1] = (float)(val.idx + 8) / 16.0f;
1459 break;
1460 case 8:
1461 offset = 4 * (sample_index % 4 * 2);
1462 index = (sample_index / 4) * 4;
1463 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1464 out_value[0] = (float)(val.idx + 8) / 16.0f;
1465 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1466 out_value[1] = (float)(val.idx + 8) / 16.0f;
1467 break;
1468 case 16:
1469 offset = 4 * (sample_index % 4 * 2);
1470 index = (sample_index / 4) * 4;
1471 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1472 out_value[0] = (float)(val.idx + 8) / 16.0f;
1473 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1474 out_value[1] = (float)(val.idx + 8) / 16.0f;
1475 break;
1476 }
1477 }
1478
1479 void radv_device_init_msaa(struct radv_device *device)
1480 {
1481 int i;
1482 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1483
1484 for (i = 0; i < 2; i++)
1485 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1486 for (i = 0; i < 4; i++)
1487 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1488 for (i = 0; i < 8; i++)
1489 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1490 for (i = 0; i < 16; i++)
1491 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1492 }