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3ca66acb36474854d4aeb9f30cc19bcd5cfdeafa
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 bool has_clear_state = physical_device->rad_info.has_clear_state;
163 int i;
164
165 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
166 if (physical_device->rad_info.drm_minor < 6) {
167 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
168 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
169 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
170 }
171
172 if (has_clear_state) {
173 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
174 radeon_emit(cs, 0);
175 }
176
177 if (physical_device->rad_info.chip_class <= GFX8)
178 si_set_raster_config(physical_device, cs);
179
180 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
181 if (!has_clear_state)
182 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
183
184 /* FIXME calculate these values somehow ??? */
185 if (physical_device->rad_info.chip_class <= GFX8) {
186 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
187 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
188 }
189
190 if (!has_clear_state) {
191 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
192 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
193 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
194 }
195
196 if (physical_device->rad_info.chip_class <= GFX9)
197 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
198 if (!has_clear_state)
199 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
200 if (physical_device->rad_info.chip_class < GFX7)
201 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
202 S_008A14_CLIP_VTX_REORDER_ENA(1));
203
204 if (!has_clear_state)
205 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
206
207 /* CLEAR_STATE doesn't clear these correctly on certain generations.
208 * I don't know why. Deduced by trial and error.
209 */
210 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
211 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
212 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
213 S_028204_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
215 S_028240_WINDOW_OFFSET_DISABLE(1));
216 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
217 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
218 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
219 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
220 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
221 }
222
223 if (!has_clear_state) {
224 for (i = 0; i < 16; i++) {
225 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
226 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
227 }
228 }
229
230 if (!has_clear_state) {
231 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
232 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
233 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
234 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
235 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
236 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
237 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
238 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
239 }
240
241 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
242 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
243 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
244
245 if (physical_device->rad_info.chip_class >= GFX10) {
246 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
247 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
248 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
249 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
250 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
251 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
252 } else if (physical_device->rad_info.chip_class == GFX9) {
253 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
254 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
255 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
256 } else {
257 /* These registers, when written, also overwrite the
258 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
259 * them. It would be an issue if there was another UMD
260 * changing them.
261 */
262 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
263 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
264 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
265 }
266
267 if (physical_device->rad_info.chip_class >= GFX7) {
268 if (physical_device->rad_info.chip_class >= GFX10) {
269 /* Logical CUs 16 - 31 */
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
271 3, S_00B404_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
273 3, S_00B104_CU_EN(0xffff));
274 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
275 3, S_00B004_CU_EN(0xffff));
276 }
277
278 if (physical_device->rad_info.chip_class >= GFX9) {
279 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
281 } else {
282 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
283 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
285 S_00B41C_WAVE_LIMIT(0x3F));
286 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
287 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
288 /* If this is 0, Bonaire can hang even if GS isn't being used.
289 * Other chips are unaffected. These are suboptimal values,
290 * but we don't use on-chip GS.
291 */
292 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
293 S_028A44_ES_VERTS_PER_SUBGRP(64) |
294 S_028A44_GS_PRIMS_PER_SUBGRP(4));
295 }
296
297 /* Compute LATE_ALLOC_VS.LIMIT. */
298 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
299 unsigned late_alloc_limit; /* The limit is per SH. */
300
301 if (physical_device->rad_info.family == CHIP_KABINI) {
302 late_alloc_limit = 0; /* Potential hang on Kabini. */
303 } else if (num_cu_per_sh <= 4) {
304 /* Too few available compute units per SH. Disallowing
305 * VS to run on one CU could hurt us more than late VS
306 * allocation would help.
307 *
308 * 2 is the highest safe number that allows us to keep
309 * all CUs enabled.
310 */
311 late_alloc_limit = 2;
312 } else {
313 /* This is a good initial value, allowing 1 late_alloc
314 * wave per SIMD on num_cu - 2.
315 */
316 late_alloc_limit = (num_cu_per_sh - 2) * 4;
317 }
318
319 unsigned late_alloc_limit_gs = late_alloc_limit;
320 unsigned cu_mask_vs = 0xffff;
321 unsigned cu_mask_gs = 0xffff;
322
323 if (late_alloc_limit > 2) {
324 if (physical_device->rad_info.chip_class >= GFX10) {
325 /* CU2 & CU3 disabled because of the dual CU design */
326 cu_mask_vs = 0xfff3;
327 cu_mask_gs = 0xfff3; /* NGG only */
328 } else {
329 cu_mask_vs = 0xfffe; /* 1 CU disabled */
330 }
331 }
332
333 /* Don't use late alloc for NGG on Navi14 due to a hw bug. */
334 if (physical_device->rad_info.family == CHIP_NAVI14) {
335 late_alloc_limit_gs = 0;
336 cu_mask_gs = 0xffff;
337 }
338
339 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
340 3, S_00B118_CU_EN(cu_mask_vs) |
341 S_00B118_WAVE_LIMIT(0x3F));
342 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
343 S_00B11C_LIMIT(late_alloc_limit));
344
345 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
346 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
347
348 if (physical_device->rad_info.chip_class >= GFX10) {
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
350 3, S_00B204_CU_EN(0xffff) |
351 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
352 }
353
354 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
355 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
356 }
357
358 if (physical_device->rad_info.chip_class >= GFX10) {
359 /* Break up a pixel wave if it contains deallocs for more than
360 * half the parameter cache.
361 *
362 * To avoid a deadlock where pixel waves aren't launched
363 * because they're waiting for more pixels while the frontend
364 * is stuck waiting for PC space, the maximum allowed value is
365 * the size of the PC minus the largest possible allocation for
366 * a single primitive shader subgroup.
367 */
368 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
369 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
370 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
371 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
372 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
373 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
374 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
375 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
376 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
377 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
378 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
379
380 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
381 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
382 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
383 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
384 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
385 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
386 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
387 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
388 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
389 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
390
391 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
392 S_00B0C0_SOFT_GROUPING_EN(1) |
393 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
394 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
395
396 if (physical_device->rad_info.family == CHIP_NAVI10 ||
397 physical_device->rad_info.family == CHIP_NAVI12 ||
398 physical_device->rad_info.family == CHIP_NAVI14) {
399 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
400 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
401 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
402 }
403
404 /* TODO: For culling, replace 128 with 256. */
405 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
406 S_030980_OVERSUB_EN(1) |
407 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
408 }
409
410 if (physical_device->rad_info.chip_class >= GFX8) {
411 uint32_t vgt_tess_distribution;
412
413 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
414 S_028B50_ACCUM_TRI(11) |
415 S_028B50_ACCUM_QUAD(11) |
416 S_028B50_DONUT_SPLIT(16);
417
418 if (physical_device->rad_info.family == CHIP_FIJI ||
419 physical_device->rad_info.family >= CHIP_POLARIS10)
420 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
421
422 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
423 vgt_tess_distribution);
424 } else if (!has_clear_state) {
425 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
426 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
427 }
428
429 if (physical_device->rad_info.chip_class >= GFX9) {
430 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
431 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
432 S_028C48_MAX_PRIM_PER_BATCH(1023));
433 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
434 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
435 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
436 }
437
438 unsigned tmp = (unsigned)(1.0 * 8.0);
439 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
440 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
441 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
442 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
443 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
444
445 if (!has_clear_state) {
446 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
447 S_028004_ZPASS_INCREMENT_DISABLE(1));
448 }
449
450 /* Enable the Polaris small primitive filter control.
451 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
452 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
453 * and AMDVLK doesn't have a workaround as well.
454 */
455 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
456 unsigned small_prim_filter_cntl =
457 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
458 /* Workaround for a hw line bug. */
459 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
460
461 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
462 small_prim_filter_cntl);
463 }
464
465 si_emit_compute(physical_device, cs);
466 }
467
468 void
469 cik_create_gfx_config(struct radv_device *device)
470 {
471 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
472 if (!cs)
473 return;
474
475 si_emit_graphics(device->physical_device, cs);
476
477 while (cs->cdw & 7) {
478 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
479 radeon_emit(cs, 0x80000000);
480 else
481 radeon_emit(cs, 0xffff1000);
482 }
483
484 device->gfx_init = device->ws->buffer_create(device->ws,
485 cs->cdw * 4, 4096,
486 RADEON_DOMAIN_GTT,
487 RADEON_FLAG_CPU_ACCESS|
488 RADEON_FLAG_NO_INTERPROCESS_SHARING |
489 RADEON_FLAG_READ_ONLY,
490 RADV_BO_PRIORITY_CS);
491 if (!device->gfx_init)
492 goto fail;
493
494 void *map = device->ws->buffer_map(device->gfx_init);
495 if (!map) {
496 device->ws->buffer_destroy(device->gfx_init);
497 device->gfx_init = NULL;
498 goto fail;
499 }
500 memcpy(map, cs->buf, cs->cdw * 4);
501
502 device->ws->buffer_unmap(device->gfx_init);
503 device->gfx_init_size_dw = cs->cdw;
504 fail:
505 device->ws->cs_destroy(cs);
506 }
507
508 static void
509 get_viewport_xform(const VkViewport *viewport,
510 float scale[3], float translate[3])
511 {
512 float x = viewport->x;
513 float y = viewport->y;
514 float half_width = 0.5f * viewport->width;
515 float half_height = 0.5f * viewport->height;
516 double n = viewport->minDepth;
517 double f = viewport->maxDepth;
518
519 scale[0] = half_width;
520 translate[0] = half_width + x;
521 scale[1] = half_height;
522 translate[1] = half_height + y;
523
524 scale[2] = (f - n);
525 translate[2] = n;
526 }
527
528 void
529 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
530 int count, const VkViewport *viewports)
531 {
532 int i;
533
534 assert(count);
535 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
536 first_vp * 4 * 6, count * 6);
537
538 for (i = 0; i < count; i++) {
539 float scale[3], translate[3];
540
541
542 get_viewport_xform(&viewports[i], scale, translate);
543 radeon_emit(cs, fui(scale[0]));
544 radeon_emit(cs, fui(translate[0]));
545 radeon_emit(cs, fui(scale[1]));
546 radeon_emit(cs, fui(translate[1]));
547 radeon_emit(cs, fui(scale[2]));
548 radeon_emit(cs, fui(translate[2]));
549 }
550
551 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
552 first_vp * 4 * 2, count * 2);
553 for (i = 0; i < count; i++) {
554 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
555 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
556 radeon_emit(cs, fui(zmin));
557 radeon_emit(cs, fui(zmax));
558 }
559 }
560
561 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
562 {
563 float scale[3], translate[3];
564 VkRect2D rect;
565
566 get_viewport_xform(viewport, scale, translate);
567
568 rect.offset.x = translate[0] - fabs(scale[0]);
569 rect.offset.y = translate[1] - fabs(scale[1]);
570 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
571 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
572
573 return rect;
574 }
575
576 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
577 VkRect2D ret;
578 ret.offset.x = MAX2(a->offset.x, b->offset.x);
579 ret.offset.y = MAX2(a->offset.y, b->offset.y);
580 ret.extent.width = MIN2(a->offset.x + a->extent.width,
581 b->offset.x + b->extent.width) - ret.offset.x;
582 ret.extent.height = MIN2(a->offset.y + a->extent.height,
583 b->offset.y + b->extent.height) - ret.offset.y;
584 return ret;
585 }
586
587 void
588 si_write_scissors(struct radeon_cmdbuf *cs, int first,
589 int count, const VkRect2D *scissors,
590 const VkViewport *viewports, bool can_use_guardband)
591 {
592 int i;
593 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
594 const float max_range = 32767.0f;
595 if (!count)
596 return;
597
598 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
599 for (i = 0; i < count; i++) {
600 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
601 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
602
603 get_viewport_xform(viewports + i, scale, translate);
604 scale[0] = fabsf(scale[0]);
605 scale[1] = fabsf(scale[1]);
606
607 if (scale[0] < 0.5)
608 scale[0] = 0.5;
609 if (scale[1] < 0.5)
610 scale[1] = 0.5;
611
612 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
613 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
614
615 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
616 S_028250_TL_Y(scissor.offset.y) |
617 S_028250_WINDOW_OFFSET_DISABLE(1));
618 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
619 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
620 }
621 if (!can_use_guardband) {
622 guardband_x = 1.0;
623 guardband_y = 1.0;
624 }
625
626 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
627 radeon_emit(cs, fui(guardband_y));
628 radeon_emit(cs, fui(1.0));
629 radeon_emit(cs, fui(guardband_x));
630 radeon_emit(cs, fui(1.0));
631 }
632
633 static inline unsigned
634 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
635 {
636 if (num == 0)
637 return 0;
638
639 if (info->incr == 0)
640 return 0;
641
642 if (num < info->min)
643 return 0;
644
645 return 1 + ((num - info->min) / info->incr);
646 }
647
648 uint32_t
649 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
650 bool instanced_draw, bool indirect_draw,
651 bool count_from_stream_output,
652 uint32_t draw_vertex_count)
653 {
654 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
655 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
656 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
657 const unsigned max_primgroup_in_wave = 2;
658 /* SWITCH_ON_EOP(0) is always preferable. */
659 bool wd_switch_on_eop = false;
660 bool ia_switch_on_eop = false;
661 bool ia_switch_on_eoi = false;
662 bool partial_vs_wave = false;
663 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
664 bool multi_instances_smaller_than_primgroup;
665
666 multi_instances_smaller_than_primgroup = indirect_draw;
667 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
668 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
669 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
670 multi_instances_smaller_than_primgroup = true;
671 }
672
673 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
674 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
675
676 if (chip_class >= GFX7) {
677 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
678
679 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
680 * We don't know that for indirect drawing, so treat it as
681 * always problematic. */
682 if (family == CHIP_HAWAII &&
683 (instanced_draw || indirect_draw))
684 wd_switch_on_eop = true;
685
686 /* Performance recommendation for 4 SE Gfx7-8 parts if
687 * instances are smaller than a primgroup.
688 * Assume indirect draws always use small instances.
689 * This is needed for good VS wave utilization.
690 */
691 if (chip_class <= GFX8 &&
692 info->max_se == 4 &&
693 multi_instances_smaller_than_primgroup)
694 wd_switch_on_eop = true;
695
696 /* Required on GFX7 and later. */
697 if (info->max_se > 2 && !wd_switch_on_eop)
698 ia_switch_on_eoi = true;
699
700 /* Required by Hawaii and, for some special cases, by GFX8. */
701 if (ia_switch_on_eoi &&
702 (family == CHIP_HAWAII ||
703 (chip_class == GFX8 &&
704 /* max primgroup in wave is always 2 - leave this for documentation */
705 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
706 partial_vs_wave = true;
707
708 /* Instancing bug on Bonaire. */
709 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
710 (instanced_draw || indirect_draw))
711 partial_vs_wave = true;
712
713 /* Hardware requirement when drawing primitives from a stream
714 * output buffer.
715 */
716 if (count_from_stream_output)
717 wd_switch_on_eop = true;
718
719 /* If the WD switch is false, the IA switch must be false too. */
720 assert(wd_switch_on_eop || !ia_switch_on_eop);
721 }
722 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
723 if (chip_class <= GFX8 && ia_switch_on_eoi)
724 partial_es_wave = true;
725
726 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
727 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
728 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
729 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
730 */
731 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
732 bool set_vgt_flush = indirect_draw;
733 if (!set_vgt_flush && instanced_draw) {
734 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
735 if (num_prims <= 1)
736 set_vgt_flush = true;
737 }
738 if (set_vgt_flush)
739 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
740 }
741 }
742
743 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
744 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
745 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
746 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
747 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
748 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
749
750 }
751
752 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
753 enum chip_class chip_class,
754 bool is_mec,
755 unsigned event, unsigned event_flags,
756 unsigned dst_sel, unsigned data_sel,
757 uint64_t va,
758 uint32_t new_fence,
759 uint64_t gfx9_eop_bug_va)
760 {
761 unsigned op = EVENT_TYPE(event) |
762 EVENT_INDEX(event == V_028A90_CS_DONE ||
763 event == V_028A90_PS_DONE ? 6 : 5) |
764 event_flags;
765 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
766 unsigned sel = EOP_DST_SEL(dst_sel) |
767 EOP_DATA_SEL(data_sel);
768
769 /* Wait for write confirmation before writing data, but don't send
770 * an interrupt. */
771 if (data_sel != EOP_DATA_SEL_DISCARD)
772 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
773
774 if (chip_class >= GFX9 || is_gfx8_mec) {
775 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
776 * counters) must immediately precede every timestamp event to
777 * prevent a GPU hang on GFX9.
778 */
779 if (chip_class == GFX9 && !is_mec) {
780 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
781 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
782 radeon_emit(cs, gfx9_eop_bug_va);
783 radeon_emit(cs, gfx9_eop_bug_va >> 32);
784 }
785
786 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
787 radeon_emit(cs, op);
788 radeon_emit(cs, sel);
789 radeon_emit(cs, va); /* address lo */
790 radeon_emit(cs, va >> 32); /* address hi */
791 radeon_emit(cs, new_fence); /* immediate data lo */
792 radeon_emit(cs, 0); /* immediate data hi */
793 if (!is_gfx8_mec)
794 radeon_emit(cs, 0); /* unused */
795 } else {
796 if (chip_class == GFX7 ||
797 chip_class == GFX8) {
798 /* Two EOP events are required to make all engines go idle
799 * (and optional cache flushes executed) before the timestamp
800 * is written.
801 */
802 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
803 radeon_emit(cs, op);
804 radeon_emit(cs, va);
805 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
806 radeon_emit(cs, 0); /* immediate data */
807 radeon_emit(cs, 0); /* unused */
808 }
809
810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
811 radeon_emit(cs, op);
812 radeon_emit(cs, va);
813 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
814 radeon_emit(cs, new_fence); /* immediate data */
815 radeon_emit(cs, 0); /* unused */
816 }
817 }
818
819 void
820 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
821 uint32_t ref, uint32_t mask)
822 {
823 assert(op == WAIT_REG_MEM_EQUAL ||
824 op == WAIT_REG_MEM_NOT_EQUAL ||
825 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
826
827 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
828 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
829 radeon_emit(cs, va);
830 radeon_emit(cs, va >> 32);
831 radeon_emit(cs, ref); /* reference value */
832 radeon_emit(cs, mask); /* mask */
833 radeon_emit(cs, 4); /* poll interval */
834 }
835
836 static void
837 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
838 bool is_mec,
839 bool is_gfx9,
840 unsigned cp_coher_cntl)
841 {
842 if (is_mec || is_gfx9) {
843 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
844 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
845 PKT3_SHADER_TYPE_S(is_mec));
846 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
847 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
848 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
849 radeon_emit(cs, 0); /* CP_COHER_BASE */
850 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
851 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
852 } else {
853 /* ACQUIRE_MEM is only required on a compute ring. */
854 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
855 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
856 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
857 radeon_emit(cs, 0); /* CP_COHER_BASE */
858 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
859 }
860 }
861
862 static void
863 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
864 enum chip_class chip_class,
865 uint32_t *flush_cnt,
866 uint64_t flush_va,
867 bool is_mec,
868 enum radv_cmd_flush_bits flush_bits,
869 uint64_t gfx9_eop_bug_va)
870 {
871 uint32_t gcr_cntl = 0;
872 unsigned cb_db_event = 0;
873
874 /* We don't need these. */
875 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
876
877 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
878 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
879 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
880 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
881 * to FORWARD when both L1 and L2 are written out (WB or INV).
882 */
883 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
884 }
885 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
886 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
887 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
888 /* Writeback and invalidate everything in L2. */
889 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
890 S_586_GLM_INV(1) | S_586_GLM_WB(1);
891 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
892 /* Writeback but do not invalidate.
893 * GLM doesn't support WB alone. If WB is set, INV must be set too.
894 */
895 gcr_cntl |= S_586_GL2_WB(1) |
896 S_586_GLM_WB(1) | S_586_GLM_INV(1);
897 }
898
899 /* TODO: Implement this new flag for GFX9+.
900 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
901 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
902 */
903
904 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
905 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
906 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
907 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
908 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
909 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
910 EVENT_INDEX(0));
911 }
912
913 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
914 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
915 /* Flush HTILE. Will wait for idle later. */
916 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
917 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
918 EVENT_INDEX(0));
919 }
920
921 /* First flush CB/DB, then L1/L2. */
922 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
923
924 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
925 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
926 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
927 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
928 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
929 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
930 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
931 } else {
932 assert(0);
933 }
934 } else {
935 /* Wait for graphics shaders to go idle if requested. */
936 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
937 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
938 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
939 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
940 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
941 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
942 }
943 }
944
945 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
948 }
949
950 if (cb_db_event) {
951 /* CB/DB flush and invalidate (or possibly just a wait for a
952 * meta flush) via RELEASE_MEM.
953 *
954 * Combine this with other cache flushes when possible; this
955 * requires affected shaders to be idle, so do it after the
956 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
957 * implied).
958 */
959 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
960 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
961 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
962 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
963 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
964 assert(G_586_GL2_US(gcr_cntl) == 0);
965 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
966 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
967 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
968 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
969 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
970
971 gcr_cntl &= C_586_GLM_WB &
972 C_586_GLM_INV &
973 C_586_GLV_INV &
974 C_586_GL1_INV &
975 C_586_GL2_INV &
976 C_586_GL2_WB; /* keep SEQ */
977
978 assert(flush_cnt);
979 (*flush_cnt)++;
980
981 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
982 S_490_GLM_WB(glm_wb) |
983 S_490_GLM_INV(glm_inv) |
984 S_490_GLV_INV(glv_inv) |
985 S_490_GL1_INV(gl1_inv) |
986 S_490_GL2_INV(gl2_inv) |
987 S_490_GL2_WB(gl2_wb) |
988 S_490_SEQ(gcr_seq),
989 EOP_DST_SEL_MEM,
990 EOP_DATA_SEL_VALUE_32BIT,
991 flush_va, *flush_cnt,
992 gfx9_eop_bug_va);
993
994 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
995 *flush_cnt, 0xffffffff);
996 }
997
998 /* VGT state sync */
999 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1000 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1001 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1002 }
1003
1004 /* Ignore fields that only modify the behavior of other fields. */
1005 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1006 /* Flush caches and wait for the caches to assert idle.
1007 * The cache flush is executed in the ME, but the PFP waits
1008 * for completion.
1009 */
1010 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1011 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1012 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1013 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1014 radeon_emit(cs, 0); /* CP_COHER_BASE */
1015 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1016 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1017 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1018 } else if ((cb_db_event ||
1019 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1020 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1021 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1022 && !is_mec) {
1023 /* We need to ensure that PFP waits as well. */
1024 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1025 radeon_emit(cs, 0);
1026 }
1027
1028 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1029 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1030 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1031 EVENT_INDEX(0));
1032 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1033 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1034 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1035 EVENT_INDEX(0));
1036 }
1037 }
1038
1039 void
1040 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1041 enum chip_class chip_class,
1042 uint32_t *flush_cnt,
1043 uint64_t flush_va,
1044 bool is_mec,
1045 enum radv_cmd_flush_bits flush_bits,
1046 uint64_t gfx9_eop_bug_va)
1047 {
1048 unsigned cp_coher_cntl = 0;
1049 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1050 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1051
1052 if (chip_class >= GFX10) {
1053 /* GFX10 cache flush handling is quite different. */
1054 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1055 is_mec, flush_bits, gfx9_eop_bug_va);
1056 return;
1057 }
1058
1059 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1060 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1061 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1062 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1063
1064 if (chip_class <= GFX8) {
1065 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1066 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1067 S_0085F0_CB0_DEST_BASE_ENA(1) |
1068 S_0085F0_CB1_DEST_BASE_ENA(1) |
1069 S_0085F0_CB2_DEST_BASE_ENA(1) |
1070 S_0085F0_CB3_DEST_BASE_ENA(1) |
1071 S_0085F0_CB4_DEST_BASE_ENA(1) |
1072 S_0085F0_CB5_DEST_BASE_ENA(1) |
1073 S_0085F0_CB6_DEST_BASE_ENA(1) |
1074 S_0085F0_CB7_DEST_BASE_ENA(1);
1075
1076 /* Necessary for DCC */
1077 if (chip_class >= GFX8) {
1078 si_cs_emit_write_event_eop(cs,
1079 chip_class,
1080 is_mec,
1081 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1082 0,
1083 EOP_DST_SEL_MEM,
1084 EOP_DATA_SEL_DISCARD,
1085 0, 0,
1086 gfx9_eop_bug_va);
1087 }
1088 }
1089 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1090 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1091 S_0085F0_DB_DEST_BASE_ENA(1);
1092 }
1093 }
1094
1095 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1096 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1097 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1098 }
1099
1100 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1101 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1102 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1103 }
1104
1105 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1106 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1107 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1108 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1110 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1111 }
1112
1113 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1114 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1115 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1116 }
1117
1118 if (chip_class == GFX9 && flush_cb_db) {
1119 unsigned cb_db_event, tc_flags;
1120
1121 /* Set the CB/DB flush event. */
1122 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1123
1124 /* These are the only allowed combinations. If you need to
1125 * do multiple operations at once, do them separately.
1126 * All operations that invalidate L2 also seem to invalidate
1127 * metadata. Volatile (VOL) and WC flushes are not listed here.
1128 *
1129 * TC | TC_WB = writeback & invalidate L2 & L1
1130 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1131 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1132 * TC | TC_NC = invalidate L2 for MTYPE == NC
1133 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1134 * TCL1 = invalidate L1
1135 */
1136 tc_flags = EVENT_TC_ACTION_ENA |
1137 EVENT_TC_MD_ACTION_ENA;
1138
1139 /* Ideally flush TC together with CB/DB. */
1140 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1141 /* Writeback and invalidate everything in L2 & L1. */
1142 tc_flags = EVENT_TC_ACTION_ENA |
1143 EVENT_TC_WB_ACTION_ENA;
1144
1145
1146 /* Clear the flags. */
1147 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1148 RADV_CMD_FLAG_WB_L2 |
1149 RADV_CMD_FLAG_INV_VCACHE);
1150 }
1151 assert(flush_cnt);
1152 (*flush_cnt)++;
1153
1154 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1155 EOP_DST_SEL_MEM,
1156 EOP_DATA_SEL_VALUE_32BIT,
1157 flush_va, *flush_cnt,
1158 gfx9_eop_bug_va);
1159 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1160 *flush_cnt, 0xffffffff);
1161 }
1162
1163 /* VGT state sync */
1164 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1166 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1167 }
1168
1169 /* VGT streamout state sync */
1170 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1171 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1172 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1173 }
1174
1175 /* Make sure ME is idle (it executes most packets) before continuing.
1176 * This prevents read-after-write hazards between PFP and ME.
1177 */
1178 if ((cp_coher_cntl ||
1179 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1180 RADV_CMD_FLAG_INV_VCACHE |
1181 RADV_CMD_FLAG_INV_L2 |
1182 RADV_CMD_FLAG_WB_L2))) &&
1183 !is_mec) {
1184 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1185 radeon_emit(cs, 0);
1186 }
1187
1188 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1189 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1190 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1191 cp_coher_cntl |
1192 S_0085F0_TC_ACTION_ENA(1) |
1193 S_0085F0_TCL1_ACTION_ENA(1) |
1194 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1195 cp_coher_cntl = 0;
1196 } else {
1197 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1198 /* WB = write-back
1199 * NC = apply to non-coherent MTYPEs
1200 * (i.e. MTYPE <= 1, which is what we use everywhere)
1201 *
1202 * WB doesn't work without NC.
1203 */
1204 si_emit_acquire_mem(cs, is_mec,
1205 chip_class == GFX9,
1206 cp_coher_cntl |
1207 S_0301F0_TC_WB_ACTION_ENA(1) |
1208 S_0301F0_TC_NC_ACTION_ENA(1));
1209 cp_coher_cntl = 0;
1210 }
1211 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1212 si_emit_acquire_mem(cs, is_mec,
1213 chip_class == GFX9,
1214 cp_coher_cntl |
1215 S_0085F0_TCL1_ACTION_ENA(1));
1216 cp_coher_cntl = 0;
1217 }
1218 }
1219
1220 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1221 * Therefore, it should be last. Done in PFP.
1222 */
1223 if (cp_coher_cntl)
1224 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1225
1226 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1227 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1228 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1229 EVENT_INDEX(0));
1230 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1231 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1232 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1233 EVENT_INDEX(0));
1234 }
1235 }
1236
1237 void
1238 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1239 {
1240 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1241
1242 if (is_compute)
1243 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1244 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1245 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1246 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1247 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1248 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1249 RADV_CMD_FLAG_VGT_FLUSH |
1250 RADV_CMD_FLAG_START_PIPELINE_STATS |
1251 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1252
1253 if (!cmd_buffer->state.flush_bits)
1254 return;
1255
1256 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1257
1258 si_cs_emit_cache_flush(cmd_buffer->cs,
1259 cmd_buffer->device->physical_device->rad_info.chip_class,
1260 &cmd_buffer->gfx9_fence_idx,
1261 cmd_buffer->gfx9_fence_va,
1262 radv_cmd_buffer_uses_mec(cmd_buffer),
1263 cmd_buffer->state.flush_bits,
1264 cmd_buffer->gfx9_eop_bug_va);
1265
1266
1267 if (unlikely(cmd_buffer->device->trace_bo))
1268 radv_cmd_buffer_trace_emit(cmd_buffer);
1269
1270 /* Clear the caches that have been flushed to avoid syncing too much
1271 * when there is some pending active queries.
1272 */
1273 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1274
1275 cmd_buffer->state.flush_bits = 0;
1276
1277 /* If the driver used a compute shader for resetting a query pool, it
1278 * should be finished at this point.
1279 */
1280 cmd_buffer->pending_reset_query = false;
1281 }
1282
1283 /* sets the CP predication state using a boolean stored at va */
1284 void
1285 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1286 bool draw_visible, uint64_t va)
1287 {
1288 uint32_t op = 0;
1289
1290 if (va) {
1291 op = PRED_OP(PREDICATION_OP_BOOL64);
1292
1293 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1294 * zero, all rendering commands are discarded. Otherwise, they
1295 * are discarded if the value is non zero.
1296 */
1297 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1298 PREDICATION_DRAW_NOT_VISIBLE;
1299 }
1300 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1301 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1302 radeon_emit(cmd_buffer->cs, op);
1303 radeon_emit(cmd_buffer->cs, va);
1304 radeon_emit(cmd_buffer->cs, va >> 32);
1305 } else {
1306 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1307 radeon_emit(cmd_buffer->cs, va);
1308 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1309 }
1310 }
1311
1312 /* Set this if you want the 3D engine to wait until CP DMA is done.
1313 * It should be set on the last CP DMA packet. */
1314 #define CP_DMA_SYNC (1 << 0)
1315
1316 /* Set this if the source data was used as a destination in a previous CP DMA
1317 * packet. It's for preventing a read-after-write (RAW) hazard between two
1318 * CP DMA packets. */
1319 #define CP_DMA_RAW_WAIT (1 << 1)
1320 #define CP_DMA_USE_L2 (1 << 2)
1321 #define CP_DMA_CLEAR (1 << 3)
1322
1323 /* Alignment for optimal performance. */
1324 #define SI_CPDMA_ALIGNMENT 32
1325
1326 /* The max number of bytes that can be copied per packet. */
1327 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1328 {
1329 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1330 S_414_BYTE_COUNT_GFX9(~0u) :
1331 S_414_BYTE_COUNT_GFX6(~0u);
1332
1333 /* make it aligned for optimal performance */
1334 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1335 }
1336
1337 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1338 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1339 * clear value.
1340 */
1341 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1342 uint64_t dst_va, uint64_t src_va,
1343 unsigned size, unsigned flags)
1344 {
1345 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1346 uint32_t header = 0, command = 0;
1347
1348 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1349
1350 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1351 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1352 command |= S_414_BYTE_COUNT_GFX9(size);
1353 else
1354 command |= S_414_BYTE_COUNT_GFX6(size);
1355
1356 /* Sync flags. */
1357 if (flags & CP_DMA_SYNC)
1358 header |= S_411_CP_SYNC(1);
1359 else {
1360 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1361 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1362 else
1363 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1364 }
1365
1366 if (flags & CP_DMA_RAW_WAIT)
1367 command |= S_414_RAW_WAIT(1);
1368
1369 /* Src and dst flags. */
1370 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1371 !(flags & CP_DMA_CLEAR) &&
1372 src_va == dst_va)
1373 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1374 else if (flags & CP_DMA_USE_L2)
1375 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1376
1377 if (flags & CP_DMA_CLEAR)
1378 header |= S_411_SRC_SEL(V_411_DATA);
1379 else if (flags & CP_DMA_USE_L2)
1380 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1381
1382 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1383 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1384 radeon_emit(cs, header);
1385 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1386 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1387 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1388 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1389 radeon_emit(cs, command);
1390 } else {
1391 assert(!(flags & CP_DMA_USE_L2));
1392 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1393 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1394 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1395 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1396 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1397 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1398 radeon_emit(cs, command);
1399 }
1400
1401 /* CP DMA is executed in ME, but index buffers are read by PFP.
1402 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1403 * indices. If we wanted to execute CP DMA in PFP, this packet
1404 * should precede it.
1405 */
1406 if (flags & CP_DMA_SYNC) {
1407 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1408 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1409 radeon_emit(cs, 0);
1410 }
1411
1412 /* CP will see the sync flag and wait for all DMAs to complete. */
1413 cmd_buffer->state.dma_is_busy = false;
1414 }
1415
1416 if (unlikely(cmd_buffer->device->trace_bo))
1417 radv_cmd_buffer_trace_emit(cmd_buffer);
1418 }
1419
1420 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1421 unsigned size)
1422 {
1423 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1424 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1425
1426 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1427 aligned_size, CP_DMA_USE_L2);
1428 }
1429
1430 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1431 uint64_t remaining_size, unsigned *flags)
1432 {
1433
1434 /* Flush the caches for the first copy only.
1435 * Also wait for the previous CP DMA operations.
1436 */
1437 if (cmd_buffer->state.flush_bits) {
1438 si_emit_cache_flush(cmd_buffer);
1439 *flags |= CP_DMA_RAW_WAIT;
1440 }
1441
1442 /* Do the synchronization after the last dma, so that all data
1443 * is written to memory.
1444 */
1445 if (byte_count == remaining_size)
1446 *flags |= CP_DMA_SYNC;
1447 }
1448
1449 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1450 {
1451 uint64_t va;
1452 uint32_t offset;
1453 unsigned dma_flags = 0;
1454 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1455 void *ptr;
1456
1457 assert(size < SI_CPDMA_ALIGNMENT);
1458
1459 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1460
1461 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1462 va += offset;
1463
1464 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1465
1466 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1467 dma_flags);
1468 }
1469
1470 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1471 uint64_t src_va, uint64_t dest_va,
1472 uint64_t size)
1473 {
1474 uint64_t main_src_va, main_dest_va;
1475 uint64_t skipped_size = 0, realign_size = 0;
1476
1477 /* Assume that we are not going to sync after the last DMA operation. */
1478 cmd_buffer->state.dma_is_busy = true;
1479
1480 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1481 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1482 /* If the size is not aligned, we must add a dummy copy at the end
1483 * just to align the internal counter. Otherwise, the DMA engine
1484 * would slow down by an order of magnitude for following copies.
1485 */
1486 if (size % SI_CPDMA_ALIGNMENT)
1487 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1488
1489 /* If the copy begins unaligned, we must start copying from the next
1490 * aligned block and the skipped part should be copied after everything
1491 * else has been copied. Only the src alignment matters, not dst.
1492 */
1493 if (src_va % SI_CPDMA_ALIGNMENT) {
1494 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1495 /* The main part will be skipped if the size is too small. */
1496 skipped_size = MIN2(skipped_size, size);
1497 size -= skipped_size;
1498 }
1499 }
1500 main_src_va = src_va + skipped_size;
1501 main_dest_va = dest_va + skipped_size;
1502
1503 while (size) {
1504 unsigned dma_flags = 0;
1505 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1506
1507 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1508 /* DMA operations via L2 are coherent and faster.
1509 * TODO: GFX7-GFX9 should also support this but it
1510 * requires tests/benchmarks.
1511 */
1512 dma_flags |= CP_DMA_USE_L2;
1513 }
1514
1515 si_cp_dma_prepare(cmd_buffer, byte_count,
1516 size + skipped_size + realign_size,
1517 &dma_flags);
1518
1519 dma_flags &= ~CP_DMA_SYNC;
1520
1521 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1522 byte_count, dma_flags);
1523
1524 size -= byte_count;
1525 main_src_va += byte_count;
1526 main_dest_va += byte_count;
1527 }
1528
1529 if (skipped_size) {
1530 unsigned dma_flags = 0;
1531
1532 si_cp_dma_prepare(cmd_buffer, skipped_size,
1533 size + skipped_size + realign_size,
1534 &dma_flags);
1535
1536 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1537 skipped_size, dma_flags);
1538 }
1539 if (realign_size)
1540 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1541 }
1542
1543 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1544 uint64_t size, unsigned value)
1545 {
1546
1547 if (!size)
1548 return;
1549
1550 assert(va % 4 == 0 && size % 4 == 0);
1551
1552 /* Assume that we are not going to sync after the last DMA operation. */
1553 cmd_buffer->state.dma_is_busy = true;
1554
1555 while (size) {
1556 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1557 unsigned dma_flags = CP_DMA_CLEAR;
1558
1559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1560 /* DMA operations via L2 are coherent and faster.
1561 * TODO: GFX7-GFX9 should also support this but it
1562 * requires tests/benchmarks.
1563 */
1564 dma_flags |= CP_DMA_USE_L2;
1565 }
1566
1567 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1568
1569 /* Emit the clear packet. */
1570 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1571 dma_flags);
1572
1573 size -= byte_count;
1574 va += byte_count;
1575 }
1576 }
1577
1578 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1579 {
1580 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1581 return;
1582
1583 if (!cmd_buffer->state.dma_is_busy)
1584 return;
1585
1586 /* Issue a dummy DMA that copies zero bytes.
1587 *
1588 * The DMA engine will see that there's no work to do and skip this
1589 * DMA request, however, the CP will see the sync flag and still wait
1590 * for all DMAs to complete.
1591 */
1592 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1593
1594 cmd_buffer->state.dma_is_busy = false;
1595 }
1596
1597 /* For MSAA sample positions. */
1598 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1599 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1600 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1601 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1602 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1603
1604 /* For obtaining location coordinates from registers */
1605 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1606 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1607 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1608 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1609
1610 /* 1x MSAA */
1611 static const uint32_t sample_locs_1x =
1612 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1613 static const unsigned max_dist_1x = 0;
1614 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1615
1616 /* 2xMSAA */
1617 static const uint32_t sample_locs_2x =
1618 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1619 static const unsigned max_dist_2x = 4;
1620 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1621
1622 /* 4xMSAA */
1623 static const uint32_t sample_locs_4x =
1624 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1625 static const unsigned max_dist_4x = 6;
1626 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1627
1628 /* 8xMSAA */
1629 static const uint32_t sample_locs_8x[] = {
1630 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1631 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1632 /* The following are unused by hardware, but we emit them to IBs
1633 * instead of multiple SET_CONTEXT_REG packets. */
1634 0,
1635 0,
1636 };
1637 static const unsigned max_dist_8x = 7;
1638 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1639
1640 unsigned radv_get_default_max_sample_dist(int log_samples)
1641 {
1642 unsigned max_dist[] = {
1643 max_dist_1x,
1644 max_dist_2x,
1645 max_dist_4x,
1646 max_dist_8x,
1647 };
1648 return max_dist[log_samples];
1649 }
1650
1651 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1652 {
1653 switch (nr_samples) {
1654 default:
1655 case 1:
1656 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1657 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1658 radeon_emit(cs, centroid_priority_1x >> 32);
1659 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1660 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1661 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1662 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1663 break;
1664 case 2:
1665 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1666 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1667 radeon_emit(cs, centroid_priority_2x >> 32);
1668 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1669 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1670 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1671 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1672 break;
1673 case 4:
1674 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1675 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1676 radeon_emit(cs, centroid_priority_4x >> 32);
1677 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1678 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1679 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1680 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1681 break;
1682 case 8:
1683 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1684 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1685 radeon_emit(cs, centroid_priority_8x >> 32);
1686 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1687 radeon_emit_array(cs, sample_locs_8x, 4);
1688 radeon_emit_array(cs, sample_locs_8x, 4);
1689 radeon_emit_array(cs, sample_locs_8x, 4);
1690 radeon_emit_array(cs, sample_locs_8x, 2);
1691 break;
1692 }
1693 }
1694
1695 static void radv_get_sample_position(struct radv_device *device,
1696 unsigned sample_count,
1697 unsigned sample_index, float *out_value)
1698 {
1699 const uint32_t *sample_locs;
1700
1701 switch (sample_count) {
1702 case 1:
1703 default:
1704 sample_locs = &sample_locs_1x;
1705 break;
1706 case 2:
1707 sample_locs = &sample_locs_2x;
1708 break;
1709 case 4:
1710 sample_locs = &sample_locs_4x;
1711 break;
1712 case 8:
1713 sample_locs = sample_locs_8x;
1714 break;
1715 }
1716
1717 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1718 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1719 }
1720
1721 void radv_device_init_msaa(struct radv_device *device)
1722 {
1723 int i;
1724
1725 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1726
1727 for (i = 0; i < 2; i++)
1728 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1729 for (i = 0; i < 4; i++)
1730 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1731 for (i = 0; i < 8; i++)
1732 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1733 }