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4b2624cb8e2ca462835814978e6875e424875685
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 void
174 si_init_compute(struct radv_physical_device *physical_device,
175 struct radv_cmd_buffer *cmd_buffer)
176 {
177 struct radeon_winsys_cs *cs = cmd_buffer->cs;
178 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
182
183 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
184 radeon_emit(cs, 0);
185 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
186 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188
189 if (physical_device->rad_info.chip_class >= CIK) {
190 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
191 radeon_set_sh_reg_seq(cs,
192 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
193 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
194 S_00B864_SH1_CU_EN(0xffff));
195 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
196 S_00B868_SH1_CU_EN(0xffff));
197 }
198
199 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
200 * and is now per pipe, so it should be handled in the
201 * kernel if we want to use something other than the default value,
202 * which is now 0x22f.
203 */
204 if (physical_device->rad_info.chip_class <= SI) {
205 /* XXX: This should be:
206 * (number of compute units) * 4 * (waves per simd) - 1 */
207
208 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
209 0x190 /* Default value */);
210 }
211 }
212
213
214 void si_init_config(struct radv_physical_device *physical_device,
215 struct radv_cmd_buffer *cmd_buffer)
216 {
217 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
218 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
219 unsigned raster_config, raster_config_1;
220 int i;
221 struct radeon_winsys_cs *cs = cmd_buffer->cs;
222 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
223 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
224 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
225
226 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
227 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
228
229 /* FIXME calculate these values somehow ??? */
230 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
231 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
232 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
233
234 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
235 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
236
237 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
238 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
239 if (physical_device->rad_info.chip_class < CIK)
240 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
241 S_008A14_CLIP_VTX_REORDER_ENA(1));
242
243 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
244 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
245
246 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
247
248 for (i = 0; i < 16; i++) {
249 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
250 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
251 }
252
253 switch (physical_device->rad_info.family) {
254 case CHIP_TAHITI:
255 case CHIP_PITCAIRN:
256 raster_config = 0x2a00126a;
257 raster_config_1 = 0x00000000;
258 break;
259 case CHIP_VERDE:
260 raster_config = 0x0000124a;
261 raster_config_1 = 0x00000000;
262 break;
263 case CHIP_OLAND:
264 raster_config = 0x00000082;
265 raster_config_1 = 0x00000000;
266 break;
267 case CHIP_HAINAN:
268 raster_config = 0x00000000;
269 raster_config_1 = 0x00000000;
270 break;
271 case CHIP_BONAIRE:
272 raster_config = 0x16000012;
273 raster_config_1 = 0x00000000;
274 break;
275 case CHIP_HAWAII:
276 raster_config = 0x3a00161a;
277 raster_config_1 = 0x0000002e;
278 break;
279 case CHIP_FIJI:
280 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
281 /* old kernels with old tiling config */
282 raster_config = 0x16000012;
283 raster_config_1 = 0x0000002a;
284 } else {
285 raster_config = 0x3a00161a;
286 raster_config_1 = 0x0000002e;
287 }
288 break;
289 case CHIP_POLARIS10:
290 raster_config = 0x16000012;
291 raster_config_1 = 0x0000002a;
292 break;
293 case CHIP_POLARIS11:
294 raster_config = 0x16000012;
295 raster_config_1 = 0x00000000;
296 break;
297 case CHIP_TONGA:
298 raster_config = 0x16000012;
299 raster_config_1 = 0x0000002a;
300 break;
301 case CHIP_ICELAND:
302 if (num_rb == 1)
303 raster_config = 0x00000000;
304 else
305 raster_config = 0x00000002;
306 raster_config_1 = 0x00000000;
307 break;
308 case CHIP_CARRIZO:
309 raster_config = 0x00000002;
310 raster_config_1 = 0x00000000;
311 break;
312 case CHIP_KAVERI:
313 /* KV should be 0x00000002, but that causes problems with radeon */
314 raster_config = 0x00000000; /* 0x00000002 */
315 raster_config_1 = 0x00000000;
316 break;
317 case CHIP_KABINI:
318 case CHIP_MULLINS:
319 case CHIP_STONEY:
320 raster_config = 0x00000000;
321 raster_config_1 = 0x00000000;
322 break;
323 default:
324 fprintf(stderr,
325 "radeonsi: Unknown GPU, using 0 for raster_config\n");
326 raster_config = 0x00000000;
327 raster_config_1 = 0x00000000;
328 break;
329 }
330
331 /* Always use the default config when all backends are enabled
332 * (or when we failed to determine the enabled backends).
333 */
334 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
335 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
336 raster_config);
337 if (physical_device->rad_info.chip_class >= CIK)
338 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
339 raster_config_1);
340 } else {
341 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
342 }
343
344 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
345 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
346 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
347 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
348 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
349 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
350 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
351
352 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
353 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
354 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
355 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
356 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
357
358 radeon_set_context_reg(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
359 radeon_set_context_reg(cs, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
360 radeon_set_context_reg(cs, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
361 radeon_set_context_reg(cs, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
362
363 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
364 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
365 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
366 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
367 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
368 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
369
370 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
371 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
372 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
373
374 if (physical_device->rad_info.chip_class >= CIK) {
375 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
376 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
377 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
378
379 if (physical_device->rad_info.num_good_compute_units /
380 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
381 /* Too few available compute units per SH. Disallowing
382 * VS to run on CU0 could hurt us more than late VS
383 * allocation would help.
384 *
385 * LATE_ALLOC_VS = 2 is the highest safe number.
386 */
387 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
388 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
389 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
390 } else {
391 /* Set LATE_ALLOC_VS == 31. It should be less than
392 * the number of scratch waves. Limitations:
393 * - VS can't execute on CU0.
394 * - If HS writes outputs to LDS, LS can't execute on CU0.
395 */
396 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
397 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
398 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
399 }
400
401 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
402 }
403
404 if (physical_device->rad_info.chip_class >= VI) {
405 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
406 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
407 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
408 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
409 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
410 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
411 S_028B50_ACCUM_ISOLINE(32) |
412 S_028B50_ACCUM_TRI(11) |
413 S_028B50_ACCUM_QUAD(11) |
414 S_028B50_DONUT_SPLIT(16));
415 } else {
416 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
417 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
418 }
419
420 if (physical_device->rad_info.family == CHIP_STONEY)
421 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
422
423 si_init_compute(physical_device, cmd_buffer);
424 }
425
426 static void
427 get_viewport_xform(const VkViewport *viewport,
428 float scale[3], float translate[3])
429 {
430 float x = viewport->x;
431 float y = viewport->y;
432 float half_width = 0.5f * viewport->width;
433 float half_height = 0.5f * viewport->height;
434 double n = viewport->minDepth;
435 double f = viewport->maxDepth;
436
437 scale[0] = half_width;
438 translate[0] = half_width + x;
439 scale[1] = half_height;
440 translate[1] = half_height + y;
441
442 scale[2] = (f - n);
443 translate[2] = n;
444 }
445
446 void
447 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
448 int count, const VkViewport *viewports)
449 {
450 int i;
451
452 if (count == 0) {
453 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
454 radeon_emit(cs, fui(1.0));
455 radeon_emit(cs, fui(0.0));
456 radeon_emit(cs, fui(1.0));
457 radeon_emit(cs, fui(0.0));
458 radeon_emit(cs, fui(1.0));
459 radeon_emit(cs, fui(0.0));
460
461 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
462 radeon_emit(cs, fui(0.0));
463 radeon_emit(cs, fui(1.0));
464
465 return;
466 }
467 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
468 first_vp * 4 * 6, count * 6);
469
470 for (i = 0; i < count; i++) {
471 float scale[3], translate[3];
472
473
474 get_viewport_xform(&viewports[i], scale, translate);
475 radeon_emit(cs, fui(scale[0]));
476 radeon_emit(cs, fui(translate[0]));
477 radeon_emit(cs, fui(scale[1]));
478 radeon_emit(cs, fui(translate[1]));
479 radeon_emit(cs, fui(scale[2]));
480 radeon_emit(cs, fui(translate[2]));
481 }
482
483 for (i = 0; i < count; i++) {
484 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
485 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
486 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
487 first_vp * 4 * 2, count * 2);
488 radeon_emit(cs, fui(zmin));
489 radeon_emit(cs, fui(zmax));
490 }
491 }
492
493 void
494 si_write_scissors(struct radeon_winsys_cs *cs, int first,
495 int count, const VkRect2D *scissors)
496 {
497 int i;
498 if (count == 0)
499 return;
500
501 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
502 for (i = 0; i < count; i++) {
503 radeon_emit(cs, S_028250_TL_X(scissors[i].offset.x) |
504 S_028250_TL_Y(scissors[i].offset.y) |
505 S_028250_WINDOW_OFFSET_DISABLE(1));
506 radeon_emit(cs, S_028254_BR_X(scissors[i].offset.x + scissors[i].extent.width) |
507 S_028254_BR_Y(scissors[i].offset.y + scissors[i].extent.height));
508 }
509 }
510
511 uint32_t
512 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer)
513 {
514 enum chip_class chip_class = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class;
515 struct radeon_info *info = &cmd_buffer->device->instance->physicalDevice.rad_info;
516 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
517 unsigned primgroup_size = 128; /* recommended without a GS */
518 unsigned max_primgroup_in_wave = 2;
519 /* SWITCH_ON_EOP(0) is always preferable. */
520 bool wd_switch_on_eop = false;
521 bool ia_switch_on_eop = false;
522 bool ia_switch_on_eoi = false;
523 bool partial_vs_wave = false;
524 bool partial_es_wave = false;
525
526 /* TODO GS */
527
528 /* TODO TES */
529
530 /* TODO linestipple */
531
532 if (chip_class >= CIK) {
533 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
534 * 4 shader engines. Set 1 to pass the assertion below.
535 * The other cases are hardware requirements. */
536 if (info->max_se < 4 ||
537 prim == V_008958_DI_PT_POLYGON ||
538 prim == V_008958_DI_PT_LINELOOP ||
539 prim == V_008958_DI_PT_TRIFAN ||
540 prim == V_008958_DI_PT_TRISTRIP_ADJ)
541 // info->primitive_restart ||
542 // info->count_from_stream_output)
543 wd_switch_on_eop = true;
544
545 /* TODO HAWAII */
546
547 /* Required on CIK and later. */
548 if (info->max_se > 2 && !wd_switch_on_eop)
549 ia_switch_on_eoi = true;
550
551 /* Required by Hawaii and, for some special cases, by VI. */
552 #if 0
553 if (ia_switch_on_eoi &&
554 (sctx->b.family == CHIP_HAWAII ||
555 (sctx->b.chip_class == VI &&
556 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
557 partial_vs_wave = true;
558 #endif
559
560 #if 0
561 /* Instancing bug on Bonaire. */
562 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
563 (info->indirect || info->instance_count > 1))
564 partial_vs_wave = true;
565 #endif
566 /* If the WD switch is false, the IA switch must be false too. */
567 assert(wd_switch_on_eop || !ia_switch_on_eop);
568 }
569 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
570 if (ia_switch_on_eoi)
571 partial_es_wave = true;
572
573 /* GS requirement. */
574 #if 0
575 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
576 partial_es_wave = true;
577 #endif
578
579 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
580 * on multi-SE chips. */
581 #if 0
582 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
583 (info->indirect ||
584 (info->instance_count > 1 &&
585 si_num_prims_for_vertices(info) <= 1)))
586 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
587 #endif
588 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
589 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
590 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
591 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
592 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
593 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
594 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
595 max_primgroup_in_wave : 0);
596
597 }
598
599 void
600 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
601 {
602 enum chip_class chip_class = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class;
603 unsigned cp_coher_cntl = 0;
604 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
605
606 if (is_compute)
607 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
608 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
609 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
610 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
611 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
612 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
613 RADV_CMD_FLAG_VGT_FLUSH);
614
615 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
616
617 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_ICACHE)
618 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
619 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
620 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
621 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
622 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
623 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
624 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
625 if (chip_class >= VI)
626 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
627 }
628
629 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
630 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
631 S_0085F0_CB0_DEST_BASE_ENA(1) |
632 S_0085F0_CB1_DEST_BASE_ENA(1) |
633 S_0085F0_CB2_DEST_BASE_ENA(1) |
634 S_0085F0_CB3_DEST_BASE_ENA(1) |
635 S_0085F0_CB4_DEST_BASE_ENA(1) |
636 S_0085F0_CB5_DEST_BASE_ENA(1) |
637 S_0085F0_CB6_DEST_BASE_ENA(1) |
638 S_0085F0_CB7_DEST_BASE_ENA(1);
639
640 /* Necessary for DCC */
641 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= VI) {
642 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
643 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
644 EVENT_INDEX(5));
645 radeon_emit(cmd_buffer->cs, 0);
646 radeon_emit(cmd_buffer->cs, 0);
647 radeon_emit(cmd_buffer->cs, 0);
648 radeon_emit(cmd_buffer->cs, 0);
649 }
650 }
651
652 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
653 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
654 S_0085F0_DB_DEST_BASE_ENA(1);
655 }
656
657 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
658 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
659 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
660 }
661
662 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
663 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
664 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
665 }
666
667 if (!(cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
668 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
669 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
670 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
671 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
672 } else if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
673 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
674 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
675 }
676 }
677
678 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
679 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
680 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
681 }
682
683 /* VGT state sync */
684 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
685 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
686 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
687 }
688
689 /* Make sure ME is idle (it executes most packets) before continuing.
690 * This prevents read-after-write hazards between PFP and ME.
691 */
692 if ((cp_coher_cntl || (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
693 !radv_cmd_buffer_uses_mec(cmd_buffer)) {
694 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
695 radeon_emit(cmd_buffer->cs, 0);
696 }
697
698 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
699 * Therefore, it should be last. Done in PFP.
700 */
701 if (cp_coher_cntl) {
702 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
703 radeon_emit(cmd_buffer->cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
704 PKT3_SHADER_TYPE_S(1));
705 radeon_emit(cmd_buffer->cs, cp_coher_cntl); /* CP_COHER_CNTL */
706 radeon_emit(cmd_buffer->cs, 0xffffffff); /* CP_COHER_SIZE */
707 radeon_emit(cmd_buffer->cs, 0xff); /* CP_COHER_SIZE_HI */
708 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE */
709 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE_HI */
710 radeon_emit(cmd_buffer->cs, 0x0000000A); /* POLL_INTERVAL */
711 } else {
712 /* ACQUIRE_MEM is only required on a compute ring. */
713 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
714 radeon_emit(cmd_buffer->cs, cp_coher_cntl); /* CP_COHER_CNTL */
715 radeon_emit(cmd_buffer->cs, 0xffffffff); /* CP_COHER_SIZE */
716 radeon_emit(cmd_buffer->cs, 0); /* CP_COHER_BASE */
717 radeon_emit(cmd_buffer->cs, 0x0000000A); /* POLL_INTERVAL */
718 }
719 }
720
721 cmd_buffer->state.flush_bits = 0;
722 }
723
724
725 /* Set this if you want the 3D engine to wait until CP DMA is done.
726 * It should be set on the last CP DMA packet. */
727 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
728
729 /* Set this if the source data was used as a destination in a previous CP DMA
730 * packet. It's for preventing a read-after-write (RAW) hazard between two
731 * CP DMA packets. */
732 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
733 #define CIK_CP_DMA_USE_L2 (1 << 2)
734
735 /* Alignment for optimal performance. */
736 #define CP_DMA_ALIGNMENT 32
737 /* The max number of bytes to copy per packet. */
738 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
739
740 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
741 uint64_t dst_va, uint64_t src_va,
742 unsigned size, unsigned flags)
743 {
744 struct radeon_winsys_cs *cs = cmd_buffer->cs;
745 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
746 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
747 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
748 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
749 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
750 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
751
752 assert(size);
753 assert((size & ((1<<21)-1)) == size);
754
755 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
756
757 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
758 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
759 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
760 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
761 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
762 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
763 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
764 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
765 } else {
766 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
767 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
768 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
769 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
770 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
771 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
772 }
773
774 /* CP DMA is executed in ME, but index buffers are read by PFP.
775 * This ensures that ME (CP DMA) is idle before PFP starts fetching
776 * indices. If we wanted to execute CP DMA in PFP, this packet
777 * should precede it.
778 */
779 if (sync_flag) {
780 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
781 radeon_emit(cs, 0);
782 }
783 }
784
785 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
786 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
787 uint64_t dst_va, unsigned size,
788 uint32_t clear_value, unsigned flags)
789 {
790 struct radeon_winsys_cs *cs = cmd_buffer->cs;
791 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
792 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
793 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
794 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
795
796 assert(size);
797 assert((size & ((1<<21)-1)) == size);
798
799 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
800
801 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
802 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
803 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
804 radeon_emit(cs, clear_value); /* DATA [31:0] */
805 radeon_emit(cs, 0);
806 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
807 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
808 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
809 } else {
810 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
811 radeon_emit(cs, clear_value); /* DATA [31:0] */
812 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
813 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
814 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
815 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
816 }
817
818 /* See "copy_buffer" for explanation. */
819 if (sync_flag) {
820 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
821 radeon_emit(cs, 0);
822 }
823 }
824
825 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
826 uint64_t remaining_size, unsigned *flags)
827 {
828
829 /* Flush the caches for the first copy only.
830 * Also wait for the previous CP DMA operations.
831 */
832 if (cmd_buffer->state.flush_bits) {
833 si_emit_cache_flush(cmd_buffer);
834 *flags |= SI_CP_DMA_RAW_WAIT;
835 }
836
837 /* Do the synchronization after the last dma, so that all data
838 * is written to memory.
839 */
840 if (byte_count == remaining_size)
841 *flags |= R600_CP_DMA_SYNC;
842 }
843
844 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
845 {
846 uint64_t va;
847 uint32_t offset;
848 unsigned dma_flags = 0;
849 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
850 void *ptr;
851
852 assert(size < CP_DMA_ALIGNMENT);
853
854 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
855
856 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
857 va += offset;
858
859 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
860
861 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
862 dma_flags);
863 }
864
865 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
866 uint64_t src_va, uint64_t dest_va,
867 uint64_t size)
868 {
869 uint64_t main_src_va, main_dest_va;
870 uint64_t skipped_size = 0, realign_size = 0;
871
872
873 if (cmd_buffer->device->instance->physicalDevice.rad_info.family <= CHIP_CARRIZO ||
874 cmd_buffer->device->instance->physicalDevice.rad_info.family == CHIP_STONEY) {
875 /* If the size is not aligned, we must add a dummy copy at the end
876 * just to align the internal counter. Otherwise, the DMA engine
877 * would slow down by an order of magnitude for following copies.
878 */
879 if (size % CP_DMA_ALIGNMENT)
880 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
881
882 /* If the copy begins unaligned, we must start copying from the next
883 * aligned block and the skipped part should be copied after everything
884 * else has been copied. Only the src alignment matters, not dst.
885 */
886 if (src_va % CP_DMA_ALIGNMENT) {
887 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
888 /* The main part will be skipped if the size is too small. */
889 skipped_size = MIN2(skipped_size, size);
890 size -= skipped_size;
891 }
892 }
893 main_src_va = src_va + skipped_size;
894 main_dest_va = dest_va + skipped_size;
895
896 while (size) {
897 unsigned dma_flags = 0;
898 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
899
900 si_cp_dma_prepare(cmd_buffer, byte_count,
901 size + skipped_size + realign_size,
902 &dma_flags);
903
904 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
905 byte_count, dma_flags);
906
907 size -= byte_count;
908 main_src_va += byte_count;
909 main_dest_va += byte_count;
910 }
911
912 if (skipped_size) {
913 unsigned dma_flags = 0;
914
915 si_cp_dma_prepare(cmd_buffer, skipped_size,
916 size + skipped_size + realign_size,
917 &dma_flags);
918
919 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
920 skipped_size, dma_flags);
921 }
922 if (realign_size)
923 si_cp_dma_realign_engine(cmd_buffer, realign_size);
924 }
925
926 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
927 uint64_t size, unsigned value)
928 {
929
930 if (!size)
931 return;
932
933 assert(va % 4 == 0 && size % 4 == 0);
934
935 while (size) {
936 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
937 unsigned dma_flags = 0;
938
939 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
940
941 /* Emit the clear packet. */
942 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
943 dma_flags);
944
945 size -= byte_count;
946 va += byte_count;
947 }
948 }
949
950 /* For MSAA sample positions. */
951 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
952 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
953 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
954 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
955 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
956
957
958 /* 2xMSAA
959 * There are two locations (4, 4), (-4, -4). */
960 const uint32_t eg_sample_locs_2x[4] = {
961 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
962 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
963 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
964 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
965 };
966 const unsigned eg_max_dist_2x = 4;
967 /* 4xMSAA
968 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
969 const uint32_t eg_sample_locs_4x[4] = {
970 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
971 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
972 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
973 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
974 };
975 const unsigned eg_max_dist_4x = 6;
976
977 /* Cayman 8xMSAA */
978 static const uint32_t cm_sample_locs_8x[] = {
979 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
980 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
981 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
982 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
983 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
984 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
985 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
986 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
987 };
988 static const unsigned cm_max_dist_8x = 8;
989 /* Cayman 16xMSAA */
990 static const uint32_t cm_sample_locs_16x[] = {
991 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
992 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
993 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
994 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
995 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
996 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
997 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
998 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
999 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1000 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1001 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1002 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1003 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1004 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1005 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1006 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1007 };
1008 static const unsigned cm_max_dist_16x = 8;
1009
1010 unsigned radv_cayman_get_maxdist(int log_samples)
1011 {
1012 unsigned max_dist[] = {
1013 0,
1014 eg_max_dist_2x,
1015 eg_max_dist_4x,
1016 cm_max_dist_8x,
1017 cm_max_dist_16x
1018 };
1019 return max_dist[log_samples];
1020 }
1021
1022 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1023 {
1024 switch (nr_samples) {
1025 default:
1026 case 1:
1027 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1028 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1029 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1030 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1031 break;
1032 case 2:
1033 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1034 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1035 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1036 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1037 break;
1038 case 4:
1039 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1040 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1041 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1042 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1043 break;
1044 case 8:
1045 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1046 radeon_emit(cs, cm_sample_locs_8x[0]);
1047 radeon_emit(cs, cm_sample_locs_8x[4]);
1048 radeon_emit(cs, 0);
1049 radeon_emit(cs, 0);
1050 radeon_emit(cs, cm_sample_locs_8x[1]);
1051 radeon_emit(cs, cm_sample_locs_8x[5]);
1052 radeon_emit(cs, 0);
1053 radeon_emit(cs, 0);
1054 radeon_emit(cs, cm_sample_locs_8x[2]);
1055 radeon_emit(cs, cm_sample_locs_8x[6]);
1056 radeon_emit(cs, 0);
1057 radeon_emit(cs, 0);
1058 radeon_emit(cs, cm_sample_locs_8x[3]);
1059 radeon_emit(cs, cm_sample_locs_8x[7]);
1060 break;
1061 case 16:
1062 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1063 radeon_emit(cs, cm_sample_locs_16x[0]);
1064 radeon_emit(cs, cm_sample_locs_16x[4]);
1065 radeon_emit(cs, cm_sample_locs_16x[8]);
1066 radeon_emit(cs, cm_sample_locs_16x[12]);
1067 radeon_emit(cs, cm_sample_locs_16x[1]);
1068 radeon_emit(cs, cm_sample_locs_16x[5]);
1069 radeon_emit(cs, cm_sample_locs_16x[9]);
1070 radeon_emit(cs, cm_sample_locs_16x[13]);
1071 radeon_emit(cs, cm_sample_locs_16x[2]);
1072 radeon_emit(cs, cm_sample_locs_16x[6]);
1073 radeon_emit(cs, cm_sample_locs_16x[10]);
1074 radeon_emit(cs, cm_sample_locs_16x[14]);
1075 radeon_emit(cs, cm_sample_locs_16x[3]);
1076 radeon_emit(cs, cm_sample_locs_16x[7]);
1077 radeon_emit(cs, cm_sample_locs_16x[11]);
1078 radeon_emit(cs, cm_sample_locs_16x[15]);
1079 break;
1080 }
1081 }
1082
1083 static void radv_cayman_get_sample_position(struct radv_device *device,
1084 unsigned sample_count,
1085 unsigned sample_index, float *out_value)
1086 {
1087 int offset, index;
1088 struct {
1089 int idx:4;
1090 } val;
1091 switch (sample_count) {
1092 case 1:
1093 default:
1094 out_value[0] = out_value[1] = 0.5;
1095 break;
1096 case 2:
1097 offset = 4 * (sample_index * 2);
1098 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1099 out_value[0] = (float)(val.idx + 8) / 16.0f;
1100 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1101 out_value[1] = (float)(val.idx + 8) / 16.0f;
1102 break;
1103 case 4:
1104 offset = 4 * (sample_index * 2);
1105 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1106 out_value[0] = (float)(val.idx + 8) / 16.0f;
1107 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1108 out_value[1] = (float)(val.idx + 8) / 16.0f;
1109 break;
1110 case 8:
1111 offset = 4 * (sample_index % 4 * 2);
1112 index = (sample_index / 4) * 4;
1113 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1114 out_value[0] = (float)(val.idx + 8) / 16.0f;
1115 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1116 out_value[1] = (float)(val.idx + 8) / 16.0f;
1117 break;
1118 case 16:
1119 offset = 4 * (sample_index % 4 * 2);
1120 index = (sample_index / 4) * 4;
1121 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1122 out_value[0] = (float)(val.idx + 8) / 16.0f;
1123 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1124 out_value[1] = (float)(val.idx + 8) / 16.0f;
1125 break;
1126 }
1127 }
1128
1129 void radv_device_init_msaa(struct radv_device *device)
1130 {
1131 int i;
1132 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1133
1134 for (i = 0; i < 2; i++)
1135 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1136 for (i = 0; i < 4; i++)
1137 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1138 for (i = 0; i < 8; i++)
1139 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1140 for (i = 0; i < 16; i++)
1141 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1142 }