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radv/gfx10: implement radv_init_dcc_control_reg()
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
106 * and is now per pipe, so it should be handled in the
107 * kernel if we want to use something other than the default value,
108 * which is now 0x22f.
109 */
110 if (physical_device->rad_info.chip_class <= GFX6) {
111 /* XXX: This should be:
112 * (number of compute units) * 4 * (waves per simd) - 1 */
113
114 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
115 0x190 /* Default value */);
116 }
117 }
118
119 /* 12.4 fixed-point */
120 static unsigned radv_pack_float_12p4(float x)
121 {
122 return x <= 0 ? 0 :
123 x >= 4096 ? 0xffff : x * 16;
124 }
125
126 static void
127 si_set_raster_config(struct radv_physical_device *physical_device,
128 struct radeon_cmdbuf *cs)
129 {
130 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
131 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
132 unsigned raster_config, raster_config_1;
133
134 ac_get_raster_config(&physical_device->rad_info,
135 &raster_config,
136 &raster_config_1, NULL);
137
138 /* Always use the default config when all backends are enabled
139 * (or when we failed to determine the enabled backends).
140 */
141 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
142 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
143 raster_config);
144 if (physical_device->rad_info.chip_class >= GFX7)
145 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
146 raster_config_1);
147 } else {
148 si_write_harvested_raster_configs(physical_device, cs,
149 raster_config,
150 raster_config_1);
151 }
152 }
153
154 void
155 si_emit_graphics(struct radv_physical_device *physical_device,
156 struct radeon_cmdbuf *cs)
157 {
158 int i;
159
160 /* Only GFX6 can disable CLEAR_STATE for now. */
161 assert(physical_device->has_clear_state ||
162 physical_device->rad_info.chip_class == GFX6);
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX9) {
241 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
244 } else {
245 /* These registers, when written, also overwrite the
246 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
247 * them. It would be an issue if there was another UMD
248 * changing them.
249 */
250 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
251 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
252 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
253 }
254
255 if (physical_device->rad_info.chip_class >= GFX7) {
256 if (physical_device->rad_info.chip_class >= GFX9) {
257 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
258 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
259 } else {
260 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
261 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
262 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
263 S_00B41C_WAVE_LIMIT(0x3F));
264 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
265 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
266 /* If this is 0, Bonaire can hang even if GS isn't being used.
267 * Other chips are unaffected. These are suboptimal values,
268 * but we don't use on-chip GS.
269 */
270 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
271 S_028A44_ES_VERTS_PER_SUBGRP(64) |
272 S_028A44_GS_PRIMS_PER_SUBGRP(4));
273 }
274 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
275 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
276
277 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
278 /* Too few available compute units per SH. Disallowing
279 * VS to run on CU0 could hurt us more than late VS
280 * allocation would help.
281 *
282 * LATE_ALLOC_VS = 2 is the highest safe number.
283 */
284 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
285 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
286 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
287 } else {
288 /* Set LATE_ALLOC_VS == 31. It should be less than
289 * the number of scratch waves. Limitations:
290 * - VS can't execute on CU0.
291 * - If HS writes outputs to LDS, LS can't execute on CU0.
292 */
293 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
294 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
296 }
297
298 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
299 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
300 }
301
302 if (physical_device->rad_info.chip_class >= GFX8) {
303 uint32_t vgt_tess_distribution;
304
305 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
306 S_028B50_ACCUM_TRI(11) |
307 S_028B50_ACCUM_QUAD(11) |
308 S_028B50_DONUT_SPLIT(16);
309
310 if (physical_device->rad_info.family == CHIP_FIJI ||
311 physical_device->rad_info.family >= CHIP_POLARIS10)
312 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
313
314 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
315 vgt_tess_distribution);
316 } else if (!physical_device->has_clear_state) {
317 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
318 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
319 }
320
321 if (physical_device->rad_info.chip_class >= GFX9) {
322 unsigned num_se = physical_device->rad_info.max_se;
323 unsigned pc_lines = 0;
324 unsigned max_alloc_count = 0;
325
326 switch (physical_device->rad_info.family) {
327 case CHIP_VEGA10:
328 case CHIP_VEGA12:
329 case CHIP_VEGA20:
330 pc_lines = 4096;
331 break;
332 case CHIP_RAVEN:
333 case CHIP_RAVEN2:
334 case CHIP_NAVI10:
335 case CHIP_NAVI12:
336 pc_lines = 1024;
337 break;
338 case CHIP_NAVI14:
339 pc_lines = 512;
340 break;
341 default:
342 assert(0);
343 }
344
345 if (physical_device->rad_info.chip_class >= GFX10) {
346 max_alloc_count = pc_lines / 3;
347 } else {
348 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
349 }
350
351 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
352 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
353 S_028C48_MAX_PRIM_PER_BATCH(1023));
354 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
355 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
356 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
357 }
358
359 unsigned tmp = (unsigned)(1.0 * 8.0);
360 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
361 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
362 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
363 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
364 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
365
366 if (!physical_device->has_clear_state) {
367 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
368 S_028004_ZPASS_INCREMENT_DISABLE(1));
369 }
370
371 /* Enable the Polaris small primitive filter control.
372 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
373 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
374 * and AMDVLK doesn't have a workaround as well.
375 */
376 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
377 unsigned small_prim_filter_cntl =
378 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
379 /* Workaround for a hw line bug. */
380 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
381
382 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
383 small_prim_filter_cntl);
384 }
385
386 si_emit_compute(physical_device, cs);
387 }
388
389 void
390 cik_create_gfx_config(struct radv_device *device)
391 {
392 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
393 if (!cs)
394 return;
395
396 si_emit_graphics(device->physical_device, cs);
397
398 while (cs->cdw & 7) {
399 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
400 radeon_emit(cs, 0x80000000);
401 else
402 radeon_emit(cs, 0xffff1000);
403 }
404
405 device->gfx_init = device->ws->buffer_create(device->ws,
406 cs->cdw * 4, 4096,
407 RADEON_DOMAIN_GTT,
408 RADEON_FLAG_CPU_ACCESS|
409 RADEON_FLAG_NO_INTERPROCESS_SHARING |
410 RADEON_FLAG_READ_ONLY,
411 RADV_BO_PRIORITY_CS);
412 if (!device->gfx_init)
413 goto fail;
414
415 void *map = device->ws->buffer_map(device->gfx_init);
416 if (!map) {
417 device->ws->buffer_destroy(device->gfx_init);
418 device->gfx_init = NULL;
419 goto fail;
420 }
421 memcpy(map, cs->buf, cs->cdw * 4);
422
423 device->ws->buffer_unmap(device->gfx_init);
424 device->gfx_init_size_dw = cs->cdw;
425 fail:
426 device->ws->cs_destroy(cs);
427 }
428
429 static void
430 get_viewport_xform(const VkViewport *viewport,
431 float scale[3], float translate[3])
432 {
433 float x = viewport->x;
434 float y = viewport->y;
435 float half_width = 0.5f * viewport->width;
436 float half_height = 0.5f * viewport->height;
437 double n = viewport->minDepth;
438 double f = viewport->maxDepth;
439
440 scale[0] = half_width;
441 translate[0] = half_width + x;
442 scale[1] = half_height;
443 translate[1] = half_height + y;
444
445 scale[2] = (f - n);
446 translate[2] = n;
447 }
448
449 void
450 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
451 int count, const VkViewport *viewports)
452 {
453 int i;
454
455 assert(count);
456 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
457 first_vp * 4 * 6, count * 6);
458
459 for (i = 0; i < count; i++) {
460 float scale[3], translate[3];
461
462
463 get_viewport_xform(&viewports[i], scale, translate);
464 radeon_emit(cs, fui(scale[0]));
465 radeon_emit(cs, fui(translate[0]));
466 radeon_emit(cs, fui(scale[1]));
467 radeon_emit(cs, fui(translate[1]));
468 radeon_emit(cs, fui(scale[2]));
469 radeon_emit(cs, fui(translate[2]));
470 }
471
472 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
473 first_vp * 4 * 2, count * 2);
474 for (i = 0; i < count; i++) {
475 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
476 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
477 radeon_emit(cs, fui(zmin));
478 radeon_emit(cs, fui(zmax));
479 }
480 }
481
482 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
483 {
484 float scale[3], translate[3];
485 VkRect2D rect;
486
487 get_viewport_xform(viewport, scale, translate);
488
489 rect.offset.x = translate[0] - fabs(scale[0]);
490 rect.offset.y = translate[1] - fabs(scale[1]);
491 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
492 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
493
494 return rect;
495 }
496
497 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
498 VkRect2D ret;
499 ret.offset.x = MAX2(a->offset.x, b->offset.x);
500 ret.offset.y = MAX2(a->offset.y, b->offset.y);
501 ret.extent.width = MIN2(a->offset.x + a->extent.width,
502 b->offset.x + b->extent.width) - ret.offset.x;
503 ret.extent.height = MIN2(a->offset.y + a->extent.height,
504 b->offset.y + b->extent.height) - ret.offset.y;
505 return ret;
506 }
507
508 void
509 si_write_scissors(struct radeon_cmdbuf *cs, int first,
510 int count, const VkRect2D *scissors,
511 const VkViewport *viewports, bool can_use_guardband)
512 {
513 int i;
514 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
515 const float max_range = 32767.0f;
516 if (!count)
517 return;
518
519 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
520 for (i = 0; i < count; i++) {
521 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
522 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
523
524 get_viewport_xform(viewports + i, scale, translate);
525 scale[0] = fabsf(scale[0]);
526 scale[1] = fabsf(scale[1]);
527
528 if (scale[0] < 0.5)
529 scale[0] = 0.5;
530 if (scale[1] < 0.5)
531 scale[1] = 0.5;
532
533 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
534 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
535
536 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
537 S_028250_TL_Y(scissor.offset.y) |
538 S_028250_WINDOW_OFFSET_DISABLE(1));
539 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
540 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
541 }
542 if (!can_use_guardband) {
543 guardband_x = 1.0;
544 guardband_y = 1.0;
545 }
546
547 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
548 radeon_emit(cs, fui(guardband_y));
549 radeon_emit(cs, fui(1.0));
550 radeon_emit(cs, fui(guardband_x));
551 radeon_emit(cs, fui(1.0));
552 }
553
554 static inline unsigned
555 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
556 {
557 if (num == 0)
558 return 0;
559
560 if (info->incr == 0)
561 return 0;
562
563 if (num < info->min)
564 return 0;
565
566 return 1 + ((num - info->min) / info->incr);
567 }
568
569 uint32_t
570 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
571 bool instanced_draw, bool indirect_draw,
572 bool count_from_stream_output,
573 uint32_t draw_vertex_count)
574 {
575 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
576 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
577 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
578 const unsigned max_primgroup_in_wave = 2;
579 /* SWITCH_ON_EOP(0) is always preferable. */
580 bool wd_switch_on_eop = false;
581 bool ia_switch_on_eop = false;
582 bool ia_switch_on_eoi = false;
583 bool partial_vs_wave = false;
584 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
585 bool multi_instances_smaller_than_primgroup;
586
587 multi_instances_smaller_than_primgroup = indirect_draw;
588 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
589 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
590 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
591 multi_instances_smaller_than_primgroup = true;
592 }
593
594 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
595 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
596
597 if (chip_class >= GFX7) {
598 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
599
600 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
601 * We don't know that for indirect drawing, so treat it as
602 * always problematic. */
603 if (family == CHIP_HAWAII &&
604 (instanced_draw || indirect_draw))
605 wd_switch_on_eop = true;
606
607 /* Performance recommendation for 4 SE Gfx7-8 parts if
608 * instances are smaller than a primgroup.
609 * Assume indirect draws always use small instances.
610 * This is needed for good VS wave utilization.
611 */
612 if (chip_class <= GFX8 &&
613 info->max_se == 4 &&
614 multi_instances_smaller_than_primgroup)
615 wd_switch_on_eop = true;
616
617 /* Required on GFX7 and later. */
618 if (info->max_se > 2 && !wd_switch_on_eop)
619 ia_switch_on_eoi = true;
620
621 /* Required by Hawaii and, for some special cases, by GFX8. */
622 if (ia_switch_on_eoi &&
623 (family == CHIP_HAWAII ||
624 (chip_class == GFX8 &&
625 /* max primgroup in wave is always 2 - leave this for documentation */
626 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
627 partial_vs_wave = true;
628
629 /* Instancing bug on Bonaire. */
630 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
631 (instanced_draw || indirect_draw))
632 partial_vs_wave = true;
633
634 /* Hardware requirement when drawing primitives from a stream
635 * output buffer.
636 */
637 if (count_from_stream_output)
638 wd_switch_on_eop = true;
639
640 /* If the WD switch is false, the IA switch must be false too. */
641 assert(wd_switch_on_eop || !ia_switch_on_eop);
642 }
643 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
644 if (chip_class <= GFX8 && ia_switch_on_eoi)
645 partial_es_wave = true;
646
647 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
648 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
649 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
650 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
651 */
652 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
653 bool set_vgt_flush = indirect_draw;
654 if (!set_vgt_flush && instanced_draw) {
655 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
656 if (num_prims <= 1)
657 set_vgt_flush = true;
658 }
659 if (set_vgt_flush)
660 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
661 }
662 }
663
664 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
665 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
666 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
667 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
668 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
669 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
670
671 }
672
673 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
674 enum chip_class chip_class,
675 bool is_mec,
676 unsigned event, unsigned event_flags,
677 unsigned data_sel,
678 uint64_t va,
679 uint32_t new_fence,
680 uint64_t gfx9_eop_bug_va)
681 {
682 unsigned op = EVENT_TYPE(event) |
683 EVENT_INDEX(5) |
684 event_flags;
685 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
686 unsigned sel = EOP_DATA_SEL(data_sel);
687
688 /* Wait for write confirmation before writing data, but don't send
689 * an interrupt. */
690 if (data_sel != EOP_DATA_SEL_DISCARD)
691 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
692
693 if (chip_class >= GFX9 || is_gfx8_mec) {
694 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
695 * counters) must immediately precede every timestamp event to
696 * prevent a GPU hang on GFX9.
697 */
698 if (chip_class == GFX9 && !is_mec) {
699 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
700 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
701 radeon_emit(cs, gfx9_eop_bug_va);
702 radeon_emit(cs, gfx9_eop_bug_va >> 32);
703 }
704
705 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
706 radeon_emit(cs, op);
707 radeon_emit(cs, sel);
708 radeon_emit(cs, va); /* address lo */
709 radeon_emit(cs, va >> 32); /* address hi */
710 radeon_emit(cs, new_fence); /* immediate data lo */
711 radeon_emit(cs, 0); /* immediate data hi */
712 if (!is_gfx8_mec)
713 radeon_emit(cs, 0); /* unused */
714 } else {
715 if (chip_class == GFX7 ||
716 chip_class == GFX8) {
717 /* Two EOP events are required to make all engines go idle
718 * (and optional cache flushes executed) before the timestamp
719 * is written.
720 */
721 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
722 radeon_emit(cs, op);
723 radeon_emit(cs, va);
724 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
725 radeon_emit(cs, 0); /* immediate data */
726 radeon_emit(cs, 0); /* unused */
727 }
728
729 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
730 radeon_emit(cs, op);
731 radeon_emit(cs, va);
732 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
733 radeon_emit(cs, new_fence); /* immediate data */
734 radeon_emit(cs, 0); /* unused */
735 }
736 }
737
738 void
739 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
740 uint32_t ref, uint32_t mask)
741 {
742 assert(op == WAIT_REG_MEM_EQUAL ||
743 op == WAIT_REG_MEM_NOT_EQUAL ||
744 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
745
746 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
747 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
748 radeon_emit(cs, va);
749 radeon_emit(cs, va >> 32);
750 radeon_emit(cs, ref); /* reference value */
751 radeon_emit(cs, mask); /* mask */
752 radeon_emit(cs, 4); /* poll interval */
753 }
754
755 static void
756 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
757 bool is_mec,
758 bool is_gfx9,
759 unsigned cp_coher_cntl)
760 {
761 if (is_mec || is_gfx9) {
762 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
763 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
764 PKT3_SHADER_TYPE_S(is_mec));
765 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
766 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
767 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
768 radeon_emit(cs, 0); /* CP_COHER_BASE */
769 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
770 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
771 } else {
772 /* ACQUIRE_MEM is only required on a compute ring. */
773 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
774 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
775 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
776 radeon_emit(cs, 0); /* CP_COHER_BASE */
777 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
778 }
779 }
780
781 void
782 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
783 enum chip_class chip_class,
784 uint32_t *flush_cnt,
785 uint64_t flush_va,
786 bool is_mec,
787 enum radv_cmd_flush_bits flush_bits,
788 uint64_t gfx9_eop_bug_va)
789 {
790 unsigned cp_coher_cntl = 0;
791 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
792 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
793
794 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
795 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
796 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
797 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
798
799 if (chip_class <= GFX8) {
800 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
801 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
802 S_0085F0_CB0_DEST_BASE_ENA(1) |
803 S_0085F0_CB1_DEST_BASE_ENA(1) |
804 S_0085F0_CB2_DEST_BASE_ENA(1) |
805 S_0085F0_CB3_DEST_BASE_ENA(1) |
806 S_0085F0_CB4_DEST_BASE_ENA(1) |
807 S_0085F0_CB5_DEST_BASE_ENA(1) |
808 S_0085F0_CB6_DEST_BASE_ENA(1) |
809 S_0085F0_CB7_DEST_BASE_ENA(1);
810
811 /* Necessary for DCC */
812 if (chip_class >= GFX8) {
813 si_cs_emit_write_event_eop(cs,
814 chip_class,
815 is_mec,
816 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
817 0,
818 EOP_DATA_SEL_DISCARD,
819 0, 0,
820 gfx9_eop_bug_va);
821 }
822 }
823 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
824 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
825 S_0085F0_DB_DEST_BASE_ENA(1);
826 }
827 }
828
829 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
832 }
833
834 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
835 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
836 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
837 }
838
839 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
841 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
842 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
843 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
844 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
845 }
846
847 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
848 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
850 }
851
852 if (chip_class >= GFX9 && flush_cb_db) {
853 unsigned cb_db_event, tc_flags;
854
855 /* Set the CB/DB flush event. */
856 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
857
858 /* These are the only allowed combinations. If you need to
859 * do multiple operations at once, do them separately.
860 * All operations that invalidate L2 also seem to invalidate
861 * metadata. Volatile (VOL) and WC flushes are not listed here.
862 *
863 * TC | TC_WB = writeback & invalidate L2 & L1
864 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
865 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
866 * TC | TC_NC = invalidate L2 for MTYPE == NC
867 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
868 * TCL1 = invalidate L1
869 */
870 tc_flags = EVENT_TC_ACTION_ENA |
871 EVENT_TC_MD_ACTION_ENA;
872
873 /* Ideally flush TC together with CB/DB. */
874 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
875 /* Writeback and invalidate everything in L2 & L1. */
876 tc_flags = EVENT_TC_ACTION_ENA |
877 EVENT_TC_WB_ACTION_ENA;
878
879
880 /* Clear the flags. */
881 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
882 RADV_CMD_FLAG_WB_L2 |
883 RADV_CMD_FLAG_INV_VCACHE);
884 }
885 assert(flush_cnt);
886 (*flush_cnt)++;
887
888 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
889 EOP_DATA_SEL_VALUE_32BIT,
890 flush_va, *flush_cnt,
891 gfx9_eop_bug_va);
892 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
893 *flush_cnt, 0xffffffff);
894 }
895
896 /* VGT state sync */
897 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
898 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
899 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
900 }
901
902 /* VGT streamout state sync */
903 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
904 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
905 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
906 }
907
908 /* Make sure ME is idle (it executes most packets) before continuing.
909 * This prevents read-after-write hazards between PFP and ME.
910 */
911 if ((cp_coher_cntl ||
912 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
913 RADV_CMD_FLAG_INV_VCACHE |
914 RADV_CMD_FLAG_INV_L2 |
915 RADV_CMD_FLAG_WB_L2))) &&
916 !is_mec) {
917 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
918 radeon_emit(cs, 0);
919 }
920
921 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
922 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
923 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
924 cp_coher_cntl |
925 S_0085F0_TC_ACTION_ENA(1) |
926 S_0085F0_TCL1_ACTION_ENA(1) |
927 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
928 cp_coher_cntl = 0;
929 } else {
930 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
931 /* WB = write-back
932 * NC = apply to non-coherent MTYPEs
933 * (i.e. MTYPE <= 1, which is what we use everywhere)
934 *
935 * WB doesn't work without NC.
936 */
937 si_emit_acquire_mem(cs, is_mec,
938 chip_class >= GFX9,
939 cp_coher_cntl |
940 S_0301F0_TC_WB_ACTION_ENA(1) |
941 S_0301F0_TC_NC_ACTION_ENA(1));
942 cp_coher_cntl = 0;
943 }
944 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
945 si_emit_acquire_mem(cs, is_mec,
946 chip_class >= GFX9,
947 cp_coher_cntl |
948 S_0085F0_TCL1_ACTION_ENA(1));
949 cp_coher_cntl = 0;
950 }
951 }
952
953 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
954 * Therefore, it should be last. Done in PFP.
955 */
956 if (cp_coher_cntl)
957 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
958
959 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
961 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
962 EVENT_INDEX(0));
963 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
964 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
965 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
966 EVENT_INDEX(0));
967 }
968 }
969
970 void
971 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
972 {
973 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
974
975 if (is_compute)
976 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
977 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
978 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
979 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
980 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
981 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
982 RADV_CMD_FLAG_VGT_FLUSH |
983 RADV_CMD_FLAG_START_PIPELINE_STATS |
984 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
985
986 if (!cmd_buffer->state.flush_bits)
987 return;
988
989 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
990
991 si_cs_emit_cache_flush(cmd_buffer->cs,
992 cmd_buffer->device->physical_device->rad_info.chip_class,
993 &cmd_buffer->gfx9_fence_idx,
994 cmd_buffer->gfx9_fence_va,
995 radv_cmd_buffer_uses_mec(cmd_buffer),
996 cmd_buffer->state.flush_bits,
997 cmd_buffer->gfx9_eop_bug_va);
998
999
1000 if (unlikely(cmd_buffer->device->trace_bo))
1001 radv_cmd_buffer_trace_emit(cmd_buffer);
1002
1003 /* Clear the caches that have been flushed to avoid syncing too much
1004 * when there is some pending active queries.
1005 */
1006 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1007
1008 cmd_buffer->state.flush_bits = 0;
1009
1010 /* If the driver used a compute shader for resetting a query pool, it
1011 * should be finished at this point.
1012 */
1013 cmd_buffer->pending_reset_query = false;
1014 }
1015
1016 /* sets the CP predication state using a boolean stored at va */
1017 void
1018 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1019 bool draw_visible, uint64_t va)
1020 {
1021 uint32_t op = 0;
1022
1023 if (va) {
1024 op = PRED_OP(PREDICATION_OP_BOOL64);
1025
1026 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1027 * zero, all rendering commands are discarded. Otherwise, they
1028 * are discarded if the value is non zero.
1029 */
1030 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1031 PREDICATION_DRAW_NOT_VISIBLE;
1032 }
1033 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1034 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1035 radeon_emit(cmd_buffer->cs, op);
1036 radeon_emit(cmd_buffer->cs, va);
1037 radeon_emit(cmd_buffer->cs, va >> 32);
1038 } else {
1039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1040 radeon_emit(cmd_buffer->cs, va);
1041 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1042 }
1043 }
1044
1045 /* Set this if you want the 3D engine to wait until CP DMA is done.
1046 * It should be set on the last CP DMA packet. */
1047 #define CP_DMA_SYNC (1 << 0)
1048
1049 /* Set this if the source data was used as a destination in a previous CP DMA
1050 * packet. It's for preventing a read-after-write (RAW) hazard between two
1051 * CP DMA packets. */
1052 #define CP_DMA_RAW_WAIT (1 << 1)
1053 #define CP_DMA_USE_L2 (1 << 2)
1054 #define CP_DMA_CLEAR (1 << 3)
1055
1056 /* Alignment for optimal performance. */
1057 #define SI_CPDMA_ALIGNMENT 32
1058
1059 /* The max number of bytes that can be copied per packet. */
1060 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1061 {
1062 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1063 S_414_BYTE_COUNT_GFX9(~0u) :
1064 S_414_BYTE_COUNT_GFX6(~0u);
1065
1066 /* make it aligned for optimal performance */
1067 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1068 }
1069
1070 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1071 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1072 * clear value.
1073 */
1074 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1075 uint64_t dst_va, uint64_t src_va,
1076 unsigned size, unsigned flags)
1077 {
1078 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1079 uint32_t header = 0, command = 0;
1080
1081 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1082
1083 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1084 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1085 command |= S_414_BYTE_COUNT_GFX9(size);
1086 else
1087 command |= S_414_BYTE_COUNT_GFX6(size);
1088
1089 /* Sync flags. */
1090 if (flags & CP_DMA_SYNC)
1091 header |= S_411_CP_SYNC(1);
1092 else {
1093 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1094 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1095 else
1096 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1097 }
1098
1099 if (flags & CP_DMA_RAW_WAIT)
1100 command |= S_414_RAW_WAIT(1);
1101
1102 /* Src and dst flags. */
1103 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1104 !(flags & CP_DMA_CLEAR) &&
1105 src_va == dst_va)
1106 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1107 else if (flags & CP_DMA_USE_L2)
1108 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1109
1110 if (flags & CP_DMA_CLEAR)
1111 header |= S_411_SRC_SEL(V_411_DATA);
1112 else if (flags & CP_DMA_USE_L2)
1113 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1114
1115 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1116 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1117 radeon_emit(cs, header);
1118 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1119 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1120 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1121 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1122 radeon_emit(cs, command);
1123 } else {
1124 assert(!(flags & CP_DMA_USE_L2));
1125 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1126 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1127 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1128 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1129 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1130 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1131 radeon_emit(cs, command);
1132 }
1133
1134 /* CP DMA is executed in ME, but index buffers are read by PFP.
1135 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1136 * indices. If we wanted to execute CP DMA in PFP, this packet
1137 * should precede it.
1138 */
1139 if (flags & CP_DMA_SYNC) {
1140 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1141 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1142 radeon_emit(cs, 0);
1143 }
1144
1145 /* CP will see the sync flag and wait for all DMAs to complete. */
1146 cmd_buffer->state.dma_is_busy = false;
1147 }
1148
1149 if (unlikely(cmd_buffer->device->trace_bo))
1150 radv_cmd_buffer_trace_emit(cmd_buffer);
1151 }
1152
1153 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1154 unsigned size)
1155 {
1156 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1157 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1158
1159 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1160 aligned_size, CP_DMA_USE_L2);
1161 }
1162
1163 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1164 uint64_t remaining_size, unsigned *flags)
1165 {
1166
1167 /* Flush the caches for the first copy only.
1168 * Also wait for the previous CP DMA operations.
1169 */
1170 if (cmd_buffer->state.flush_bits) {
1171 si_emit_cache_flush(cmd_buffer);
1172 *flags |= CP_DMA_RAW_WAIT;
1173 }
1174
1175 /* Do the synchronization after the last dma, so that all data
1176 * is written to memory.
1177 */
1178 if (byte_count == remaining_size)
1179 *flags |= CP_DMA_SYNC;
1180 }
1181
1182 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1183 {
1184 uint64_t va;
1185 uint32_t offset;
1186 unsigned dma_flags = 0;
1187 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1188 void *ptr;
1189
1190 assert(size < SI_CPDMA_ALIGNMENT);
1191
1192 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1193
1194 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1195 va += offset;
1196
1197 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1198
1199 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1200 dma_flags);
1201 }
1202
1203 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1204 uint64_t src_va, uint64_t dest_va,
1205 uint64_t size)
1206 {
1207 uint64_t main_src_va, main_dest_va;
1208 uint64_t skipped_size = 0, realign_size = 0;
1209
1210 /* Assume that we are not going to sync after the last DMA operation. */
1211 cmd_buffer->state.dma_is_busy = true;
1212
1213 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1214 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1215 /* If the size is not aligned, we must add a dummy copy at the end
1216 * just to align the internal counter. Otherwise, the DMA engine
1217 * would slow down by an order of magnitude for following copies.
1218 */
1219 if (size % SI_CPDMA_ALIGNMENT)
1220 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1221
1222 /* If the copy begins unaligned, we must start copying from the next
1223 * aligned block and the skipped part should be copied after everything
1224 * else has been copied. Only the src alignment matters, not dst.
1225 */
1226 if (src_va % SI_CPDMA_ALIGNMENT) {
1227 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1228 /* The main part will be skipped if the size is too small. */
1229 skipped_size = MIN2(skipped_size, size);
1230 size -= skipped_size;
1231 }
1232 }
1233 main_src_va = src_va + skipped_size;
1234 main_dest_va = dest_va + skipped_size;
1235
1236 while (size) {
1237 unsigned dma_flags = 0;
1238 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1239
1240 si_cp_dma_prepare(cmd_buffer, byte_count,
1241 size + skipped_size + realign_size,
1242 &dma_flags);
1243
1244 dma_flags &= ~CP_DMA_SYNC;
1245
1246 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1247 byte_count, dma_flags);
1248
1249 size -= byte_count;
1250 main_src_va += byte_count;
1251 main_dest_va += byte_count;
1252 }
1253
1254 if (skipped_size) {
1255 unsigned dma_flags = 0;
1256
1257 si_cp_dma_prepare(cmd_buffer, skipped_size,
1258 size + skipped_size + realign_size,
1259 &dma_flags);
1260
1261 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1262 skipped_size, dma_flags);
1263 }
1264 if (realign_size)
1265 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1266 }
1267
1268 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1269 uint64_t size, unsigned value)
1270 {
1271
1272 if (!size)
1273 return;
1274
1275 assert(va % 4 == 0 && size % 4 == 0);
1276
1277 /* Assume that we are not going to sync after the last DMA operation. */
1278 cmd_buffer->state.dma_is_busy = true;
1279
1280 while (size) {
1281 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1282 unsigned dma_flags = CP_DMA_CLEAR;
1283
1284 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1285
1286 /* Emit the clear packet. */
1287 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1288 dma_flags);
1289
1290 size -= byte_count;
1291 va += byte_count;
1292 }
1293 }
1294
1295 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1296 {
1297 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1298 return;
1299
1300 if (!cmd_buffer->state.dma_is_busy)
1301 return;
1302
1303 /* Issue a dummy DMA that copies zero bytes.
1304 *
1305 * The DMA engine will see that there's no work to do and skip this
1306 * DMA request, however, the CP will see the sync flag and still wait
1307 * for all DMAs to complete.
1308 */
1309 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1310
1311 cmd_buffer->state.dma_is_busy = false;
1312 }
1313
1314 /* For MSAA sample positions. */
1315 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1316 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1317 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1318 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1319 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1320
1321 /* For obtaining location coordinates from registers */
1322 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1323 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1324 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1325 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1326
1327 /* 1x MSAA */
1328 static const uint32_t sample_locs_1x =
1329 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1330 static const unsigned max_dist_1x = 0;
1331 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1332
1333 /* 2xMSAA */
1334 static const uint32_t sample_locs_2x =
1335 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1336 static const unsigned max_dist_2x = 4;
1337 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1338
1339 /* 4xMSAA */
1340 static const uint32_t sample_locs_4x =
1341 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1342 static const unsigned max_dist_4x = 6;
1343 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1344
1345 /* 8xMSAA */
1346 static const uint32_t sample_locs_8x[] = {
1347 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1348 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1349 /* The following are unused by hardware, but we emit them to IBs
1350 * instead of multiple SET_CONTEXT_REG packets. */
1351 0,
1352 0,
1353 };
1354 static const unsigned max_dist_8x = 7;
1355 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1356
1357 unsigned radv_get_default_max_sample_dist(int log_samples)
1358 {
1359 unsigned max_dist[] = {
1360 max_dist_1x,
1361 max_dist_2x,
1362 max_dist_4x,
1363 max_dist_8x,
1364 };
1365 return max_dist[log_samples];
1366 }
1367
1368 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1369 {
1370 switch (nr_samples) {
1371 default:
1372 case 1:
1373 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1374 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1375 radeon_emit(cs, centroid_priority_1x >> 32);
1376 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1377 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1378 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1379 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1380 break;
1381 case 2:
1382 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1383 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1384 radeon_emit(cs, centroid_priority_2x >> 32);
1385 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1386 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1387 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1388 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1389 break;
1390 case 4:
1391 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1392 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1393 radeon_emit(cs, centroid_priority_4x >> 32);
1394 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1395 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1396 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1397 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1398 break;
1399 case 8:
1400 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1401 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1402 radeon_emit(cs, centroid_priority_8x >> 32);
1403 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1404 radeon_emit_array(cs, sample_locs_8x, 4);
1405 radeon_emit_array(cs, sample_locs_8x, 4);
1406 radeon_emit_array(cs, sample_locs_8x, 4);
1407 radeon_emit_array(cs, sample_locs_8x, 2);
1408 break;
1409 }
1410 }
1411
1412 static void radv_get_sample_position(struct radv_device *device,
1413 unsigned sample_count,
1414 unsigned sample_index, float *out_value)
1415 {
1416 const uint32_t *sample_locs;
1417
1418 switch (sample_count) {
1419 case 1:
1420 default:
1421 sample_locs = &sample_locs_1x;
1422 break;
1423 case 2:
1424 sample_locs = &sample_locs_2x;
1425 break;
1426 case 4:
1427 sample_locs = &sample_locs_4x;
1428 break;
1429 case 8:
1430 sample_locs = sample_locs_8x;
1431 break;
1432 }
1433
1434 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1435 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1436 }
1437
1438 void radv_device_init_msaa(struct radv_device *device)
1439 {
1440 int i;
1441
1442 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1443
1444 for (i = 0; i < 2; i++)
1445 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1446 for (i = 0; i < 4; i++)
1447 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1448 for (i = 0; i < 8; i++)
1449 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1450 }