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[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 /* 12.4 fixed-point */
220 static unsigned radv_pack_float_12p4(float x)
221 {
222 return x <= 0 ? 0 :
223 x >= 4096 ? 0xffff : x * 16;
224 }
225
226 static void
227 si_set_raster_config(struct radv_physical_device *physical_device,
228 struct radeon_winsys_cs *cs)
229 {
230 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
231 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
232 unsigned raster_config, raster_config_1;
233
234 switch (physical_device->rad_info.family) {
235 case CHIP_TAHITI:
236 case CHIP_PITCAIRN:
237 raster_config = 0x2a00126a;
238 raster_config_1 = 0x00000000;
239 break;
240 case CHIP_VERDE:
241 raster_config = 0x0000124a;
242 raster_config_1 = 0x00000000;
243 break;
244 case CHIP_OLAND:
245 raster_config = 0x00000082;
246 raster_config_1 = 0x00000000;
247 break;
248 case CHIP_HAINAN:
249 raster_config = 0x00000000;
250 raster_config_1 = 0x00000000;
251 break;
252 case CHIP_BONAIRE:
253 raster_config = 0x16000012;
254 raster_config_1 = 0x00000000;
255 break;
256 case CHIP_HAWAII:
257 raster_config = 0x3a00161a;
258 raster_config_1 = 0x0000002e;
259 break;
260 case CHIP_FIJI:
261 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
262 /* old kernels with old tiling config */
263 raster_config = 0x16000012;
264 raster_config_1 = 0x0000002a;
265 } else {
266 raster_config = 0x3a00161a;
267 raster_config_1 = 0x0000002e;
268 }
269 break;
270 case CHIP_POLARIS10:
271 raster_config = 0x16000012;
272 raster_config_1 = 0x0000002a;
273 break;
274 case CHIP_POLARIS11:
275 case CHIP_POLARIS12:
276 raster_config = 0x16000012;
277 raster_config_1 = 0x00000000;
278 break;
279 case CHIP_TONGA:
280 raster_config = 0x16000012;
281 raster_config_1 = 0x0000002a;
282 break;
283 case CHIP_ICELAND:
284 if (num_rb == 1)
285 raster_config = 0x00000000;
286 else
287 raster_config = 0x00000002;
288 raster_config_1 = 0x00000000;
289 break;
290 case CHIP_CARRIZO:
291 raster_config = 0x00000002;
292 raster_config_1 = 0x00000000;
293 break;
294 case CHIP_KAVERI:
295 /* KV should be 0x00000002, but that causes problems with radeon */
296 raster_config = 0x00000000; /* 0x00000002 */
297 raster_config_1 = 0x00000000;
298 break;
299 case CHIP_KABINI:
300 case CHIP_MULLINS:
301 case CHIP_STONEY:
302 raster_config = 0x00000000;
303 raster_config_1 = 0x00000000;
304 break;
305 default:
306 fprintf(stderr,
307 "radv: Unknown GPU, using 0 for raster_config\n");
308 raster_config = 0x00000000;
309 raster_config_1 = 0x00000000;
310 break;
311 }
312
313 /* Always use the default config when all backends are enabled
314 * (or when we failed to determine the enabled backends).
315 */
316 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
317 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
318 raster_config);
319 if (physical_device->rad_info.chip_class >= CIK)
320 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
321 raster_config_1);
322 } else {
323 si_write_harvested_raster_configs(physical_device, cs,
324 raster_config,
325 raster_config_1);
326 }
327 }
328
329 static void
330 si_emit_config(struct radv_physical_device *physical_device,
331 struct radeon_winsys_cs *cs)
332 {
333 int i;
334
335 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
336 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
337 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
338
339 if (physical_device->rad_info.chip_class <= VI)
340 si_set_raster_config(physical_device, cs);
341
342 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
343 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
344
345 /* FIXME calculate these values somehow ??? */
346 if (physical_device->rad_info.chip_class <= VI) {
347 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
348 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
349 }
350
351 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
352
353 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
354 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
355
356 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
357 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
358 if (physical_device->rad_info.chip_class >= GFX9)
359 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 0);
360 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
361 if (physical_device->rad_info.chip_class < CIK)
362 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
363 S_008A14_CLIP_VTX_REORDER_ENA(1));
364
365 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
366 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
367
368 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
369
370 for (i = 0; i < 16; i++) {
371 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
372 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
373 }
374
375 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
376 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
377 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
378 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
379 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
380 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
381 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
382
383 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
384 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
385 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
386 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
387 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
388
389 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
390 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
391 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
392 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
393 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
394 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
395
396 if (physical_device->rad_info.chip_class >= GFX9) {
397 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
398 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
399 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
400 } else {
401 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
402 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
403 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
404 }
405
406 if (physical_device->rad_info.chip_class >= CIK) {
407 if (physical_device->rad_info.chip_class >= GFX9) {
408 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
409 } else {
410 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
411 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
412 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
413 /* If this is 0, Bonaire can hang even if GS isn't being used.
414 * Other chips are unaffected. These are suboptimal values,
415 * but we don't use on-chip GS.
416 */
417 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
418 S_028A44_ES_VERTS_PER_SUBGRP(64) |
419 S_028A44_GS_PRIMS_PER_SUBGRP(4));
420 }
421 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
422
423 if (physical_device->rad_info.num_good_compute_units /
424 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
425 /* Too few available compute units per SH. Disallowing
426 * VS to run on CU0 could hurt us more than late VS
427 * allocation would help.
428 *
429 * LATE_ALLOC_VS = 2 is the highest safe number.
430 */
431 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
432 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
433 } else {
434 /* Set LATE_ALLOC_VS == 31. It should be less than
435 * the number of scratch waves. Limitations:
436 * - VS can't execute on CU0.
437 * - If HS writes outputs to LDS, LS can't execute on CU0.
438 */
439 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
440 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
441 }
442
443 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
444 }
445
446 if (physical_device->rad_info.chip_class >= VI) {
447 uint32_t vgt_tess_distribution;
448 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
449 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
450 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
451 if (physical_device->rad_info.family < CHIP_POLARIS10)
452 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
453 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
454
455 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
456 S_028B50_ACCUM_TRI(11) |
457 S_028B50_ACCUM_QUAD(11) |
458 S_028B50_DONUT_SPLIT(16);
459
460 if (physical_device->rad_info.family == CHIP_FIJI ||
461 physical_device->rad_info.family >= CHIP_POLARIS10)
462 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
463
464 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
465 vgt_tess_distribution);
466 } else {
467 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
468 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
469 }
470
471 if (physical_device->has_rbplus)
472 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
473
474 if (physical_device->rad_info.chip_class >= GFX9) {
475 unsigned num_se = physical_device->rad_info.max_se;
476 unsigned pc_lines = 0;
477
478 switch (physical_device->rad_info.family) {
479 case CHIP_VEGA10:
480 pc_lines = 4096;
481 break;
482 case CHIP_RAVEN:
483 pc_lines = 1024;
484 break;
485 default:
486 assert(0);
487 }
488
489 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
490 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
491 radeon_set_context_reg(cs, R_028064_DB_RENDER_FILTER, 0);
492 /* TODO: We can use this to disable RBs for rendering to GART: */
493 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
494 radeon_set_context_reg(cs, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
495 /* TODO: Enable the binner: */
496 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
497 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
498 S_028C44_DISABLE_START_OF_PRIM(1));
499 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
500 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
501 S_028C48_MAX_PRIM_PER_BATCH(1023));
502 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
503 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
504 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
505 }
506
507 unsigned tmp = (unsigned)(1.0 * 8.0);
508 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
509 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
510 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
511 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
512 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
513
514 si_emit_compute(physical_device, cs);
515 }
516
517 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
518 {
519 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
520
521 si_emit_config(physical_device, cmd_buffer->cs);
522 }
523
524 void
525 cik_create_gfx_config(struct radv_device *device)
526 {
527 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
528 if (!cs)
529 return;
530
531 si_emit_config(device->physical_device, cs);
532
533 while (cs->cdw & 7) {
534 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
535 radeon_emit(cs, 0x80000000);
536 else
537 radeon_emit(cs, 0xffff1000);
538 }
539
540 device->gfx_init = device->ws->buffer_create(device->ws,
541 cs->cdw * 4, 4096,
542 RADEON_DOMAIN_GTT,
543 RADEON_FLAG_CPU_ACCESS);
544 if (!device->gfx_init)
545 goto fail;
546
547 void *map = device->ws->buffer_map(device->gfx_init);
548 if (!map) {
549 device->ws->buffer_destroy(device->gfx_init);
550 device->gfx_init = NULL;
551 goto fail;
552 }
553 memcpy(map, cs->buf, cs->cdw * 4);
554
555 device->ws->buffer_unmap(device->gfx_init);
556 device->gfx_init_size_dw = cs->cdw;
557 fail:
558 device->ws->cs_destroy(cs);
559 }
560
561 static void
562 get_viewport_xform(const VkViewport *viewport,
563 float scale[3], float translate[3])
564 {
565 float x = viewport->x;
566 float y = viewport->y;
567 float half_width = 0.5f * viewport->width;
568 float half_height = 0.5f * viewport->height;
569 double n = viewport->minDepth;
570 double f = viewport->maxDepth;
571
572 scale[0] = half_width;
573 translate[0] = half_width + x;
574 scale[1] = half_height;
575 translate[1] = half_height + y;
576
577 scale[2] = (f - n);
578 translate[2] = n;
579 }
580
581 void
582 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
583 int count, const VkViewport *viewports)
584 {
585 int i;
586
587 assert(count);
588 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
589 first_vp * 4 * 6, count * 6);
590
591 for (i = 0; i < count; i++) {
592 float scale[3], translate[3];
593
594
595 get_viewport_xform(&viewports[i], scale, translate);
596 radeon_emit(cs, fui(scale[0]));
597 radeon_emit(cs, fui(translate[0]));
598 radeon_emit(cs, fui(scale[1]));
599 radeon_emit(cs, fui(translate[1]));
600 radeon_emit(cs, fui(scale[2]));
601 radeon_emit(cs, fui(translate[2]));
602 }
603
604 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
605 first_vp * 4 * 2, count * 2);
606 for (i = 0; i < count; i++) {
607 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
608 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
609 radeon_emit(cs, fui(zmin));
610 radeon_emit(cs, fui(zmax));
611 }
612 }
613
614 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
615 {
616 float scale[3], translate[3];
617 VkRect2D rect;
618
619 get_viewport_xform(viewport, scale, translate);
620
621 rect.offset.x = translate[0] - abs(scale[0]);
622 rect.offset.y = translate[1] - abs(scale[1]);
623 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
624 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
625
626 return rect;
627 }
628
629 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
630 VkRect2D ret;
631 ret.offset.x = MAX2(a->offset.x, b->offset.x);
632 ret.offset.y = MAX2(a->offset.y, b->offset.y);
633 ret.extent.width = MIN2(a->offset.x + a->extent.width,
634 b->offset.x + b->extent.width) - ret.offset.x;
635 ret.extent.height = MIN2(a->offset.y + a->extent.height,
636 b->offset.y + b->extent.height) - ret.offset.y;
637 return ret;
638 }
639
640 void
641 si_write_scissors(struct radeon_winsys_cs *cs, int first,
642 int count, const VkRect2D *scissors,
643 const VkViewport *viewports, bool can_use_guardband)
644 {
645 int i;
646 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
647 const float max_range = 32767.0f;
648 assert(count);
649
650 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
651 for (i = 0; i < count; i++) {
652 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
653 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
654
655 get_viewport_xform(viewports + i, scale, translate);
656 scale[0] = abs(scale[0]);
657 scale[1] = abs(scale[1]);
658
659 if (scale[0] < 0.5)
660 scale[0] = 0.5;
661 if (scale[1] < 0.5)
662 scale[1] = 0.5;
663
664 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
665 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
666
667 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
668 S_028250_TL_Y(scissor.offset.y) |
669 S_028250_WINDOW_OFFSET_DISABLE(1));
670 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
671 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
672 }
673 if (!can_use_guardband) {
674 guardband_x = 1.0;
675 guardband_y = 1.0;
676 }
677
678 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
679 radeon_emit(cs, fui(guardband_y));
680 radeon_emit(cs, fui(1.0));
681 radeon_emit(cs, fui(guardband_x));
682 radeon_emit(cs, fui(1.0));
683 }
684
685 static inline unsigned
686 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
687 {
688 if (num == 0)
689 return 0;
690
691 if (info->incr == 0)
692 return 0;
693
694 if (num < info->min)
695 return 0;
696
697 return 1 + ((num - info->min) / info->incr);
698 }
699
700 uint32_t
701 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
702 bool instanced_draw, bool indirect_draw,
703 uint32_t draw_vertex_count)
704 {
705 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
706 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
707 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
708 const unsigned max_primgroup_in_wave = 2;
709 /* SWITCH_ON_EOP(0) is always preferable. */
710 bool wd_switch_on_eop = false;
711 bool ia_switch_on_eop = false;
712 bool ia_switch_on_eoi = false;
713 bool partial_vs_wave = false;
714 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave;
715 bool multi_instances_smaller_than_primgroup;
716
717 multi_instances_smaller_than_primgroup = indirect_draw;
718 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
719 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
720 if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
721 multi_instances_smaller_than_primgroup = true;
722 }
723
724 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi;
725 partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave;
726
727 if (chip_class >= CIK) {
728 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop;
729
730 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
731 * We don't know that for indirect drawing, so treat it as
732 * always problematic. */
733 if (family == CHIP_HAWAII &&
734 (instanced_draw || indirect_draw))
735 wd_switch_on_eop = true;
736
737 /* Performance recommendation for 4 SE Gfx7-8 parts if
738 * instances are smaller than a primgroup.
739 * Assume indirect draws always use small instances.
740 * This is needed for good VS wave utilization.
741 */
742 if (chip_class <= VI &&
743 info->max_se == 4 &&
744 multi_instances_smaller_than_primgroup)
745 wd_switch_on_eop = true;
746
747 /* Required on CIK and later. */
748 if (info->max_se > 2 && !wd_switch_on_eop)
749 ia_switch_on_eoi = true;
750
751 /* Required by Hawaii and, for some special cases, by VI. */
752 if (ia_switch_on_eoi &&
753 (family == CHIP_HAWAII ||
754 (chip_class == VI &&
755 /* max primgroup in wave is always 2 - leave this for documentation */
756 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
757 partial_vs_wave = true;
758
759 /* Instancing bug on Bonaire. */
760 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
761 (instanced_draw || indirect_draw))
762 partial_vs_wave = true;
763
764 /* If the WD switch is false, the IA switch must be false too. */
765 assert(wd_switch_on_eop || !ia_switch_on_eop);
766 }
767 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
768 if (chip_class <= VI && ia_switch_on_eoi)
769 partial_es_wave = true;
770
771 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
772 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
773 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
774 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
775 */
776 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
777 bool set_vgt_flush = indirect_draw;
778 if (!set_vgt_flush && instanced_draw) {
779 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
780 if (num_prims <= 1)
781 set_vgt_flush = true;
782 }
783 if (set_vgt_flush)
784 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
785 }
786 }
787
788 return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
789 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
790 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
791 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
792 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
793 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
794
795 }
796
797 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
798 bool predicated,
799 enum chip_class chip_class,
800 bool is_mec,
801 unsigned event, unsigned event_flags,
802 unsigned data_sel,
803 uint64_t va,
804 uint32_t old_fence,
805 uint32_t new_fence)
806 {
807 unsigned op = EVENT_TYPE(event) |
808 EVENT_INDEX(5) |
809 event_flags;
810 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
811
812 if (chip_class >= GFX9 || is_gfx8_mec) {
813 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
814 radeon_emit(cs, op);
815 radeon_emit(cs, EOP_DATA_SEL(data_sel));
816 radeon_emit(cs, va); /* address lo */
817 radeon_emit(cs, va >> 32); /* address hi */
818 radeon_emit(cs, new_fence); /* immediate data lo */
819 radeon_emit(cs, 0); /* immediate data hi */
820 if (!is_gfx8_mec)
821 radeon_emit(cs, 0); /* unused */
822 } else {
823 if (chip_class == CIK ||
824 chip_class == VI) {
825 /* Two EOP events are required to make all engines go idle
826 * (and optional cache flushes executed) before the timestamp
827 * is written.
828 */
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
830 radeon_emit(cs, op);
831 radeon_emit(cs, va);
832 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
833 radeon_emit(cs, old_fence); /* immediate data */
834 radeon_emit(cs, 0); /* unused */
835 }
836
837 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
838 radeon_emit(cs, op);
839 radeon_emit(cs, va);
840 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
841 radeon_emit(cs, new_fence); /* immediate data */
842 radeon_emit(cs, 0); /* unused */
843 }
844 }
845
846 void
847 si_emit_wait_fence(struct radeon_winsys_cs *cs,
848 bool predicated,
849 uint64_t va, uint32_t ref,
850 uint32_t mask)
851 {
852 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
853 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
854 radeon_emit(cs, va);
855 radeon_emit(cs, va >> 32);
856 radeon_emit(cs, ref); /* reference value */
857 radeon_emit(cs, mask); /* mask */
858 radeon_emit(cs, 4); /* poll interval */
859 }
860
861 static void
862 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
863 bool is_mec,
864 bool predicated,
865 bool is_gfx9,
866 unsigned cp_coher_cntl)
867 {
868 if (is_mec || is_gfx9) {
869 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
870 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
871 PKT3_SHADER_TYPE_S(is_mec));
872 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
873 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
874 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
875 radeon_emit(cs, 0); /* CP_COHER_BASE */
876 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
877 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
878 } else {
879 /* ACQUIRE_MEM is only required on a compute ring. */
880 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
881 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
882 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
883 radeon_emit(cs, 0); /* CP_COHER_BASE */
884 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
885 }
886 }
887
888 void
889 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
890 bool predicated,
891 enum chip_class chip_class,
892 uint32_t *flush_cnt,
893 uint64_t flush_va,
894 bool is_mec,
895 enum radv_cmd_flush_bits flush_bits)
896 {
897 unsigned cp_coher_cntl = 0;
898 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
899 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
900
901 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
902 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
903 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
904 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
905
906 if (chip_class <= VI) {
907 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
908 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
909 S_0085F0_CB0_DEST_BASE_ENA(1) |
910 S_0085F0_CB1_DEST_BASE_ENA(1) |
911 S_0085F0_CB2_DEST_BASE_ENA(1) |
912 S_0085F0_CB3_DEST_BASE_ENA(1) |
913 S_0085F0_CB4_DEST_BASE_ENA(1) |
914 S_0085F0_CB5_DEST_BASE_ENA(1) |
915 S_0085F0_CB6_DEST_BASE_ENA(1) |
916 S_0085F0_CB7_DEST_BASE_ENA(1);
917
918 /* Necessary for DCC */
919 if (chip_class >= VI) {
920 si_cs_emit_write_event_eop(cs,
921 predicated,
922 chip_class,
923 is_mec,
924 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
925 0, 0, 0, 0, 0);
926 }
927 }
928 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
929 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
930 S_0085F0_DB_DEST_BASE_ENA(1);
931 }
932 }
933
934 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
935 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
936 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
937 }
938
939 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
940 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
941 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
942 }
943
944 if (!flush_cb_db) {
945 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
948 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
950 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
951 }
952 }
953
954 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
955 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
956 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
957 }
958
959 if (chip_class >= GFX9 && flush_cb_db) {
960 unsigned cb_db_event, tc_flags;
961
962 /* Set the CB/DB flush event. */
963 switch (flush_cb_db) {
964 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
965 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
966 break;
967 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
968 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
969 break;
970 default:
971 /* both CB & DB */
972 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
973 }
974
975 /* TC | TC_WB = invalidate L2 data
976 * TC_MD | TC_WB = invalidate L2 metadata
977 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
978 *
979 * The metadata cache must always be invalidated for coherency
980 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
981 *
982 * TC must be invalidated on GFX9 only if the CB/DB surface is
983 * not pipe-aligned. If the surface is RB-aligned, it might not
984 * strictly be pipe-aligned since RB alignment takes precendence.
985 */
986 tc_flags = EVENT_TC_WB_ACTION_ENA |
987 EVENT_TC_MD_ACTION_ENA;
988
989 /* Ideally flush TC together with CB/DB. */
990 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
991 tc_flags |= EVENT_TC_ACTION_ENA |
992 EVENT_TCL1_ACTION_ENA;
993
994 /* Clear the flags. */
995 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
996 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
997 RADV_CMD_FLAG_INV_VMEM_L1);
998 }
999 assert(flush_cnt);
1000 uint32_t old_fence = (*flush_cnt)++;
1001
1002 si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
1003 flush_va, old_fence, *flush_cnt);
1004 si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
1005 }
1006
1007 /* VGT state sync */
1008 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1009 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
1010 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1011 }
1012
1013 /* Make sure ME is idle (it executes most packets) before continuing.
1014 * This prevents read-after-write hazards between PFP and ME.
1015 */
1016 if ((cp_coher_cntl ||
1017 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1018 RADV_CMD_FLAG_INV_VMEM_L1 |
1019 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1020 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1021 !is_mec) {
1022 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
1023 radeon_emit(cs, 0);
1024 }
1025
1026 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1027 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1028 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
1029 cp_coher_cntl |
1030 S_0085F0_TC_ACTION_ENA(1) |
1031 S_0085F0_TCL1_ACTION_ENA(1) |
1032 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1033 cp_coher_cntl = 0;
1034 } else {
1035 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1036 /* WB = write-back
1037 * NC = apply to non-coherent MTYPEs
1038 * (i.e. MTYPE <= 1, which is what we use everywhere)
1039 *
1040 * WB doesn't work without NC.
1041 */
1042 si_emit_acquire_mem(cs, is_mec, predicated,
1043 chip_class >= GFX9,
1044 cp_coher_cntl |
1045 S_0301F0_TC_WB_ACTION_ENA(1) |
1046 S_0301F0_TC_NC_ACTION_ENA(1));
1047 cp_coher_cntl = 0;
1048 }
1049 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1050 si_emit_acquire_mem(cs, is_mec,
1051 predicated, chip_class >= GFX9,
1052 cp_coher_cntl |
1053 S_0085F0_TCL1_ACTION_ENA(1));
1054 cp_coher_cntl = 0;
1055 }
1056 }
1057
1058 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1059 * Therefore, it should be last. Done in PFP.
1060 */
1061 if (cp_coher_cntl)
1062 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
1063 }
1064
1065 void
1066 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1067 {
1068 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1069
1070 if (is_compute)
1071 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1072 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1073 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1074 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1075 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1076 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1077 RADV_CMD_FLAG_VGT_FLUSH);
1078
1079 if (!cmd_buffer->state.flush_bits)
1080 return;
1081
1082 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1083 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1084
1085 uint32_t *ptr = NULL;
1086 uint64_t va = 0;
1087 if (chip_class == GFX9) {
1088 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1089 ptr = &cmd_buffer->gfx9_fence_idx;
1090 }
1091 si_cs_emit_cache_flush(cmd_buffer->cs,
1092 cmd_buffer->state.predicating,
1093 cmd_buffer->device->physical_device->rad_info.chip_class,
1094 ptr, va,
1095 radv_cmd_buffer_uses_mec(cmd_buffer),
1096 cmd_buffer->state.flush_bits);
1097
1098
1099 radv_cmd_buffer_trace_emit(cmd_buffer);
1100 cmd_buffer->state.flush_bits = 0;
1101 }
1102
1103 /* sets the CP predication state using a boolean stored at va */
1104 void
1105 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1106 {
1107 uint32_t op = 0;
1108
1109 if (va)
1110 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1111 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1112 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1113 radeon_emit(cmd_buffer->cs, op);
1114 radeon_emit(cmd_buffer->cs, va);
1115 radeon_emit(cmd_buffer->cs, va >> 32);
1116 } else {
1117 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1118 radeon_emit(cmd_buffer->cs, va);
1119 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1120 }
1121 }
1122
1123 /* Set this if you want the 3D engine to wait until CP DMA is done.
1124 * It should be set on the last CP DMA packet. */
1125 #define CP_DMA_SYNC (1 << 0)
1126
1127 /* Set this if the source data was used as a destination in a previous CP DMA
1128 * packet. It's for preventing a read-after-write (RAW) hazard between two
1129 * CP DMA packets. */
1130 #define CP_DMA_RAW_WAIT (1 << 1)
1131 #define CP_DMA_USE_L2 (1 << 2)
1132 #define CP_DMA_CLEAR (1 << 3)
1133
1134 /* Alignment for optimal performance. */
1135 #define SI_CPDMA_ALIGNMENT 32
1136
1137 /* The max number of bytes that can be copied per packet. */
1138 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1139 {
1140 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1141 S_414_BYTE_COUNT_GFX9(~0u) :
1142 S_414_BYTE_COUNT_GFX6(~0u);
1143
1144 /* make it aligned for optimal performance */
1145 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1146 }
1147
1148 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1149 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1150 * clear value.
1151 */
1152 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1153 uint64_t dst_va, uint64_t src_va,
1154 unsigned size, unsigned flags)
1155 {
1156 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1157 uint32_t header = 0, command = 0;
1158
1159 assert(size);
1160 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1161
1162 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1163 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1164 command |= S_414_BYTE_COUNT_GFX9(size);
1165 else
1166 command |= S_414_BYTE_COUNT_GFX6(size);
1167
1168 /* Sync flags. */
1169 if (flags & CP_DMA_SYNC)
1170 header |= S_411_CP_SYNC(1);
1171 else {
1172 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1173 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1174 else
1175 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1176 }
1177
1178 if (flags & CP_DMA_RAW_WAIT)
1179 command |= S_414_RAW_WAIT(1);
1180
1181 /* Src and dst flags. */
1182 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1183 !(flags & CP_DMA_CLEAR) &&
1184 src_va == dst_va)
1185 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1186 else if (flags & CP_DMA_USE_L2)
1187 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1188
1189 if (flags & CP_DMA_CLEAR)
1190 header |= S_411_SRC_SEL(V_411_DATA);
1191 else if (flags & CP_DMA_USE_L2)
1192 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1193
1194 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1195 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1196 radeon_emit(cs, header);
1197 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1198 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1199 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1200 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1201 radeon_emit(cs, command);
1202 } else {
1203 assert(!(flags & CP_DMA_USE_L2));
1204 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1205 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1206 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1207 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1208 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1209 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1210 radeon_emit(cs, command);
1211 }
1212
1213 /* CP DMA is executed in ME, but index buffers are read by PFP.
1214 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1215 * indices. If we wanted to execute CP DMA in PFP, this packet
1216 * should precede it.
1217 */
1218 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1219 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1220 radeon_emit(cs, 0);
1221 }
1222
1223 radv_cmd_buffer_trace_emit(cmd_buffer);
1224 }
1225
1226 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1227 unsigned size)
1228 {
1229 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1230 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1231
1232 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1233 aligned_size, CP_DMA_USE_L2);
1234 }
1235
1236 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1237 uint64_t remaining_size, unsigned *flags)
1238 {
1239
1240 /* Flush the caches for the first copy only.
1241 * Also wait for the previous CP DMA operations.
1242 */
1243 if (cmd_buffer->state.flush_bits) {
1244 si_emit_cache_flush(cmd_buffer);
1245 *flags |= CP_DMA_RAW_WAIT;
1246 }
1247
1248 /* Do the synchronization after the last dma, so that all data
1249 * is written to memory.
1250 */
1251 if (byte_count == remaining_size)
1252 *flags |= CP_DMA_SYNC;
1253 }
1254
1255 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1256 {
1257 uint64_t va;
1258 uint32_t offset;
1259 unsigned dma_flags = 0;
1260 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1261 void *ptr;
1262
1263 assert(size < SI_CPDMA_ALIGNMENT);
1264
1265 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1266
1267 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1268 va += offset;
1269
1270 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1271
1272 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1273 dma_flags);
1274 }
1275
1276 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1277 uint64_t src_va, uint64_t dest_va,
1278 uint64_t size)
1279 {
1280 uint64_t main_src_va, main_dest_va;
1281 uint64_t skipped_size = 0, realign_size = 0;
1282
1283
1284 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1285 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1286 /* If the size is not aligned, we must add a dummy copy at the end
1287 * just to align the internal counter. Otherwise, the DMA engine
1288 * would slow down by an order of magnitude for following copies.
1289 */
1290 if (size % SI_CPDMA_ALIGNMENT)
1291 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1292
1293 /* If the copy begins unaligned, we must start copying from the next
1294 * aligned block and the skipped part should be copied after everything
1295 * else has been copied. Only the src alignment matters, not dst.
1296 */
1297 if (src_va % SI_CPDMA_ALIGNMENT) {
1298 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1299 /* The main part will be skipped if the size is too small. */
1300 skipped_size = MIN2(skipped_size, size);
1301 size -= skipped_size;
1302 }
1303 }
1304 main_src_va = src_va + skipped_size;
1305 main_dest_va = dest_va + skipped_size;
1306
1307 while (size) {
1308 unsigned dma_flags = 0;
1309 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1310
1311 si_cp_dma_prepare(cmd_buffer, byte_count,
1312 size + skipped_size + realign_size,
1313 &dma_flags);
1314
1315 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1316 byte_count, dma_flags);
1317
1318 size -= byte_count;
1319 main_src_va += byte_count;
1320 main_dest_va += byte_count;
1321 }
1322
1323 if (skipped_size) {
1324 unsigned dma_flags = 0;
1325
1326 si_cp_dma_prepare(cmd_buffer, skipped_size,
1327 size + skipped_size + realign_size,
1328 &dma_flags);
1329
1330 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1331 skipped_size, dma_flags);
1332 }
1333 if (realign_size)
1334 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1335 }
1336
1337 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1338 uint64_t size, unsigned value)
1339 {
1340
1341 if (!size)
1342 return;
1343
1344 assert(va % 4 == 0 && size % 4 == 0);
1345
1346 while (size) {
1347 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1348 unsigned dma_flags = CP_DMA_CLEAR;
1349
1350 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1351
1352 /* Emit the clear packet. */
1353 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1354 dma_flags);
1355
1356 size -= byte_count;
1357 va += byte_count;
1358 }
1359 }
1360
1361 /* For MSAA sample positions. */
1362 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1363 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1364 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1365 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1366 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1367
1368
1369 /* 2xMSAA
1370 * There are two locations (4, 4), (-4, -4). */
1371 const uint32_t eg_sample_locs_2x[4] = {
1372 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1373 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1374 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1375 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1376 };
1377 const unsigned eg_max_dist_2x = 4;
1378 /* 4xMSAA
1379 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1380 const uint32_t eg_sample_locs_4x[4] = {
1381 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1382 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1383 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1384 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1385 };
1386 const unsigned eg_max_dist_4x = 6;
1387
1388 /* Cayman 8xMSAA */
1389 static const uint32_t cm_sample_locs_8x[] = {
1390 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1391 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1392 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1393 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1394 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1395 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1396 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1397 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1398 };
1399 static const unsigned cm_max_dist_8x = 8;
1400 /* Cayman 16xMSAA */
1401 static const uint32_t cm_sample_locs_16x[] = {
1402 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1403 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1404 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1405 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1406 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1407 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1408 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1409 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1410 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1411 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1412 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1413 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1414 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1415 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1416 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1417 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1418 };
1419 static const unsigned cm_max_dist_16x = 8;
1420
1421 unsigned radv_cayman_get_maxdist(int log_samples)
1422 {
1423 unsigned max_dist[] = {
1424 0,
1425 eg_max_dist_2x,
1426 eg_max_dist_4x,
1427 cm_max_dist_8x,
1428 cm_max_dist_16x
1429 };
1430 return max_dist[log_samples];
1431 }
1432
1433 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1434 {
1435 switch (nr_samples) {
1436 default:
1437 case 1:
1438 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1439 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1440 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1441 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1442 break;
1443 case 2:
1444 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1445 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1446 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1447 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1448 break;
1449 case 4:
1450 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1451 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1452 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1453 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1454 break;
1455 case 8:
1456 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1457 radeon_emit(cs, cm_sample_locs_8x[0]);
1458 radeon_emit(cs, cm_sample_locs_8x[4]);
1459 radeon_emit(cs, 0);
1460 radeon_emit(cs, 0);
1461 radeon_emit(cs, cm_sample_locs_8x[1]);
1462 radeon_emit(cs, cm_sample_locs_8x[5]);
1463 radeon_emit(cs, 0);
1464 radeon_emit(cs, 0);
1465 radeon_emit(cs, cm_sample_locs_8x[2]);
1466 radeon_emit(cs, cm_sample_locs_8x[6]);
1467 radeon_emit(cs, 0);
1468 radeon_emit(cs, 0);
1469 radeon_emit(cs, cm_sample_locs_8x[3]);
1470 radeon_emit(cs, cm_sample_locs_8x[7]);
1471 break;
1472 case 16:
1473 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1474 radeon_emit(cs, cm_sample_locs_16x[0]);
1475 radeon_emit(cs, cm_sample_locs_16x[4]);
1476 radeon_emit(cs, cm_sample_locs_16x[8]);
1477 radeon_emit(cs, cm_sample_locs_16x[12]);
1478 radeon_emit(cs, cm_sample_locs_16x[1]);
1479 radeon_emit(cs, cm_sample_locs_16x[5]);
1480 radeon_emit(cs, cm_sample_locs_16x[9]);
1481 radeon_emit(cs, cm_sample_locs_16x[13]);
1482 radeon_emit(cs, cm_sample_locs_16x[2]);
1483 radeon_emit(cs, cm_sample_locs_16x[6]);
1484 radeon_emit(cs, cm_sample_locs_16x[10]);
1485 radeon_emit(cs, cm_sample_locs_16x[14]);
1486 radeon_emit(cs, cm_sample_locs_16x[3]);
1487 radeon_emit(cs, cm_sample_locs_16x[7]);
1488 radeon_emit(cs, cm_sample_locs_16x[11]);
1489 radeon_emit(cs, cm_sample_locs_16x[15]);
1490 break;
1491 }
1492 }
1493
1494 static void radv_cayman_get_sample_position(struct radv_device *device,
1495 unsigned sample_count,
1496 unsigned sample_index, float *out_value)
1497 {
1498 int offset, index;
1499 struct {
1500 int idx:4;
1501 } val;
1502 switch (sample_count) {
1503 case 1:
1504 default:
1505 out_value[0] = out_value[1] = 0.5;
1506 break;
1507 case 2:
1508 offset = 4 * (sample_index * 2);
1509 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1510 out_value[0] = (float)(val.idx + 8) / 16.0f;
1511 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1512 out_value[1] = (float)(val.idx + 8) / 16.0f;
1513 break;
1514 case 4:
1515 offset = 4 * (sample_index * 2);
1516 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1517 out_value[0] = (float)(val.idx + 8) / 16.0f;
1518 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1519 out_value[1] = (float)(val.idx + 8) / 16.0f;
1520 break;
1521 case 8:
1522 offset = 4 * (sample_index % 4 * 2);
1523 index = (sample_index / 4) * 4;
1524 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1525 out_value[0] = (float)(val.idx + 8) / 16.0f;
1526 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1527 out_value[1] = (float)(val.idx + 8) / 16.0f;
1528 break;
1529 case 16:
1530 offset = 4 * (sample_index % 4 * 2);
1531 index = (sample_index / 4) * 4;
1532 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1533 out_value[0] = (float)(val.idx + 8) / 16.0f;
1534 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1535 out_value[1] = (float)(val.idx + 8) / 16.0f;
1536 break;
1537 }
1538 }
1539
1540 void radv_device_init_msaa(struct radv_device *device)
1541 {
1542 int i;
1543 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1544
1545 for (i = 0; i < 2; i++)
1546 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1547 for (i = 0; i < 4; i++)
1548 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1549 for (i = 0; i < 8; i++)
1550 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1551 for (i = 0; i < 16; i++)
1552 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1553 }