2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for SI */
30 #include "radv_private.h"
31 #include "radv_shader.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
39 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
40 struct radeon_winsys_cs
*cs
,
41 unsigned raster_config
,
42 unsigned raster_config_1
)
44 unsigned sh_per_se
= MAX2(physical_device
->rad_info
.max_sh_per_se
, 1);
45 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
46 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
47 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
48 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
49 unsigned rb_per_se
= num_rb
/ num_se
;
53 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
54 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
55 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
56 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
58 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
59 assert(sh_per_se
== 1 || sh_per_se
== 2);
60 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
66 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
67 (!se_mask
[2] && !se_mask
[3]))) {
68 raster_config_1
&= C_028354_SE_PAIR_MAP
;
70 if (!se_mask
[0] && !se_mask
[1]) {
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
79 for (se
= 0; se
< num_se
; se
++) {
80 unsigned raster_config_se
= raster_config
;
81 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
82 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
83 int idx
= (se
/ 2) * 2;
85 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
86 raster_config_se
&= C_028350_SE_MAP
;
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
99 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
100 raster_config_se
&= C_028350_PKR_MAP
;
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
111 if (rb_per_se
>= 2) {
112 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
113 unsigned rb1_mask
= rb0_mask
<< 1;
117 if (!rb0_mask
|| !rb1_mask
) {
118 raster_config_se
&= C_028350_RB_MAP_PKR0
;
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
130 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
131 rb1_mask
= rb0_mask
<< 1;
134 if (!rb0_mask
|| !rb1_mask
) {
135 raster_config_se
&= C_028350_RB_MAP_PKR1
;
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device
->rad_info
.chip_class
< CIK
)
150 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
151 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
152 INSTANCE_BROADCAST_WRITES
);
154 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
155 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
158 if (physical_device
->rad_info
.chip_class
>= CIK
)
159 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device
->rad_info
.chip_class
< CIK
)
164 radeon_set_config_reg(cs
, GRBM_GFX_INDEX
,
165 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
166 INSTANCE_BROADCAST_WRITES
);
168 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
174 si_emit_compute(struct radv_physical_device
*physical_device
,
175 struct radeon_winsys_cs
*cs
)
177 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
182 radeon_set_sh_reg_seq(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 3);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188 if (physical_device
->rad_info
.chip_class
>= CIK
) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs
,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
192 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
203 if (physical_device
->rad_info
.chip_class
<= SI
) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
207 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
208 0x190 /* Default value */);
213 si_init_compute(struct radv_cmd_buffer
*cmd_buffer
)
215 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
216 si_emit_compute(physical_device
, cmd_buffer
->cs
);
219 /* 12.4 fixed-point */
220 static unsigned radv_pack_float_12p4(float x
)
223 x
>= 4096 ? 0xffff : x
* 16;
227 si_set_raster_config(struct radv_physical_device
*physical_device
,
228 struct radeon_winsys_cs
*cs
)
230 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
231 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
232 unsigned raster_config
, raster_config_1
;
234 switch (physical_device
->rad_info
.family
) {
237 raster_config
= 0x2a00126a;
238 raster_config_1
= 0x00000000;
241 raster_config
= 0x0000124a;
242 raster_config_1
= 0x00000000;
245 raster_config
= 0x00000082;
246 raster_config_1
= 0x00000000;
249 raster_config
= 0x00000000;
250 raster_config_1
= 0x00000000;
253 raster_config
= 0x16000012;
254 raster_config_1
= 0x00000000;
257 raster_config
= 0x3a00161a;
258 raster_config_1
= 0x0000002e;
261 if (physical_device
->rad_info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
262 /* old kernels with old tiling config */
263 raster_config
= 0x16000012;
264 raster_config_1
= 0x0000002a;
266 raster_config
= 0x3a00161a;
267 raster_config_1
= 0x0000002e;
271 raster_config
= 0x16000012;
272 raster_config_1
= 0x0000002a;
276 raster_config
= 0x16000012;
277 raster_config_1
= 0x00000000;
280 raster_config
= 0x16000012;
281 raster_config_1
= 0x0000002a;
285 raster_config
= 0x00000000;
287 raster_config
= 0x00000002;
288 raster_config_1
= 0x00000000;
291 raster_config
= 0x00000002;
292 raster_config_1
= 0x00000000;
295 /* KV should be 0x00000002, but that causes problems with radeon */
296 raster_config
= 0x00000000; /* 0x00000002 */
297 raster_config_1
= 0x00000000;
302 raster_config
= 0x00000000;
303 raster_config_1
= 0x00000000;
307 "radv: Unknown GPU, using 0 for raster_config\n");
308 raster_config
= 0x00000000;
309 raster_config_1
= 0x00000000;
313 /* Always use the default config when all backends are enabled
314 * (or when we failed to determine the enabled backends).
316 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
317 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
319 if (physical_device
->rad_info
.chip_class
>= CIK
)
320 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
323 si_write_harvested_raster_configs(physical_device
, cs
,
330 si_emit_config(struct radv_physical_device
*physical_device
,
331 struct radeon_winsys_cs
*cs
)
335 /* Only SI can disable CLEAR_STATE for now. */
336 assert(physical_device
->has_clear_state
||
337 physical_device
->rad_info
.chip_class
== SI
);
339 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
340 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
341 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
343 if (physical_device
->has_clear_state
) {
344 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
348 if (physical_device
->rad_info
.chip_class
<= VI
)
349 si_set_raster_config(physical_device
, cs
);
351 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
352 if (!physical_device
->has_clear_state
)
353 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
355 /* FIXME calculate these values somehow ??? */
356 if (physical_device
->rad_info
.chip_class
<= VI
) {
357 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
358 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
361 if (!physical_device
->has_clear_state
) {
362 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
363 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
364 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
367 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
368 if (!physical_device
->has_clear_state
)
369 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
370 if (physical_device
->rad_info
.chip_class
< CIK
)
371 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
372 S_008A14_CLIP_VTX_REORDER_ENA(1));
374 radeon_set_context_reg(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
375 radeon_set_context_reg(cs
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
377 if (!physical_device
->has_clear_state
)
378 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
380 /* CLEAR_STATE doesn't clear these correctly on certain generations.
381 * I don't know why. Deduced by trial and error.
383 if (physical_device
->rad_info
.chip_class
<= CIK
) {
384 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
385 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
386 S_028204_WINDOW_OFFSET_DISABLE(1));
387 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
388 S_028240_WINDOW_OFFSET_DISABLE(1));
389 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
390 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
391 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
392 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
393 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
396 if (!physical_device
->has_clear_state
) {
397 for (i
= 0; i
< 16; i
++) {
398 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
399 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
403 if (!physical_device
->has_clear_state
) {
404 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
405 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
406 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
407 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
408 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
409 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
410 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
411 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
414 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
415 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
416 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
418 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
419 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
420 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
421 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
423 /* These registers, when written, also overwrite the
424 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
425 * them. It would be an issue if there was another UMD
428 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
429 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
430 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
433 if (physical_device
->rad_info
.chip_class
>= CIK
) {
434 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
435 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_CU_EN(0xffff));
437 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
438 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
439 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
440 /* If this is 0, Bonaire can hang even if GS isn't being used.
441 * Other chips are unaffected. These are suboptimal values,
442 * but we don't use on-chip GS.
444 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
445 S_028A44_ES_VERTS_PER_SUBGRP(64) |
446 S_028A44_GS_PRIMS_PER_SUBGRP(4));
448 radeon_set_sh_reg(cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
450 if (physical_device
->rad_info
.num_good_compute_units
/
451 (physical_device
->rad_info
.max_se
* physical_device
->rad_info
.max_sh_per_se
) <= 4) {
452 /* Too few available compute units per SH. Disallowing
453 * VS to run on CU0 could hurt us more than late VS
454 * allocation would help.
456 * LATE_ALLOC_VS = 2 is the highest safe number.
458 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
459 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
461 /* Set LATE_ALLOC_VS == 31. It should be less than
462 * the number of scratch waves. Limitations:
463 * - VS can't execute on CU0.
464 * - If HS writes outputs to LDS, LS can't execute on CU0.
466 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
467 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
470 radeon_set_sh_reg(cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
473 if (physical_device
->rad_info
.chip_class
>= VI
) {
474 uint32_t vgt_tess_distribution
;
475 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
476 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
477 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
479 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
480 S_028B50_ACCUM_TRI(11) |
481 S_028B50_ACCUM_QUAD(11) |
482 S_028B50_DONUT_SPLIT(16);
484 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
485 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
486 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
488 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
489 vgt_tess_distribution
);
490 } else if (!physical_device
->has_clear_state
) {
491 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
492 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
495 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
496 unsigned num_se
= physical_device
->rad_info
.max_se
;
497 unsigned pc_lines
= 0;
499 switch (physical_device
->rad_info
.family
) {
510 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
511 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
));
512 /* TODO: Enable the binner: */
513 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
514 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
515 S_028C44_DISABLE_START_OF_PRIM(1));
516 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
517 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
518 S_028C48_MAX_PRIM_PER_BATCH(1023));
519 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
520 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
521 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
524 unsigned tmp
= (unsigned)(1.0 * 8.0);
525 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
526 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
527 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
528 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
529 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
531 si_emit_compute(physical_device
, cs
);
534 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
)
536 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
538 si_emit_config(physical_device
, cmd_buffer
->cs
);
542 cik_create_gfx_config(struct radv_device
*device
)
544 struct radeon_winsys_cs
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
548 si_emit_config(device
->physical_device
, cs
);
550 while (cs
->cdw
& 7) {
551 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
552 radeon_emit(cs
, 0x80000000);
554 radeon_emit(cs
, 0xffff1000);
557 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
560 RADEON_FLAG_CPU_ACCESS
);
561 if (!device
->gfx_init
)
564 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
566 device
->ws
->buffer_destroy(device
->gfx_init
);
567 device
->gfx_init
= NULL
;
570 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
572 device
->ws
->buffer_unmap(device
->gfx_init
);
573 device
->gfx_init_size_dw
= cs
->cdw
;
575 device
->ws
->cs_destroy(cs
);
579 get_viewport_xform(const VkViewport
*viewport
,
580 float scale
[3], float translate
[3])
582 float x
= viewport
->x
;
583 float y
= viewport
->y
;
584 float half_width
= 0.5f
* viewport
->width
;
585 float half_height
= 0.5f
* viewport
->height
;
586 double n
= viewport
->minDepth
;
587 double f
= viewport
->maxDepth
;
589 scale
[0] = half_width
;
590 translate
[0] = half_width
+ x
;
591 scale
[1] = half_height
;
592 translate
[1] = half_height
+ y
;
599 si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
600 int count
, const VkViewport
*viewports
)
605 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
606 first_vp
* 4 * 6, count
* 6);
608 for (i
= 0; i
< count
; i
++) {
609 float scale
[3], translate
[3];
612 get_viewport_xform(&viewports
[i
], scale
, translate
);
613 radeon_emit(cs
, fui(scale
[0]));
614 radeon_emit(cs
, fui(translate
[0]));
615 radeon_emit(cs
, fui(scale
[1]));
616 radeon_emit(cs
, fui(translate
[1]));
617 radeon_emit(cs
, fui(scale
[2]));
618 radeon_emit(cs
, fui(translate
[2]));
621 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
622 first_vp
* 4 * 2, count
* 2);
623 for (i
= 0; i
< count
; i
++) {
624 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
625 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
626 radeon_emit(cs
, fui(zmin
));
627 radeon_emit(cs
, fui(zmax
));
631 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
633 float scale
[3], translate
[3];
636 get_viewport_xform(viewport
, scale
, translate
);
638 rect
.offset
.x
= translate
[0] - abs(scale
[0]);
639 rect
.offset
.y
= translate
[1] - abs(scale
[1]);
640 rect
.extent
.width
= ceilf(translate
[0] + abs(scale
[0])) - rect
.offset
.x
;
641 rect
.extent
.height
= ceilf(translate
[1] + abs(scale
[1])) - rect
.offset
.y
;
646 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
648 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
649 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
650 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
651 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
652 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
653 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
658 si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
659 int count
, const VkRect2D
*scissors
,
660 const VkViewport
*viewports
, bool can_use_guardband
)
663 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
664 const float max_range
= 32767.0f
;
667 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
668 for (i
= 0; i
< count
; i
++) {
669 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
670 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
672 get_viewport_xform(viewports
+ i
, scale
, translate
);
673 scale
[0] = abs(scale
[0]);
674 scale
[1] = abs(scale
[1]);
681 guardband_x
= MIN2(guardband_x
, (max_range
- abs(translate
[0])) / scale
[0]);
682 guardband_y
= MIN2(guardband_y
, (max_range
- abs(translate
[1])) / scale
[1]);
684 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
685 S_028250_TL_Y(scissor
.offset
.y
) |
686 S_028250_WINDOW_OFFSET_DISABLE(1));
687 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
688 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
690 if (!can_use_guardband
) {
695 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
696 radeon_emit(cs
, fui(guardband_y
));
697 radeon_emit(cs
, fui(1.0));
698 radeon_emit(cs
, fui(guardband_x
));
699 radeon_emit(cs
, fui(1.0));
702 static inline unsigned
703 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
714 return 1 + ((num
- info
->min
) / info
->incr
);
718 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
719 bool instanced_draw
, bool indirect_draw
,
720 uint32_t draw_vertex_count
)
722 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
723 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
724 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
725 const unsigned max_primgroup_in_wave
= 2;
726 /* SWITCH_ON_EOP(0) is always preferable. */
727 bool wd_switch_on_eop
= false;
728 bool ia_switch_on_eop
= false;
729 bool ia_switch_on_eoi
= false;
730 bool partial_vs_wave
= false;
731 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.partial_es_wave
;
732 bool multi_instances_smaller_than_primgroup
;
734 multi_instances_smaller_than_primgroup
= indirect_draw
;
735 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
736 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
737 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.primgroup_size
)
738 multi_instances_smaller_than_primgroup
= true;
741 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_switch_on_eoi
;
742 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.partial_vs_wave
;
744 if (chip_class
>= CIK
) {
745 wd_switch_on_eop
= cmd_buffer
->state
.pipeline
->graphics
.wd_switch_on_eop
;
747 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
748 * We don't know that for indirect drawing, so treat it as
749 * always problematic. */
750 if (family
== CHIP_HAWAII
&&
751 (instanced_draw
|| indirect_draw
))
752 wd_switch_on_eop
= true;
754 /* Performance recommendation for 4 SE Gfx7-8 parts if
755 * instances are smaller than a primgroup.
756 * Assume indirect draws always use small instances.
757 * This is needed for good VS wave utilization.
759 if (chip_class
<= VI
&&
761 multi_instances_smaller_than_primgroup
)
762 wd_switch_on_eop
= true;
764 /* Required on CIK and later. */
765 if (info
->max_se
> 2 && !wd_switch_on_eop
)
766 ia_switch_on_eoi
= true;
768 /* Required by Hawaii and, for some special cases, by VI. */
769 if (ia_switch_on_eoi
&&
770 (family
== CHIP_HAWAII
||
772 /* max primgroup in wave is always 2 - leave this for documentation */
773 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
774 partial_vs_wave
= true;
776 /* Instancing bug on Bonaire. */
777 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
778 (instanced_draw
|| indirect_draw
))
779 partial_vs_wave
= true;
781 /* If the WD switch is false, the IA switch must be false too. */
782 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
784 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
785 if (chip_class
<= VI
&& ia_switch_on_eoi
)
786 partial_es_wave
= true;
788 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
789 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
790 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
791 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
793 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
794 bool set_vgt_flush
= indirect_draw
;
795 if (!set_vgt_flush
&& instanced_draw
) {
796 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
798 set_vgt_flush
= true;
801 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
805 return cmd_buffer
->state
.pipeline
->graphics
.base_ia_multi_vgt_param
|
806 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
807 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
808 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
809 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
810 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= CIK
? wd_switch_on_eop
: 0);
814 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
816 enum chip_class chip_class
,
818 unsigned event
, unsigned event_flags
,
824 unsigned op
= EVENT_TYPE(event
) |
827 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
829 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
830 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, predicated
));
832 radeon_emit(cs
, EOP_DATA_SEL(data_sel
));
833 radeon_emit(cs
, va
); /* address lo */
834 radeon_emit(cs
, va
>> 32); /* address hi */
835 radeon_emit(cs
, new_fence
); /* immediate data lo */
836 radeon_emit(cs
, 0); /* immediate data hi */
838 radeon_emit(cs
, 0); /* unused */
840 if (chip_class
== CIK
||
842 /* Two EOP events are required to make all engines go idle
843 * (and optional cache flushes executed) before the timestamp
846 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
849 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
850 radeon_emit(cs
, old_fence
); /* immediate data */
851 radeon_emit(cs
, 0); /* unused */
854 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
857 radeon_emit(cs
, ((va
>> 32) & 0xffff) | EOP_DATA_SEL(data_sel
));
858 radeon_emit(cs
, new_fence
); /* immediate data */
859 radeon_emit(cs
, 0); /* unused */
864 si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
866 uint64_t va
, uint32_t ref
,
869 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, predicated
));
870 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
872 radeon_emit(cs
, va
>> 32);
873 radeon_emit(cs
, ref
); /* reference value */
874 radeon_emit(cs
, mask
); /* mask */
875 radeon_emit(cs
, 4); /* poll interval */
879 si_emit_acquire_mem(struct radeon_winsys_cs
*cs
,
883 unsigned cp_coher_cntl
)
885 if (is_mec
|| is_gfx9
) {
886 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
887 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, predicated
) |
888 PKT3_SHADER_TYPE_S(is_mec
));
889 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
890 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
891 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
892 radeon_emit(cs
, 0); /* CP_COHER_BASE */
893 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
894 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
896 /* ACQUIRE_MEM is only required on a compute ring. */
897 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, predicated
));
898 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
899 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
900 radeon_emit(cs
, 0); /* CP_COHER_BASE */
901 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
906 si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
908 enum chip_class chip_class
,
912 enum radv_cmd_flush_bits flush_bits
)
914 unsigned cp_coher_cntl
= 0;
915 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
916 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
918 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
919 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
920 if (flush_bits
& RADV_CMD_FLAG_INV_SMEM_L1
)
921 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
923 if (chip_class
<= VI
) {
924 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
925 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
926 S_0085F0_CB0_DEST_BASE_ENA(1) |
927 S_0085F0_CB1_DEST_BASE_ENA(1) |
928 S_0085F0_CB2_DEST_BASE_ENA(1) |
929 S_0085F0_CB3_DEST_BASE_ENA(1) |
930 S_0085F0_CB4_DEST_BASE_ENA(1) |
931 S_0085F0_CB5_DEST_BASE_ENA(1) |
932 S_0085F0_CB6_DEST_BASE_ENA(1) |
933 S_0085F0_CB7_DEST_BASE_ENA(1);
935 /* Necessary for DCC */
936 if (chip_class
>= VI
) {
937 si_cs_emit_write_event_eop(cs
,
941 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
945 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
946 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
947 S_0085F0_DB_DEST_BASE_ENA(1);
951 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
952 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
953 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
956 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
957 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
958 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
962 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
963 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
964 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
965 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
966 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
967 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
971 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
972 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
973 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
976 if (chip_class
>= GFX9
&& flush_cb_db
) {
977 unsigned cb_db_event
, tc_flags
;
979 /* Set the CB/DB flush event. */
980 switch (flush_cb_db
) {
981 case RADV_CMD_FLAG_FLUSH_AND_INV_CB
:
982 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
984 case RADV_CMD_FLAG_FLUSH_AND_INV_DB
:
985 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
989 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
992 /* TC | TC_WB = invalidate L2 data
993 * TC_MD | TC_WB = invalidate L2 metadata
994 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
996 * The metadata cache must always be invalidated for coherency
997 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
999 * TC must be invalidated on GFX9 only if the CB/DB surface is
1000 * not pipe-aligned. If the surface is RB-aligned, it might not
1001 * strictly be pipe-aligned since RB alignment takes precendence.
1003 tc_flags
= EVENT_TC_WB_ACTION_ENA
|
1004 EVENT_TC_MD_ACTION_ENA
;
1006 /* Ideally flush TC together with CB/DB. */
1007 if (flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) {
1008 tc_flags
|= EVENT_TC_ACTION_ENA
|
1009 EVENT_TCL1_ACTION_ENA
;
1011 /* Clear the flags. */
1012 flush_bits
&= ~(RADV_CMD_FLAG_INV_GLOBAL_L2
|
1013 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
|
1014 RADV_CMD_FLAG_INV_VMEM_L1
);
1017 uint32_t old_fence
= (*flush_cnt
)++;
1019 si_cs_emit_write_event_eop(cs
, predicated
, chip_class
, false, cb_db_event
, tc_flags
, 1,
1020 flush_va
, old_fence
, *flush_cnt
);
1021 si_emit_wait_fence(cs
, predicated
, flush_va
, *flush_cnt
, 0xffffffff);
1024 /* VGT state sync */
1025 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1026 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, predicated
));
1027 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1030 /* Make sure ME is idle (it executes most packets) before continuing.
1031 * This prevents read-after-write hazards between PFP and ME.
1033 if ((cp_coher_cntl
||
1034 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1035 RADV_CMD_FLAG_INV_VMEM_L1
|
1036 RADV_CMD_FLAG_INV_GLOBAL_L2
|
1037 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) &&
1039 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, predicated
));
1043 if ((flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) ||
1044 (chip_class
<= CIK
&& (flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) {
1045 si_emit_acquire_mem(cs
, is_mec
, predicated
, chip_class
>= GFX9
,
1047 S_0085F0_TC_ACTION_ENA(1) |
1048 S_0085F0_TCL1_ACTION_ENA(1) |
1049 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= VI
));
1052 if(flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
) {
1054 * NC = apply to non-coherent MTYPEs
1055 * (i.e. MTYPE <= 1, which is what we use everywhere)
1057 * WB doesn't work without NC.
1059 si_emit_acquire_mem(cs
, is_mec
, predicated
,
1062 S_0301F0_TC_WB_ACTION_ENA(1) |
1063 S_0301F0_TC_NC_ACTION_ENA(1));
1066 if (flush_bits
& RADV_CMD_FLAG_INV_VMEM_L1
) {
1067 si_emit_acquire_mem(cs
, is_mec
,
1068 predicated
, chip_class
>= GFX9
,
1070 S_0085F0_TCL1_ACTION_ENA(1));
1075 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1076 * Therefore, it should be last. Done in PFP.
1079 si_emit_acquire_mem(cs
, is_mec
, predicated
, chip_class
>= GFX9
, cp_coher_cntl
);
1083 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
1085 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1088 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1089 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1090 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1091 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1092 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1093 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1094 RADV_CMD_FLAG_VGT_FLUSH
);
1096 if (!cmd_buffer
->state
.flush_bits
)
1099 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
1100 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
1102 uint32_t *ptr
= NULL
;
1104 if (chip_class
== GFX9
) {
1105 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) + cmd_buffer
->gfx9_fence_offset
;
1106 ptr
= &cmd_buffer
->gfx9_fence_idx
;
1108 si_cs_emit_cache_flush(cmd_buffer
->cs
,
1109 cmd_buffer
->state
.predicating
,
1110 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1112 radv_cmd_buffer_uses_mec(cmd_buffer
),
1113 cmd_buffer
->state
.flush_bits
);
1116 radv_cmd_buffer_trace_emit(cmd_buffer
);
1117 cmd_buffer
->state
.flush_bits
= 0;
1120 /* sets the CP predication state using a boolean stored at va */
1122 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
1127 op
= PRED_OP(PREDICATION_OP_BOOL64
) | PREDICATION_DRAW_VISIBLE
;
1128 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1129 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1130 radeon_emit(cmd_buffer
->cs
, op
);
1131 radeon_emit(cmd_buffer
->cs
, va
);
1132 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1134 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1135 radeon_emit(cmd_buffer
->cs
, va
);
1136 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1140 /* Set this if you want the 3D engine to wait until CP DMA is done.
1141 * It should be set on the last CP DMA packet. */
1142 #define CP_DMA_SYNC (1 << 0)
1144 /* Set this if the source data was used as a destination in a previous CP DMA
1145 * packet. It's for preventing a read-after-write (RAW) hazard between two
1146 * CP DMA packets. */
1147 #define CP_DMA_RAW_WAIT (1 << 1)
1148 #define CP_DMA_USE_L2 (1 << 2)
1149 #define CP_DMA_CLEAR (1 << 3)
1151 /* Alignment for optimal performance. */
1152 #define SI_CPDMA_ALIGNMENT 32
1154 /* The max number of bytes that can be copied per packet. */
1155 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1157 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1158 S_414_BYTE_COUNT_GFX9(~0u) :
1159 S_414_BYTE_COUNT_GFX6(~0u);
1161 /* make it aligned for optimal performance */
1162 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1165 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1166 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1169 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1170 uint64_t dst_va
, uint64_t src_va
,
1171 unsigned size
, unsigned flags
)
1173 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1174 uint32_t header
= 0, command
= 0;
1177 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1179 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1180 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1181 command
|= S_414_BYTE_COUNT_GFX9(size
);
1183 command
|= S_414_BYTE_COUNT_GFX6(size
);
1186 if (flags
& CP_DMA_SYNC
)
1187 header
|= S_411_CP_SYNC(1);
1189 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1190 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1192 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1195 if (flags
& CP_DMA_RAW_WAIT
)
1196 command
|= S_414_RAW_WAIT(1);
1198 /* Src and dst flags. */
1199 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1200 !(flags
& CP_DMA_CLEAR
) &&
1202 header
|= S_411_DSL_SEL(V_411_NOWHERE
); /* prefetch only */
1203 else if (flags
& CP_DMA_USE_L2
)
1204 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
1206 if (flags
& CP_DMA_CLEAR
)
1207 header
|= S_411_SRC_SEL(V_411_DATA
);
1208 else if (flags
& CP_DMA_USE_L2
)
1209 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1211 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1212 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1213 radeon_emit(cs
, header
);
1214 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1215 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1216 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1217 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1218 radeon_emit(cs
, command
);
1220 assert(!(flags
& CP_DMA_USE_L2
));
1221 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1222 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1223 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1224 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1225 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1226 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1227 radeon_emit(cs
, command
);
1230 /* CP DMA is executed in ME, but index buffers are read by PFP.
1231 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1232 * indices. If we wanted to execute CP DMA in PFP, this packet
1233 * should precede it.
1235 if ((flags
& CP_DMA_SYNC
) && cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1236 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1240 radv_cmd_buffer_trace_emit(cmd_buffer
);
1243 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1246 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1247 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1249 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1250 aligned_size
, CP_DMA_USE_L2
);
1253 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1254 uint64_t remaining_size
, unsigned *flags
)
1257 /* Flush the caches for the first copy only.
1258 * Also wait for the previous CP DMA operations.
1260 if (cmd_buffer
->state
.flush_bits
) {
1261 si_emit_cache_flush(cmd_buffer
);
1262 *flags
|= CP_DMA_RAW_WAIT
;
1265 /* Do the synchronization after the last dma, so that all data
1266 * is written to memory.
1268 if (byte_count
== remaining_size
)
1269 *flags
|= CP_DMA_SYNC
;
1272 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1276 unsigned dma_flags
= 0;
1277 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1280 assert(size
< SI_CPDMA_ALIGNMENT
);
1282 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1284 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1287 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1289 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1293 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1294 uint64_t src_va
, uint64_t dest_va
,
1297 uint64_t main_src_va
, main_dest_va
;
1298 uint64_t skipped_size
= 0, realign_size
= 0;
1301 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1302 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1303 /* If the size is not aligned, we must add a dummy copy at the end
1304 * just to align the internal counter. Otherwise, the DMA engine
1305 * would slow down by an order of magnitude for following copies.
1307 if (size
% SI_CPDMA_ALIGNMENT
)
1308 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1310 /* If the copy begins unaligned, we must start copying from the next
1311 * aligned block and the skipped part should be copied after everything
1312 * else has been copied. Only the src alignment matters, not dst.
1314 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1315 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1316 /* The main part will be skipped if the size is too small. */
1317 skipped_size
= MIN2(skipped_size
, size
);
1318 size
-= skipped_size
;
1321 main_src_va
= src_va
+ skipped_size
;
1322 main_dest_va
= dest_va
+ skipped_size
;
1325 unsigned dma_flags
= 0;
1326 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1328 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1329 size
+ skipped_size
+ realign_size
,
1332 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1333 byte_count
, dma_flags
);
1336 main_src_va
+= byte_count
;
1337 main_dest_va
+= byte_count
;
1341 unsigned dma_flags
= 0;
1343 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1344 size
+ skipped_size
+ realign_size
,
1347 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1348 skipped_size
, dma_flags
);
1351 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1354 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1355 uint64_t size
, unsigned value
)
1361 assert(va
% 4 == 0 && size
% 4 == 0);
1364 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1365 unsigned dma_flags
= CP_DMA_CLEAR
;
1367 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1369 /* Emit the clear packet. */
1370 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1378 /* For MSAA sample positions. */
1379 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1380 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1381 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1382 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1383 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1387 * There are two locations (4, 4), (-4, -4). */
1388 const uint32_t eg_sample_locs_2x
[4] = {
1389 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1390 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1391 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1392 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1394 const unsigned eg_max_dist_2x
= 4;
1396 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1397 const uint32_t eg_sample_locs_4x
[4] = {
1398 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1399 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1400 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1401 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1403 const unsigned eg_max_dist_4x
= 6;
1406 static const uint32_t cm_sample_locs_8x
[] = {
1407 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1408 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1409 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1410 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1411 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1412 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1413 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1414 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1416 static const unsigned cm_max_dist_8x
= 8;
1417 /* Cayman 16xMSAA */
1418 static const uint32_t cm_sample_locs_16x
[] = {
1419 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1420 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1421 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1422 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1423 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1424 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1425 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1426 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1427 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1428 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1429 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1430 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1431 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1432 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1433 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1434 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1436 static const unsigned cm_max_dist_16x
= 8;
1438 unsigned radv_cayman_get_maxdist(int log_samples
)
1440 unsigned max_dist
[] = {
1447 return max_dist
[log_samples
];
1450 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
)
1452 switch (nr_samples
) {
1455 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0);
1456 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0);
1457 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0);
1458 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0);
1461 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_2x
[0]);
1462 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_2x
[1]);
1463 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_2x
[2]);
1464 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_2x
[3]);
1467 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_4x
[0]);
1468 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_4x
[1]);
1469 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_4x
[2]);
1470 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_4x
[3]);
1473 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1474 radeon_emit(cs
, cm_sample_locs_8x
[0]);
1475 radeon_emit(cs
, cm_sample_locs_8x
[4]);
1478 radeon_emit(cs
, cm_sample_locs_8x
[1]);
1479 radeon_emit(cs
, cm_sample_locs_8x
[5]);
1482 radeon_emit(cs
, cm_sample_locs_8x
[2]);
1483 radeon_emit(cs
, cm_sample_locs_8x
[6]);
1486 radeon_emit(cs
, cm_sample_locs_8x
[3]);
1487 radeon_emit(cs
, cm_sample_locs_8x
[7]);
1490 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
1491 radeon_emit(cs
, cm_sample_locs_16x
[0]);
1492 radeon_emit(cs
, cm_sample_locs_16x
[4]);
1493 radeon_emit(cs
, cm_sample_locs_16x
[8]);
1494 radeon_emit(cs
, cm_sample_locs_16x
[12]);
1495 radeon_emit(cs
, cm_sample_locs_16x
[1]);
1496 radeon_emit(cs
, cm_sample_locs_16x
[5]);
1497 radeon_emit(cs
, cm_sample_locs_16x
[9]);
1498 radeon_emit(cs
, cm_sample_locs_16x
[13]);
1499 radeon_emit(cs
, cm_sample_locs_16x
[2]);
1500 radeon_emit(cs
, cm_sample_locs_16x
[6]);
1501 radeon_emit(cs
, cm_sample_locs_16x
[10]);
1502 radeon_emit(cs
, cm_sample_locs_16x
[14]);
1503 radeon_emit(cs
, cm_sample_locs_16x
[3]);
1504 radeon_emit(cs
, cm_sample_locs_16x
[7]);
1505 radeon_emit(cs
, cm_sample_locs_16x
[11]);
1506 radeon_emit(cs
, cm_sample_locs_16x
[15]);
1511 static void radv_cayman_get_sample_position(struct radv_device
*device
,
1512 unsigned sample_count
,
1513 unsigned sample_index
, float *out_value
)
1519 switch (sample_count
) {
1522 out_value
[0] = out_value
[1] = 0.5;
1525 offset
= 4 * (sample_index
* 2);
1526 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1527 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1528 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1529 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1532 offset
= 4 * (sample_index
* 2);
1533 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1534 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1535 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1536 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1539 offset
= 4 * (sample_index
% 4 * 2);
1540 index
= (sample_index
/ 4) * 4;
1541 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1542 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1543 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1544 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1547 offset
= 4 * (sample_index
% 4 * 2);
1548 index
= (sample_index
/ 4) * 4;
1549 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
1550 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1551 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
1552 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1557 void radv_device_init_msaa(struct radv_device
*device
)
1560 radv_cayman_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1562 for (i
= 0; i
< 2; i
++)
1563 radv_cayman_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1564 for (i
= 0; i
< 4; i
++)
1565 radv_cayman_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1566 for (i
= 0; i
< 8; i
++)
1567 radv_cayman_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);
1568 for (i
= 0; i
< 16; i
++)
1569 radv_cayman_get_sample_position(device
, 16, i
, device
->sample_locations_16x
[i
]);