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6d01e0ad7fd90e1e076ea3683bd266051181428c
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX10) {
241 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
244 } else if (physical_device->rad_info.chip_class >= GFX9) {
245 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
248 } else {
249 /* These registers, when written, also overwrite the
250 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
251 * them. It would be an issue if there was another UMD
252 * changing them.
253 */
254 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
255 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
256 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
257 }
258
259 if (physical_device->rad_info.chip_class >= GFX7) {
260 if (physical_device->rad_info.chip_class >= GFX10) {
261 /* Logical CUs 16 - 31 */
262 radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
263 S_00B404_CU_EN(0xffff));
264 radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
265 S_00B204_CU_EN(0xffff) |
266 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
267 radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
268 S_00B104_CU_EN(0xffff));
269 radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
270 S_00B004_CU_EN(0xffff));
271 }
272
273 if (physical_device->rad_info.chip_class >= GFX9) {
274 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
275 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
276 } else {
277 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
278 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
279 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 S_00B41C_WAVE_LIMIT(0x3F));
281 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
282 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
283 /* If this is 0, Bonaire can hang even if GS isn't being used.
284 * Other chips are unaffected. These are suboptimal values,
285 * but we don't use on-chip GS.
286 */
287 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
288 S_028A44_ES_VERTS_PER_SUBGRP(64) |
289 S_028A44_GS_PRIMS_PER_SUBGRP(4));
290 }
291 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
292 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
293
294 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
295 /* Too few available compute units per SH. Disallowing
296 * VS to run on CU0 could hurt us more than late VS
297 * allocation would help.
298 *
299 * LATE_ALLOC_VS = 2 is the highest safe number.
300 */
301 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
302 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
303 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
304 } else {
305 /* Set LATE_ALLOC_VS == 31. It should be less than
306 * the number of scratch waves. Limitations:
307 * - VS can't execute on CU0.
308 * - If HS writes outputs to LDS, LS can't execute on CU0.
309 */
310 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
311 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
312 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
313 }
314
315 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
316 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
317 }
318
319 if (physical_device->rad_info.chip_class >= GFX10) {
320 /* Break up a pixel wave if it contains deallocs for more than
321 * half the parameter cache.
322 *
323 * To avoid a deadlock where pixel waves aren't launched
324 * because they're waiting for more pixels while the frontend
325 * is stuck waiting for PC space, the maximum allowed value is
326 * the size of the PC minus the largest possible allocation for
327 * a single primitive shader subgroup.
328 */
329 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
330 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
331 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
332 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
333 physical_device->rad_info.pa_sc_tile_steering_override);
334 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
335 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
336 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
337 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
338 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
339 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
340 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
341 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
342
343 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
344 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
345 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
346 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
347 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
348 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
349 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
350 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
351 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
352 }
353
354 if (physical_device->rad_info.chip_class >= GFX8) {
355 uint32_t vgt_tess_distribution;
356
357 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
358 S_028B50_ACCUM_TRI(11) |
359 S_028B50_ACCUM_QUAD(11) |
360 S_028B50_DONUT_SPLIT(16);
361
362 if (physical_device->rad_info.family == CHIP_FIJI ||
363 physical_device->rad_info.family >= CHIP_POLARIS10)
364 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
365
366 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
367 vgt_tess_distribution);
368 } else if (!physical_device->has_clear_state) {
369 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
370 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
371 }
372
373 if (physical_device->rad_info.chip_class >= GFX9) {
374 unsigned num_se = physical_device->rad_info.max_se;
375 unsigned pc_lines = 0;
376 unsigned max_alloc_count = 0;
377
378 switch (physical_device->rad_info.family) {
379 case CHIP_VEGA10:
380 case CHIP_VEGA12:
381 case CHIP_VEGA20:
382 pc_lines = 4096;
383 break;
384 case CHIP_RAVEN:
385 case CHIP_RAVEN2:
386 case CHIP_NAVI10:
387 case CHIP_NAVI12:
388 pc_lines = 1024;
389 break;
390 case CHIP_NAVI14:
391 pc_lines = 512;
392 break;
393 default:
394 assert(0);
395 }
396
397 if (physical_device->rad_info.chip_class >= GFX10) {
398 max_alloc_count = pc_lines / 3;
399 } else {
400 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
401 }
402
403 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
404 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
405 S_028C48_MAX_PRIM_PER_BATCH(1023));
406 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
407 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
408 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
409 }
410
411 unsigned tmp = (unsigned)(1.0 * 8.0);
412 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
413 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
414 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
415 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
416 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
417
418 if (!physical_device->has_clear_state) {
419 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
420 S_028004_ZPASS_INCREMENT_DISABLE(1));
421 }
422
423 /* Enable the Polaris small primitive filter control.
424 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
425 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
426 * and AMDVLK doesn't have a workaround as well.
427 */
428 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
429 unsigned small_prim_filter_cntl =
430 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
431 /* Workaround for a hw line bug. */
432 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
433
434 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
435 small_prim_filter_cntl);
436 }
437
438 si_emit_compute(physical_device, cs);
439 }
440
441 void
442 cik_create_gfx_config(struct radv_device *device)
443 {
444 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
445 if (!cs)
446 return;
447
448 si_emit_graphics(device->physical_device, cs);
449
450 while (cs->cdw & 7) {
451 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
452 radeon_emit(cs, 0x80000000);
453 else
454 radeon_emit(cs, 0xffff1000);
455 }
456
457 device->gfx_init = device->ws->buffer_create(device->ws,
458 cs->cdw * 4, 4096,
459 RADEON_DOMAIN_GTT,
460 RADEON_FLAG_CPU_ACCESS|
461 RADEON_FLAG_NO_INTERPROCESS_SHARING |
462 RADEON_FLAG_READ_ONLY,
463 RADV_BO_PRIORITY_CS);
464 if (!device->gfx_init)
465 goto fail;
466
467 void *map = device->ws->buffer_map(device->gfx_init);
468 if (!map) {
469 device->ws->buffer_destroy(device->gfx_init);
470 device->gfx_init = NULL;
471 goto fail;
472 }
473 memcpy(map, cs->buf, cs->cdw * 4);
474
475 device->ws->buffer_unmap(device->gfx_init);
476 device->gfx_init_size_dw = cs->cdw;
477 fail:
478 device->ws->cs_destroy(cs);
479 }
480
481 static void
482 get_viewport_xform(const VkViewport *viewport,
483 float scale[3], float translate[3])
484 {
485 float x = viewport->x;
486 float y = viewport->y;
487 float half_width = 0.5f * viewport->width;
488 float half_height = 0.5f * viewport->height;
489 double n = viewport->minDepth;
490 double f = viewport->maxDepth;
491
492 scale[0] = half_width;
493 translate[0] = half_width + x;
494 scale[1] = half_height;
495 translate[1] = half_height + y;
496
497 scale[2] = (f - n);
498 translate[2] = n;
499 }
500
501 void
502 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
503 int count, const VkViewport *viewports)
504 {
505 int i;
506
507 assert(count);
508 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
509 first_vp * 4 * 6, count * 6);
510
511 for (i = 0; i < count; i++) {
512 float scale[3], translate[3];
513
514
515 get_viewport_xform(&viewports[i], scale, translate);
516 radeon_emit(cs, fui(scale[0]));
517 radeon_emit(cs, fui(translate[0]));
518 radeon_emit(cs, fui(scale[1]));
519 radeon_emit(cs, fui(translate[1]));
520 radeon_emit(cs, fui(scale[2]));
521 radeon_emit(cs, fui(translate[2]));
522 }
523
524 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
525 first_vp * 4 * 2, count * 2);
526 for (i = 0; i < count; i++) {
527 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
528 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
529 radeon_emit(cs, fui(zmin));
530 radeon_emit(cs, fui(zmax));
531 }
532 }
533
534 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
535 {
536 float scale[3], translate[3];
537 VkRect2D rect;
538
539 get_viewport_xform(viewport, scale, translate);
540
541 rect.offset.x = translate[0] - fabs(scale[0]);
542 rect.offset.y = translate[1] - fabs(scale[1]);
543 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
544 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
545
546 return rect;
547 }
548
549 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
550 VkRect2D ret;
551 ret.offset.x = MAX2(a->offset.x, b->offset.x);
552 ret.offset.y = MAX2(a->offset.y, b->offset.y);
553 ret.extent.width = MIN2(a->offset.x + a->extent.width,
554 b->offset.x + b->extent.width) - ret.offset.x;
555 ret.extent.height = MIN2(a->offset.y + a->extent.height,
556 b->offset.y + b->extent.height) - ret.offset.y;
557 return ret;
558 }
559
560 void
561 si_write_scissors(struct radeon_cmdbuf *cs, int first,
562 int count, const VkRect2D *scissors,
563 const VkViewport *viewports, bool can_use_guardband)
564 {
565 int i;
566 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
567 const float max_range = 32767.0f;
568 if (!count)
569 return;
570
571 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
572 for (i = 0; i < count; i++) {
573 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
574 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
575
576 get_viewport_xform(viewports + i, scale, translate);
577 scale[0] = fabsf(scale[0]);
578 scale[1] = fabsf(scale[1]);
579
580 if (scale[0] < 0.5)
581 scale[0] = 0.5;
582 if (scale[1] < 0.5)
583 scale[1] = 0.5;
584
585 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
586 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
587
588 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
589 S_028250_TL_Y(scissor.offset.y) |
590 S_028250_WINDOW_OFFSET_DISABLE(1));
591 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
592 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
593 }
594 if (!can_use_guardband) {
595 guardband_x = 1.0;
596 guardband_y = 1.0;
597 }
598
599 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
600 radeon_emit(cs, fui(guardband_y));
601 radeon_emit(cs, fui(1.0));
602 radeon_emit(cs, fui(guardband_x));
603 radeon_emit(cs, fui(1.0));
604 }
605
606 static inline unsigned
607 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
608 {
609 if (num == 0)
610 return 0;
611
612 if (info->incr == 0)
613 return 0;
614
615 if (num < info->min)
616 return 0;
617
618 return 1 + ((num - info->min) / info->incr);
619 }
620
621 uint32_t
622 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
623 bool instanced_draw, bool indirect_draw,
624 bool count_from_stream_output,
625 uint32_t draw_vertex_count)
626 {
627 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
628 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
629 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
630 const unsigned max_primgroup_in_wave = 2;
631 /* SWITCH_ON_EOP(0) is always preferable. */
632 bool wd_switch_on_eop = false;
633 bool ia_switch_on_eop = false;
634 bool ia_switch_on_eoi = false;
635 bool partial_vs_wave = false;
636 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
637 bool multi_instances_smaller_than_primgroup;
638
639 multi_instances_smaller_than_primgroup = indirect_draw;
640 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
641 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
642 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
643 multi_instances_smaller_than_primgroup = true;
644 }
645
646 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
647 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
648
649 if (chip_class >= GFX7) {
650 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
651
652 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
653 * We don't know that for indirect drawing, so treat it as
654 * always problematic. */
655 if (family == CHIP_HAWAII &&
656 (instanced_draw || indirect_draw))
657 wd_switch_on_eop = true;
658
659 /* Performance recommendation for 4 SE Gfx7-8 parts if
660 * instances are smaller than a primgroup.
661 * Assume indirect draws always use small instances.
662 * This is needed for good VS wave utilization.
663 */
664 if (chip_class <= GFX8 &&
665 info->max_se == 4 &&
666 multi_instances_smaller_than_primgroup)
667 wd_switch_on_eop = true;
668
669 /* Required on GFX7 and later. */
670 if (info->max_se > 2 && !wd_switch_on_eop)
671 ia_switch_on_eoi = true;
672
673 /* Required by Hawaii and, for some special cases, by GFX8. */
674 if (ia_switch_on_eoi &&
675 (family == CHIP_HAWAII ||
676 (chip_class == GFX8 &&
677 /* max primgroup in wave is always 2 - leave this for documentation */
678 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
679 partial_vs_wave = true;
680
681 /* Instancing bug on Bonaire. */
682 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
683 (instanced_draw || indirect_draw))
684 partial_vs_wave = true;
685
686 /* Hardware requirement when drawing primitives from a stream
687 * output buffer.
688 */
689 if (count_from_stream_output)
690 wd_switch_on_eop = true;
691
692 /* If the WD switch is false, the IA switch must be false too. */
693 assert(wd_switch_on_eop || !ia_switch_on_eop);
694 }
695 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
696 if (chip_class <= GFX8 && ia_switch_on_eoi)
697 partial_es_wave = true;
698
699 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
700 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
701 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
702 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
703 */
704 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
705 bool set_vgt_flush = indirect_draw;
706 if (!set_vgt_flush && instanced_draw) {
707 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
708 if (num_prims <= 1)
709 set_vgt_flush = true;
710 }
711 if (set_vgt_flush)
712 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
713 }
714 }
715
716 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
717 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
718 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
719 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
720 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
721 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
722
723 }
724
725 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
726 enum chip_class chip_class,
727 bool is_mec,
728 unsigned event, unsigned event_flags,
729 unsigned data_sel,
730 uint64_t va,
731 uint32_t new_fence,
732 uint64_t gfx9_eop_bug_va)
733 {
734 unsigned op = EVENT_TYPE(event) |
735 EVENT_INDEX(5) |
736 event_flags;
737 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
738 unsigned sel = EOP_DATA_SEL(data_sel);
739
740 /* Wait for write confirmation before writing data, but don't send
741 * an interrupt. */
742 if (data_sel != EOP_DATA_SEL_DISCARD)
743 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
744
745 if (chip_class >= GFX9 || is_gfx8_mec) {
746 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
747 * counters) must immediately precede every timestamp event to
748 * prevent a GPU hang on GFX9.
749 */
750 if (chip_class == GFX9 && !is_mec) {
751 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
752 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
753 radeon_emit(cs, gfx9_eop_bug_va);
754 radeon_emit(cs, gfx9_eop_bug_va >> 32);
755 }
756
757 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
758 radeon_emit(cs, op);
759 radeon_emit(cs, sel);
760 radeon_emit(cs, va); /* address lo */
761 radeon_emit(cs, va >> 32); /* address hi */
762 radeon_emit(cs, new_fence); /* immediate data lo */
763 radeon_emit(cs, 0); /* immediate data hi */
764 if (!is_gfx8_mec)
765 radeon_emit(cs, 0); /* unused */
766 } else {
767 if (chip_class == GFX7 ||
768 chip_class == GFX8) {
769 /* Two EOP events are required to make all engines go idle
770 * (and optional cache flushes executed) before the timestamp
771 * is written.
772 */
773 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
774 radeon_emit(cs, op);
775 radeon_emit(cs, va);
776 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
777 radeon_emit(cs, 0); /* immediate data */
778 radeon_emit(cs, 0); /* unused */
779 }
780
781 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
782 radeon_emit(cs, op);
783 radeon_emit(cs, va);
784 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
785 radeon_emit(cs, new_fence); /* immediate data */
786 radeon_emit(cs, 0); /* unused */
787 }
788 }
789
790 void
791 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
792 uint32_t ref, uint32_t mask)
793 {
794 assert(op == WAIT_REG_MEM_EQUAL ||
795 op == WAIT_REG_MEM_NOT_EQUAL ||
796 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
797
798 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
799 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
800 radeon_emit(cs, va);
801 radeon_emit(cs, va >> 32);
802 radeon_emit(cs, ref); /* reference value */
803 radeon_emit(cs, mask); /* mask */
804 radeon_emit(cs, 4); /* poll interval */
805 }
806
807 static void
808 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
809 bool is_mec,
810 bool is_gfx9,
811 unsigned cp_coher_cntl)
812 {
813 if (is_mec || is_gfx9) {
814 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
815 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
816 PKT3_SHADER_TYPE_S(is_mec));
817 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
818 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
819 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
820 radeon_emit(cs, 0); /* CP_COHER_BASE */
821 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
822 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
823 } else {
824 /* ACQUIRE_MEM is only required on a compute ring. */
825 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
826 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
827 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
828 radeon_emit(cs, 0); /* CP_COHER_BASE */
829 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
830 }
831 }
832
833 static void
834 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
835 enum chip_class chip_class,
836 uint32_t *flush_cnt,
837 uint64_t flush_va,
838 bool is_mec,
839 enum radv_cmd_flush_bits flush_bits,
840 uint64_t gfx9_eop_bug_va)
841 {
842 uint32_t gcr_cntl = 0;
843 unsigned cb_db_event = 0;
844
845 /* We don't need these. */
846 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_FLUSH |
847 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
848
849 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
850 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
851 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
852 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
853 * to FORWARD when both L1 and L2 are written out (WB or INV).
854 */
855 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
856 }
857 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
858 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
859 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
860 /* Writeback and invalidate everything in L2. */
861 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
862 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
863 /* Writeback but do not invalidate. */
864 gcr_cntl |= S_586_GL2_WB(1);
865 }
866
867 /* TODO: Implement this new flag for GFX9+.
868 if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
869 gcr_cntl |= S_586_GLM_INV(1);
870 */
871
872 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
873 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
874 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
875 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
876 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
877 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
878 EVENT_INDEX(0));
879 }
880
881 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
882 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
883 /* Flush HTILE. Will wait for idle later. */
884 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
885 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
886 EVENT_INDEX(0));
887 }
888
889 /* First flush CB/DB, then L1/L2. */
890 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
891
892 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
893 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
894 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
895 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
896 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
897 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
898 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
899 } else {
900 assert(0);
901 }
902 } else {
903 /* Wait for graphics shaders to go idle if requested. */
904 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
906 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
907 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
908 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
909 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
910 }
911 }
912
913 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
914 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
916 }
917
918 if (cb_db_event) {
919 /* CB/DB flush and invalidate (or possibly just a wait for a
920 * meta flush) via RELEASE_MEM.
921 *
922 * Combine this with other cache flushes when possible; this
923 * requires affected shaders to be idle, so do it after the
924 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
925 * implied).
926 */
927 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
928 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
929 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
930 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
931 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
932 assert(G_586_GL2_US(gcr_cntl) == 0);
933 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
934 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
935 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
936 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
937 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
938
939 gcr_cntl &= C_586_GLM_WB &
940 C_586_GLM_INV &
941 C_586_GLV_INV &
942 C_586_GL1_INV &
943 C_586_GL2_INV &
944 C_586_GL2_WB; /* keep SEQ */
945
946 assert(flush_cnt);
947 (*flush_cnt)++;
948
949 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
950 S_490_GLM_WB(glm_wb) |
951 S_490_GLM_INV(glm_inv) |
952 S_490_GLV_INV(glv_inv) |
953 S_490_GL1_INV(gl1_inv) |
954 S_490_GL2_INV(gl2_inv) |
955 S_490_GL2_WB(gl2_wb) |
956 S_490_SEQ(gcr_seq),
957 EOP_DATA_SEL_VALUE_32BIT,
958 flush_va, *flush_cnt,
959 gfx9_eop_bug_va);
960
961 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
962 *flush_cnt, 0xffffffff);
963 }
964
965 /* Ignore fields that only modify the behavior of other fields. */
966 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
967 /* Flush caches and wait for the caches to assert idle.
968 * The cache flush is executed in the ME, but the PFP waits
969 * for completion.
970 */
971 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
972 radeon_emit(cs, 0); /* CP_COHER_CNTL */
973 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
974 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
975 radeon_emit(cs, 0); /* CP_COHER_BASE */
976 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
977 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
978 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
979 } else if ((cb_db_event ||
980 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
981 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
982 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
983 && !is_mec) {
984 /* We need to ensure that PFP waits as well. */
985 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
986 radeon_emit(cs, 0);
987 }
988
989 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
990 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
991 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
992 EVENT_INDEX(0));
993 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
994 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
995 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
996 EVENT_INDEX(0));
997 }
998 }
999
1000 void
1001 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1002 enum chip_class chip_class,
1003 uint32_t *flush_cnt,
1004 uint64_t flush_va,
1005 bool is_mec,
1006 enum radv_cmd_flush_bits flush_bits,
1007 uint64_t gfx9_eop_bug_va)
1008 {
1009 unsigned cp_coher_cntl = 0;
1010 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1011 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1012
1013 if (chip_class >= GFX10) {
1014 /* GFX10 cache flush handling is quite different. */
1015 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1016 is_mec, flush_bits, gfx9_eop_bug_va);
1017 return;
1018 }
1019
1020 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1021 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1022 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1023 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1024
1025 if (chip_class <= GFX8) {
1026 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1027 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1028 S_0085F0_CB0_DEST_BASE_ENA(1) |
1029 S_0085F0_CB1_DEST_BASE_ENA(1) |
1030 S_0085F0_CB2_DEST_BASE_ENA(1) |
1031 S_0085F0_CB3_DEST_BASE_ENA(1) |
1032 S_0085F0_CB4_DEST_BASE_ENA(1) |
1033 S_0085F0_CB5_DEST_BASE_ENA(1) |
1034 S_0085F0_CB6_DEST_BASE_ENA(1) |
1035 S_0085F0_CB7_DEST_BASE_ENA(1);
1036
1037 /* Necessary for DCC */
1038 if (chip_class >= GFX8) {
1039 si_cs_emit_write_event_eop(cs,
1040 chip_class,
1041 is_mec,
1042 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1043 0,
1044 EOP_DATA_SEL_DISCARD,
1045 0, 0,
1046 gfx9_eop_bug_va);
1047 }
1048 }
1049 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1050 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1051 S_0085F0_DB_DEST_BASE_ENA(1);
1052 }
1053 }
1054
1055 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1056 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1057 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1058 }
1059
1060 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1061 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1062 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1063 }
1064
1065 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1066 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1067 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1068 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1069 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1070 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1071 }
1072
1073 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1074 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1075 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1076 }
1077
1078 if (chip_class >= GFX9 && flush_cb_db) {
1079 unsigned cb_db_event, tc_flags;
1080
1081 /* Set the CB/DB flush event. */
1082 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1083
1084 /* These are the only allowed combinations. If you need to
1085 * do multiple operations at once, do them separately.
1086 * All operations that invalidate L2 also seem to invalidate
1087 * metadata. Volatile (VOL) and WC flushes are not listed here.
1088 *
1089 * TC | TC_WB = writeback & invalidate L2 & L1
1090 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1091 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1092 * TC | TC_NC = invalidate L2 for MTYPE == NC
1093 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1094 * TCL1 = invalidate L1
1095 */
1096 tc_flags = EVENT_TC_ACTION_ENA |
1097 EVENT_TC_MD_ACTION_ENA;
1098
1099 /* Ideally flush TC together with CB/DB. */
1100 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1101 /* Writeback and invalidate everything in L2 & L1. */
1102 tc_flags = EVENT_TC_ACTION_ENA |
1103 EVENT_TC_WB_ACTION_ENA;
1104
1105
1106 /* Clear the flags. */
1107 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1108 RADV_CMD_FLAG_WB_L2 |
1109 RADV_CMD_FLAG_INV_VCACHE);
1110 }
1111 assert(flush_cnt);
1112 (*flush_cnt)++;
1113
1114 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1115 EOP_DATA_SEL_VALUE_32BIT,
1116 flush_va, *flush_cnt,
1117 gfx9_eop_bug_va);
1118 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1119 *flush_cnt, 0xffffffff);
1120 }
1121
1122 /* VGT state sync */
1123 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1125 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1126 }
1127
1128 /* VGT streamout state sync */
1129 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1131 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1132 }
1133
1134 /* Make sure ME is idle (it executes most packets) before continuing.
1135 * This prevents read-after-write hazards between PFP and ME.
1136 */
1137 if ((cp_coher_cntl ||
1138 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1139 RADV_CMD_FLAG_INV_VCACHE |
1140 RADV_CMD_FLAG_INV_L2 |
1141 RADV_CMD_FLAG_WB_L2))) &&
1142 !is_mec) {
1143 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1144 radeon_emit(cs, 0);
1145 }
1146
1147 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1148 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1149 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
1150 cp_coher_cntl |
1151 S_0085F0_TC_ACTION_ENA(1) |
1152 S_0085F0_TCL1_ACTION_ENA(1) |
1153 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1154 cp_coher_cntl = 0;
1155 } else {
1156 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1157 /* WB = write-back
1158 * NC = apply to non-coherent MTYPEs
1159 * (i.e. MTYPE <= 1, which is what we use everywhere)
1160 *
1161 * WB doesn't work without NC.
1162 */
1163 si_emit_acquire_mem(cs, is_mec,
1164 chip_class >= GFX9,
1165 cp_coher_cntl |
1166 S_0301F0_TC_WB_ACTION_ENA(1) |
1167 S_0301F0_TC_NC_ACTION_ENA(1));
1168 cp_coher_cntl = 0;
1169 }
1170 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1171 si_emit_acquire_mem(cs, is_mec,
1172 chip_class >= GFX9,
1173 cp_coher_cntl |
1174 S_0085F0_TCL1_ACTION_ENA(1));
1175 cp_coher_cntl = 0;
1176 }
1177 }
1178
1179 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1180 * Therefore, it should be last. Done in PFP.
1181 */
1182 if (cp_coher_cntl)
1183 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
1184
1185 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1186 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1187 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1188 EVENT_INDEX(0));
1189 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1190 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1191 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1192 EVENT_INDEX(0));
1193 }
1194 }
1195
1196 void
1197 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1198 {
1199 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1200
1201 if (is_compute)
1202 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1203 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1204 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1205 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1206 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1207 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1208 RADV_CMD_FLAG_VGT_FLUSH |
1209 RADV_CMD_FLAG_START_PIPELINE_STATS |
1210 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1211
1212 if (!cmd_buffer->state.flush_bits)
1213 return;
1214
1215 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1216
1217 si_cs_emit_cache_flush(cmd_buffer->cs,
1218 cmd_buffer->device->physical_device->rad_info.chip_class,
1219 &cmd_buffer->gfx9_fence_idx,
1220 cmd_buffer->gfx9_fence_va,
1221 radv_cmd_buffer_uses_mec(cmd_buffer),
1222 cmd_buffer->state.flush_bits,
1223 cmd_buffer->gfx9_eop_bug_va);
1224
1225
1226 if (unlikely(cmd_buffer->device->trace_bo))
1227 radv_cmd_buffer_trace_emit(cmd_buffer);
1228
1229 /* Clear the caches that have been flushed to avoid syncing too much
1230 * when there is some pending active queries.
1231 */
1232 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1233
1234 cmd_buffer->state.flush_bits = 0;
1235
1236 /* If the driver used a compute shader for resetting a query pool, it
1237 * should be finished at this point.
1238 */
1239 cmd_buffer->pending_reset_query = false;
1240 }
1241
1242 /* sets the CP predication state using a boolean stored at va */
1243 void
1244 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1245 bool draw_visible, uint64_t va)
1246 {
1247 uint32_t op = 0;
1248
1249 if (va) {
1250 op = PRED_OP(PREDICATION_OP_BOOL64);
1251
1252 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1253 * zero, all rendering commands are discarded. Otherwise, they
1254 * are discarded if the value is non zero.
1255 */
1256 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1257 PREDICATION_DRAW_NOT_VISIBLE;
1258 }
1259 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1260 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1261 radeon_emit(cmd_buffer->cs, op);
1262 radeon_emit(cmd_buffer->cs, va);
1263 radeon_emit(cmd_buffer->cs, va >> 32);
1264 } else {
1265 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1266 radeon_emit(cmd_buffer->cs, va);
1267 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1268 }
1269 }
1270
1271 /* Set this if you want the 3D engine to wait until CP DMA is done.
1272 * It should be set on the last CP DMA packet. */
1273 #define CP_DMA_SYNC (1 << 0)
1274
1275 /* Set this if the source data was used as a destination in a previous CP DMA
1276 * packet. It's for preventing a read-after-write (RAW) hazard between two
1277 * CP DMA packets. */
1278 #define CP_DMA_RAW_WAIT (1 << 1)
1279 #define CP_DMA_USE_L2 (1 << 2)
1280 #define CP_DMA_CLEAR (1 << 3)
1281
1282 /* Alignment for optimal performance. */
1283 #define SI_CPDMA_ALIGNMENT 32
1284
1285 /* The max number of bytes that can be copied per packet. */
1286 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1287 {
1288 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1289 S_414_BYTE_COUNT_GFX9(~0u) :
1290 S_414_BYTE_COUNT_GFX6(~0u);
1291
1292 /* make it aligned for optimal performance */
1293 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1294 }
1295
1296 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1297 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1298 * clear value.
1299 */
1300 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1301 uint64_t dst_va, uint64_t src_va,
1302 unsigned size, unsigned flags)
1303 {
1304 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1305 uint32_t header = 0, command = 0;
1306
1307 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1308
1309 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1310 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1311 command |= S_414_BYTE_COUNT_GFX9(size);
1312 else
1313 command |= S_414_BYTE_COUNT_GFX6(size);
1314
1315 /* Sync flags. */
1316 if (flags & CP_DMA_SYNC)
1317 header |= S_411_CP_SYNC(1);
1318 else {
1319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1320 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1321 else
1322 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1323 }
1324
1325 if (flags & CP_DMA_RAW_WAIT)
1326 command |= S_414_RAW_WAIT(1);
1327
1328 /* Src and dst flags. */
1329 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1330 !(flags & CP_DMA_CLEAR) &&
1331 src_va == dst_va)
1332 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1333 else if (flags & CP_DMA_USE_L2)
1334 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1335
1336 if (flags & CP_DMA_CLEAR)
1337 header |= S_411_SRC_SEL(V_411_DATA);
1338 else if (flags & CP_DMA_USE_L2)
1339 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1340
1341 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1342 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1343 radeon_emit(cs, header);
1344 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1345 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1346 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1347 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1348 radeon_emit(cs, command);
1349 } else {
1350 assert(!(flags & CP_DMA_USE_L2));
1351 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1352 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1353 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1354 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1355 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1356 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1357 radeon_emit(cs, command);
1358 }
1359
1360 /* CP DMA is executed in ME, but index buffers are read by PFP.
1361 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1362 * indices. If we wanted to execute CP DMA in PFP, this packet
1363 * should precede it.
1364 */
1365 if (flags & CP_DMA_SYNC) {
1366 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1367 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1368 radeon_emit(cs, 0);
1369 }
1370
1371 /* CP will see the sync flag and wait for all DMAs to complete. */
1372 cmd_buffer->state.dma_is_busy = false;
1373 }
1374
1375 if (unlikely(cmd_buffer->device->trace_bo))
1376 radv_cmd_buffer_trace_emit(cmd_buffer);
1377 }
1378
1379 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1380 unsigned size)
1381 {
1382 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1383 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1384
1385 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1386 aligned_size, CP_DMA_USE_L2);
1387 }
1388
1389 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1390 uint64_t remaining_size, unsigned *flags)
1391 {
1392
1393 /* Flush the caches for the first copy only.
1394 * Also wait for the previous CP DMA operations.
1395 */
1396 if (cmd_buffer->state.flush_bits) {
1397 si_emit_cache_flush(cmd_buffer);
1398 *flags |= CP_DMA_RAW_WAIT;
1399 }
1400
1401 /* Do the synchronization after the last dma, so that all data
1402 * is written to memory.
1403 */
1404 if (byte_count == remaining_size)
1405 *flags |= CP_DMA_SYNC;
1406 }
1407
1408 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1409 {
1410 uint64_t va;
1411 uint32_t offset;
1412 unsigned dma_flags = 0;
1413 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1414 void *ptr;
1415
1416 assert(size < SI_CPDMA_ALIGNMENT);
1417
1418 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1419
1420 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1421 va += offset;
1422
1423 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1424
1425 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1426 dma_flags);
1427 }
1428
1429 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1430 uint64_t src_va, uint64_t dest_va,
1431 uint64_t size)
1432 {
1433 uint64_t main_src_va, main_dest_va;
1434 uint64_t skipped_size = 0, realign_size = 0;
1435
1436 /* Assume that we are not going to sync after the last DMA operation. */
1437 cmd_buffer->state.dma_is_busy = true;
1438
1439 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1440 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1441 /* If the size is not aligned, we must add a dummy copy at the end
1442 * just to align the internal counter. Otherwise, the DMA engine
1443 * would slow down by an order of magnitude for following copies.
1444 */
1445 if (size % SI_CPDMA_ALIGNMENT)
1446 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1447
1448 /* If the copy begins unaligned, we must start copying from the next
1449 * aligned block and the skipped part should be copied after everything
1450 * else has been copied. Only the src alignment matters, not dst.
1451 */
1452 if (src_va % SI_CPDMA_ALIGNMENT) {
1453 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1454 /* The main part will be skipped if the size is too small. */
1455 skipped_size = MIN2(skipped_size, size);
1456 size -= skipped_size;
1457 }
1458 }
1459 main_src_va = src_va + skipped_size;
1460 main_dest_va = dest_va + skipped_size;
1461
1462 while (size) {
1463 unsigned dma_flags = 0;
1464 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1465
1466 si_cp_dma_prepare(cmd_buffer, byte_count,
1467 size + skipped_size + realign_size,
1468 &dma_flags);
1469
1470 dma_flags &= ~CP_DMA_SYNC;
1471
1472 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1473 byte_count, dma_flags);
1474
1475 size -= byte_count;
1476 main_src_va += byte_count;
1477 main_dest_va += byte_count;
1478 }
1479
1480 if (skipped_size) {
1481 unsigned dma_flags = 0;
1482
1483 si_cp_dma_prepare(cmd_buffer, skipped_size,
1484 size + skipped_size + realign_size,
1485 &dma_flags);
1486
1487 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1488 skipped_size, dma_flags);
1489 }
1490 if (realign_size)
1491 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1492 }
1493
1494 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1495 uint64_t size, unsigned value)
1496 {
1497
1498 if (!size)
1499 return;
1500
1501 assert(va % 4 == 0 && size % 4 == 0);
1502
1503 /* Assume that we are not going to sync after the last DMA operation. */
1504 cmd_buffer->state.dma_is_busy = true;
1505
1506 while (size) {
1507 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1508 unsigned dma_flags = CP_DMA_CLEAR;
1509
1510 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1511
1512 /* Emit the clear packet. */
1513 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1514 dma_flags);
1515
1516 size -= byte_count;
1517 va += byte_count;
1518 }
1519 }
1520
1521 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1522 {
1523 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1524 return;
1525
1526 if (!cmd_buffer->state.dma_is_busy)
1527 return;
1528
1529 /* Issue a dummy DMA that copies zero bytes.
1530 *
1531 * The DMA engine will see that there's no work to do and skip this
1532 * DMA request, however, the CP will see the sync flag and still wait
1533 * for all DMAs to complete.
1534 */
1535 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1536
1537 cmd_buffer->state.dma_is_busy = false;
1538 }
1539
1540 /* For MSAA sample positions. */
1541 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1542 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1543 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1544 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1545 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1546
1547 /* For obtaining location coordinates from registers */
1548 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1549 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1550 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1551 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1552
1553 /* 1x MSAA */
1554 static const uint32_t sample_locs_1x =
1555 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1556 static const unsigned max_dist_1x = 0;
1557 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1558
1559 /* 2xMSAA */
1560 static const uint32_t sample_locs_2x =
1561 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1562 static const unsigned max_dist_2x = 4;
1563 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1564
1565 /* 4xMSAA */
1566 static const uint32_t sample_locs_4x =
1567 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1568 static const unsigned max_dist_4x = 6;
1569 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1570
1571 /* 8xMSAA */
1572 static const uint32_t sample_locs_8x[] = {
1573 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1574 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1575 /* The following are unused by hardware, but we emit them to IBs
1576 * instead of multiple SET_CONTEXT_REG packets. */
1577 0,
1578 0,
1579 };
1580 static const unsigned max_dist_8x = 7;
1581 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1582
1583 unsigned radv_get_default_max_sample_dist(int log_samples)
1584 {
1585 unsigned max_dist[] = {
1586 max_dist_1x,
1587 max_dist_2x,
1588 max_dist_4x,
1589 max_dist_8x,
1590 };
1591 return max_dist[log_samples];
1592 }
1593
1594 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1595 {
1596 switch (nr_samples) {
1597 default:
1598 case 1:
1599 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1600 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1601 radeon_emit(cs, centroid_priority_1x >> 32);
1602 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1603 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1604 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1605 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1606 break;
1607 case 2:
1608 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1609 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1610 radeon_emit(cs, centroid_priority_2x >> 32);
1611 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1612 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1613 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1614 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1615 break;
1616 case 4:
1617 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1618 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1619 radeon_emit(cs, centroid_priority_4x >> 32);
1620 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1621 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1622 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1623 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1624 break;
1625 case 8:
1626 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1627 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1628 radeon_emit(cs, centroid_priority_8x >> 32);
1629 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1630 radeon_emit_array(cs, sample_locs_8x, 4);
1631 radeon_emit_array(cs, sample_locs_8x, 4);
1632 radeon_emit_array(cs, sample_locs_8x, 4);
1633 radeon_emit_array(cs, sample_locs_8x, 2);
1634 break;
1635 }
1636 }
1637
1638 static void radv_get_sample_position(struct radv_device *device,
1639 unsigned sample_count,
1640 unsigned sample_index, float *out_value)
1641 {
1642 const uint32_t *sample_locs;
1643
1644 switch (sample_count) {
1645 case 1:
1646 default:
1647 sample_locs = &sample_locs_1x;
1648 break;
1649 case 2:
1650 sample_locs = &sample_locs_2x;
1651 break;
1652 case 4:
1653 sample_locs = &sample_locs_4x;
1654 break;
1655 case 8:
1656 sample_locs = sample_locs_8x;
1657 break;
1658 }
1659
1660 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1661 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1662 }
1663
1664 void radv_device_init_msaa(struct radv_device *device)
1665 {
1666 int i;
1667
1668 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1669
1670 for (i = 0; i < 2; i++)
1671 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1672 for (i = 0; i < 4; i++)
1673 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1674 for (i = 0; i < 8; i++)
1675 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1676 }